1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "hw/sysbus.h" 22 #include "gic_internal.h" 23 #include "qom/cpu.h" 24 25 //#define DEBUG_GIC 26 27 #ifdef DEBUG_GIC 28 #define DPRINTF(fmt, ...) \ 29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) 30 #else 31 #define DPRINTF(fmt, ...) do {} while(0) 32 #endif 33 34 static const uint8_t gic_id[] = { 35 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 36 }; 37 38 #define NUM_CPU(s) ((s)->num_cpu) 39 40 static inline int gic_get_current_cpu(GICState *s) 41 { 42 if (s->num_cpu > 1) { 43 return current_cpu->cpu_index; 44 } 45 return 0; 46 } 47 48 /* TODO: Many places that call this routine could be optimized. */ 49 /* Update interrupt status after enabled or pending bits have been changed. */ 50 void gic_update(GICState *s) 51 { 52 int best_irq; 53 int best_prio; 54 int irq; 55 int level; 56 int cpu; 57 int cm; 58 59 for (cpu = 0; cpu < NUM_CPU(s); cpu++) { 60 cm = 1 << cpu; 61 s->current_pending[cpu] = 1023; 62 if (!s->enabled || !s->cpu_enabled[cpu]) { 63 qemu_irq_lower(s->parent_irq[cpu]); 64 return; 65 } 66 best_prio = 0x100; 67 best_irq = 1023; 68 for (irq = 0; irq < s->num_irq; irq++) { 69 if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) { 70 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 71 best_prio = GIC_GET_PRIORITY(irq, cpu); 72 best_irq = irq; 73 } 74 } 75 } 76 level = 0; 77 if (best_prio < s->priority_mask[cpu]) { 78 s->current_pending[cpu] = best_irq; 79 if (best_prio < s->running_priority[cpu]) { 80 DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu); 81 level = 1; 82 } 83 } 84 qemu_set_irq(s->parent_irq[cpu], level); 85 } 86 } 87 88 void gic_set_pending_private(GICState *s, int cpu, int irq) 89 { 90 int cm = 1 << cpu; 91 92 if (GIC_TEST_PENDING(irq, cm)) 93 return; 94 95 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 96 GIC_SET_PENDING(irq, cm); 97 gic_update(s); 98 } 99 100 /* Process a change in an external IRQ input. */ 101 static void gic_set_irq(void *opaque, int irq, int level) 102 { 103 /* Meaning of the 'irq' parameter: 104 * [0..N-1] : external interrupts 105 * [N..N+31] : PPI (internal) interrupts for CPU 0 106 * [N+32..N+63] : PPI (internal interrupts for CPU 1 107 * ... 108 */ 109 GICState *s = (GICState *)opaque; 110 int cm, target; 111 if (irq < (s->num_irq - GIC_INTERNAL)) { 112 /* The first external input line is internal interrupt 32. */ 113 cm = ALL_CPU_MASK; 114 irq += GIC_INTERNAL; 115 target = GIC_TARGET(irq); 116 } else { 117 int cpu; 118 irq -= (s->num_irq - GIC_INTERNAL); 119 cpu = irq / GIC_INTERNAL; 120 irq %= GIC_INTERNAL; 121 cm = 1 << cpu; 122 target = cm; 123 } 124 125 if (level == GIC_TEST_LEVEL(irq, cm)) { 126 return; 127 } 128 129 if (level) { 130 GIC_SET_LEVEL(irq, cm); 131 if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 132 DPRINTF("Set %d pending mask %x\n", irq, target); 133 GIC_SET_PENDING(irq, target); 134 } 135 } else { 136 GIC_CLEAR_LEVEL(irq, cm); 137 } 138 gic_update(s); 139 } 140 141 static void gic_set_running_irq(GICState *s, int cpu, int irq) 142 { 143 s->running_irq[cpu] = irq; 144 if (irq == 1023) { 145 s->running_priority[cpu] = 0x100; 146 } else { 147 s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); 148 } 149 gic_update(s); 150 } 151 152 uint32_t gic_acknowledge_irq(GICState *s, int cpu) 153 { 154 int new_irq; 155 int cm = 1 << cpu; 156 new_irq = s->current_pending[cpu]; 157 if (new_irq == 1023 158 || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { 159 DPRINTF("ACK no pending IRQ\n"); 160 return 1023; 161 } 162 s->last_active[new_irq][cpu] = s->running_irq[cpu]; 163 /* Clear pending flags for both level and edge triggered interrupts. 164 Level triggered IRQs will be reasserted once they become inactive. */ 165 GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); 166 gic_set_running_irq(s, cpu, new_irq); 167 DPRINTF("ACK %d\n", new_irq); 168 return new_irq; 169 } 170 171 void gic_complete_irq(GICState *s, int cpu, int irq) 172 { 173 int update = 0; 174 int cm = 1 << cpu; 175 DPRINTF("EOI %d\n", irq); 176 if (irq >= s->num_irq) { 177 /* This handles two cases: 178 * 1. If software writes the ID of a spurious interrupt [ie 1023] 179 * to the GICC_EOIR, the GIC ignores that write. 180 * 2. If software writes the number of a non-existent interrupt 181 * this must be a subcase of "value written does not match the last 182 * valid interrupt value read from the Interrupt Acknowledge 183 * register" and so this is UNPREDICTABLE. We choose to ignore it. 184 */ 185 return; 186 } 187 if (s->running_irq[cpu] == 1023) 188 return; /* No active IRQ. */ 189 /* Mark level triggered interrupts as pending if they are still 190 raised. */ 191 if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 192 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 193 DPRINTF("Set %d pending mask %x\n", irq, cm); 194 GIC_SET_PENDING(irq, cm); 195 update = 1; 196 } 197 if (irq != s->running_irq[cpu]) { 198 /* Complete an IRQ that is not currently running. */ 199 int tmp = s->running_irq[cpu]; 200 while (s->last_active[tmp][cpu] != 1023) { 201 if (s->last_active[tmp][cpu] == irq) { 202 s->last_active[tmp][cpu] = s->last_active[irq][cpu]; 203 break; 204 } 205 tmp = s->last_active[tmp][cpu]; 206 } 207 if (update) { 208 gic_update(s); 209 } 210 } else { 211 /* Complete the current running IRQ. */ 212 gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); 213 } 214 } 215 216 static uint32_t gic_dist_readb(void *opaque, hwaddr offset) 217 { 218 GICState *s = (GICState *)opaque; 219 uint32_t res; 220 int irq; 221 int i; 222 int cpu; 223 int cm; 224 int mask; 225 226 cpu = gic_get_current_cpu(s); 227 cm = 1 << cpu; 228 if (offset < 0x100) { 229 if (offset == 0) 230 return s->enabled; 231 if (offset == 4) 232 return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); 233 if (offset < 0x08) 234 return 0; 235 if (offset >= 0x80) { 236 /* Interrupt Security , RAZ/WI */ 237 return 0; 238 } 239 goto bad_reg; 240 } else if (offset < 0x200) { 241 /* Interrupt Set/Clear Enable. */ 242 if (offset < 0x180) 243 irq = (offset - 0x100) * 8; 244 else 245 irq = (offset - 0x180) * 8; 246 irq += GIC_BASE_IRQ; 247 if (irq >= s->num_irq) 248 goto bad_reg; 249 res = 0; 250 for (i = 0; i < 8; i++) { 251 if (GIC_TEST_ENABLED(irq + i, cm)) { 252 res |= (1 << i); 253 } 254 } 255 } else if (offset < 0x300) { 256 /* Interrupt Set/Clear Pending. */ 257 if (offset < 0x280) 258 irq = (offset - 0x200) * 8; 259 else 260 irq = (offset - 0x280) * 8; 261 irq += GIC_BASE_IRQ; 262 if (irq >= s->num_irq) 263 goto bad_reg; 264 res = 0; 265 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 266 for (i = 0; i < 8; i++) { 267 if (GIC_TEST_PENDING(irq + i, mask)) { 268 res |= (1 << i); 269 } 270 } 271 } else if (offset < 0x400) { 272 /* Interrupt Active. */ 273 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 274 if (irq >= s->num_irq) 275 goto bad_reg; 276 res = 0; 277 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 278 for (i = 0; i < 8; i++) { 279 if (GIC_TEST_ACTIVE(irq + i, mask)) { 280 res |= (1 << i); 281 } 282 } 283 } else if (offset < 0x800) { 284 /* Interrupt Priority. */ 285 irq = (offset - 0x400) + GIC_BASE_IRQ; 286 if (irq >= s->num_irq) 287 goto bad_reg; 288 res = GIC_GET_PRIORITY(irq, cpu); 289 } else if (offset < 0xc00) { 290 /* Interrupt CPU Target. */ 291 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 292 /* For uniprocessor GICs these RAZ/WI */ 293 res = 0; 294 } else { 295 irq = (offset - 0x800) + GIC_BASE_IRQ; 296 if (irq >= s->num_irq) { 297 goto bad_reg; 298 } 299 if (irq >= 29 && irq <= 31) { 300 res = cm; 301 } else { 302 res = GIC_TARGET(irq); 303 } 304 } 305 } else if (offset < 0xf00) { 306 /* Interrupt Configuration. */ 307 irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; 308 if (irq >= s->num_irq) 309 goto bad_reg; 310 res = 0; 311 for (i = 0; i < 4; i++) { 312 if (GIC_TEST_MODEL(irq + i)) 313 res |= (1 << (i * 2)); 314 if (GIC_TEST_TRIGGER(irq + i)) 315 res |= (2 << (i * 2)); 316 } 317 } else if (offset < 0xfe0) { 318 goto bad_reg; 319 } else /* offset >= 0xfe0 */ { 320 if (offset & 3) { 321 res = 0; 322 } else { 323 res = gic_id[(offset - 0xfe0) >> 2]; 324 } 325 } 326 return res; 327 bad_reg: 328 qemu_log_mask(LOG_GUEST_ERROR, 329 "gic_dist_readb: Bad offset %x\n", (int)offset); 330 return 0; 331 } 332 333 static uint32_t gic_dist_readw(void *opaque, hwaddr offset) 334 { 335 uint32_t val; 336 val = gic_dist_readb(opaque, offset); 337 val |= gic_dist_readb(opaque, offset + 1) << 8; 338 return val; 339 } 340 341 static uint32_t gic_dist_readl(void *opaque, hwaddr offset) 342 { 343 uint32_t val; 344 val = gic_dist_readw(opaque, offset); 345 val |= gic_dist_readw(opaque, offset + 2) << 16; 346 return val; 347 } 348 349 static void gic_dist_writeb(void *opaque, hwaddr offset, 350 uint32_t value) 351 { 352 GICState *s = (GICState *)opaque; 353 int irq; 354 int i; 355 int cpu; 356 357 cpu = gic_get_current_cpu(s); 358 if (offset < 0x100) { 359 if (offset == 0) { 360 s->enabled = (value & 1); 361 DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); 362 } else if (offset < 4) { 363 /* ignored. */ 364 } else if (offset >= 0x80) { 365 /* Interrupt Security Registers, RAZ/WI */ 366 } else { 367 goto bad_reg; 368 } 369 } else if (offset < 0x180) { 370 /* Interrupt Set Enable. */ 371 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 372 if (irq >= s->num_irq) 373 goto bad_reg; 374 if (irq < 16) 375 value = 0xff; 376 for (i = 0; i < 8; i++) { 377 if (value & (1 << i)) { 378 int mask = 379 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 380 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 381 382 if (!GIC_TEST_ENABLED(irq + i, cm)) { 383 DPRINTF("Enabled IRQ %d\n", irq + i); 384 } 385 GIC_SET_ENABLED(irq + i, cm); 386 /* If a raised level triggered IRQ enabled then mark 387 is as pending. */ 388 if (GIC_TEST_LEVEL(irq + i, mask) 389 && !GIC_TEST_TRIGGER(irq + i)) { 390 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 391 GIC_SET_PENDING(irq + i, mask); 392 } 393 } 394 } 395 } else if (offset < 0x200) { 396 /* Interrupt Clear Enable. */ 397 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 398 if (irq >= s->num_irq) 399 goto bad_reg; 400 if (irq < 16) 401 value = 0; 402 for (i = 0; i < 8; i++) { 403 if (value & (1 << i)) { 404 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 405 406 if (GIC_TEST_ENABLED(irq + i, cm)) { 407 DPRINTF("Disabled IRQ %d\n", irq + i); 408 } 409 GIC_CLEAR_ENABLED(irq + i, cm); 410 } 411 } 412 } else if (offset < 0x280) { 413 /* Interrupt Set Pending. */ 414 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 415 if (irq >= s->num_irq) 416 goto bad_reg; 417 if (irq < 16) 418 irq = 0; 419 420 for (i = 0; i < 8; i++) { 421 if (value & (1 << i)) { 422 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 423 } 424 } 425 } else if (offset < 0x300) { 426 /* Interrupt Clear Pending. */ 427 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 428 if (irq >= s->num_irq) 429 goto bad_reg; 430 for (i = 0; i < 8; i++) { 431 /* ??? This currently clears the pending bit for all CPUs, even 432 for per-CPU interrupts. It's unclear whether this is the 433 corect behavior. */ 434 if (value & (1 << i)) { 435 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 436 } 437 } 438 } else if (offset < 0x400) { 439 /* Interrupt Active. */ 440 goto bad_reg; 441 } else if (offset < 0x800) { 442 /* Interrupt Priority. */ 443 irq = (offset - 0x400) + GIC_BASE_IRQ; 444 if (irq >= s->num_irq) 445 goto bad_reg; 446 if (irq < GIC_INTERNAL) { 447 s->priority1[irq][cpu] = value; 448 } else { 449 s->priority2[irq - GIC_INTERNAL] = value; 450 } 451 } else if (offset < 0xc00) { 452 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 453 * annoying exception of the 11MPCore's GIC. 454 */ 455 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 456 irq = (offset - 0x800) + GIC_BASE_IRQ; 457 if (irq >= s->num_irq) { 458 goto bad_reg; 459 } 460 if (irq < 29) { 461 value = 0; 462 } else if (irq < GIC_INTERNAL) { 463 value = ALL_CPU_MASK; 464 } 465 s->irq_target[irq] = value & ALL_CPU_MASK; 466 } 467 } else if (offset < 0xf00) { 468 /* Interrupt Configuration. */ 469 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 470 if (irq >= s->num_irq) 471 goto bad_reg; 472 if (irq < GIC_INTERNAL) 473 value |= 0xaa; 474 for (i = 0; i < 4; i++) { 475 if (value & (1 << (i * 2))) { 476 GIC_SET_MODEL(irq + i); 477 } else { 478 GIC_CLEAR_MODEL(irq + i); 479 } 480 if (value & (2 << (i * 2))) { 481 GIC_SET_TRIGGER(irq + i); 482 } else { 483 GIC_CLEAR_TRIGGER(irq + i); 484 } 485 } 486 } else { 487 /* 0xf00 is only handled for 32-bit writes. */ 488 goto bad_reg; 489 } 490 gic_update(s); 491 return; 492 bad_reg: 493 qemu_log_mask(LOG_GUEST_ERROR, 494 "gic_dist_writeb: Bad offset %x\n", (int)offset); 495 } 496 497 static void gic_dist_writew(void *opaque, hwaddr offset, 498 uint32_t value) 499 { 500 gic_dist_writeb(opaque, offset, value & 0xff); 501 gic_dist_writeb(opaque, offset + 1, value >> 8); 502 } 503 504 static void gic_dist_writel(void *opaque, hwaddr offset, 505 uint32_t value) 506 { 507 GICState *s = (GICState *)opaque; 508 if (offset == 0xf00) { 509 int cpu; 510 int irq; 511 int mask; 512 513 cpu = gic_get_current_cpu(s); 514 irq = value & 0x3ff; 515 switch ((value >> 24) & 3) { 516 case 0: 517 mask = (value >> 16) & ALL_CPU_MASK; 518 break; 519 case 1: 520 mask = ALL_CPU_MASK ^ (1 << cpu); 521 break; 522 case 2: 523 mask = 1 << cpu; 524 break; 525 default: 526 DPRINTF("Bad Soft Int target filter\n"); 527 mask = ALL_CPU_MASK; 528 break; 529 } 530 GIC_SET_PENDING(irq, mask); 531 gic_update(s); 532 return; 533 } 534 gic_dist_writew(opaque, offset, value & 0xffff); 535 gic_dist_writew(opaque, offset + 2, value >> 16); 536 } 537 538 static const MemoryRegionOps gic_dist_ops = { 539 .old_mmio = { 540 .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, }, 541 .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, }, 542 }, 543 .endianness = DEVICE_NATIVE_ENDIAN, 544 }; 545 546 static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) 547 { 548 switch (offset) { 549 case 0x00: /* Control */ 550 return s->cpu_enabled[cpu]; 551 case 0x04: /* Priority mask */ 552 return s->priority_mask[cpu]; 553 case 0x08: /* Binary Point */ 554 /* ??? Not implemented. */ 555 return 0; 556 case 0x0c: /* Acknowledge */ 557 return gic_acknowledge_irq(s, cpu); 558 case 0x14: /* Running Priority */ 559 return s->running_priority[cpu]; 560 case 0x18: /* Highest Pending Interrupt */ 561 return s->current_pending[cpu]; 562 default: 563 qemu_log_mask(LOG_GUEST_ERROR, 564 "gic_cpu_read: Bad offset %x\n", (int)offset); 565 return 0; 566 } 567 } 568 569 static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) 570 { 571 switch (offset) { 572 case 0x00: /* Control */ 573 s->cpu_enabled[cpu] = (value & 1); 574 DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled[cpu] ? "En" : "Dis"); 575 break; 576 case 0x04: /* Priority mask */ 577 s->priority_mask[cpu] = (value & 0xff); 578 break; 579 case 0x08: /* Binary Point */ 580 /* ??? Not implemented. */ 581 break; 582 case 0x10: /* End Of Interrupt */ 583 return gic_complete_irq(s, cpu, value & 0x3ff); 584 default: 585 qemu_log_mask(LOG_GUEST_ERROR, 586 "gic_cpu_write: Bad offset %x\n", (int)offset); 587 return; 588 } 589 gic_update(s); 590 } 591 592 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 593 static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr, 594 unsigned size) 595 { 596 GICState *s = (GICState *)opaque; 597 return gic_cpu_read(s, gic_get_current_cpu(s), addr); 598 } 599 600 static void gic_thiscpu_write(void *opaque, hwaddr addr, 601 uint64_t value, unsigned size) 602 { 603 GICState *s = (GICState *)opaque; 604 gic_cpu_write(s, gic_get_current_cpu(s), addr, value); 605 } 606 607 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 608 * These just decode the opaque pointer into GICState* + cpu id. 609 */ 610 static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr, 611 unsigned size) 612 { 613 GICState **backref = (GICState **)opaque; 614 GICState *s = *backref; 615 int id = (backref - s->backref); 616 return gic_cpu_read(s, id, addr); 617 } 618 619 static void gic_do_cpu_write(void *opaque, hwaddr addr, 620 uint64_t value, unsigned size) 621 { 622 GICState **backref = (GICState **)opaque; 623 GICState *s = *backref; 624 int id = (backref - s->backref); 625 gic_cpu_write(s, id, addr, value); 626 } 627 628 static const MemoryRegionOps gic_thiscpu_ops = { 629 .read = gic_thiscpu_read, 630 .write = gic_thiscpu_write, 631 .endianness = DEVICE_NATIVE_ENDIAN, 632 }; 633 634 static const MemoryRegionOps gic_cpu_ops = { 635 .read = gic_do_cpu_read, 636 .write = gic_do_cpu_write, 637 .endianness = DEVICE_NATIVE_ENDIAN, 638 }; 639 640 void gic_init_irqs_and_distributor(GICState *s, int num_irq) 641 { 642 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 643 int i; 644 645 i = s->num_irq - GIC_INTERNAL; 646 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 647 * GPIO array layout is thus: 648 * [0..N-1] SPIs 649 * [N..N+31] PPIs for CPU 0 650 * [N+32..N+63] PPIs for CPU 1 651 * ... 652 */ 653 if (s->revision != REV_NVIC) { 654 i += (GIC_INTERNAL * s->num_cpu); 655 } 656 qdev_init_gpio_in(DEVICE(s), gic_set_irq, i); 657 for (i = 0; i < NUM_CPU(s); i++) { 658 sysbus_init_irq(sbd, &s->parent_irq[i]); 659 } 660 memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, 661 "gic_dist", 0x1000); 662 } 663 664 static void arm_gic_realize(DeviceState *dev, Error **errp) 665 { 666 /* Device instance realize function for the GIC sysbus device */ 667 int i; 668 GICState *s = ARM_GIC(dev); 669 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 670 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 671 672 agc->parent_realize(dev, errp); 673 if (error_is_set(errp)) { 674 return; 675 } 676 677 gic_init_irqs_and_distributor(s, s->num_irq); 678 679 /* Memory regions for the CPU interfaces (NVIC doesn't have these): 680 * a region for "CPU interface for this core", then a region for 681 * "CPU interface for core 0", "for core 1", ... 682 * NB that the memory region size of 0x100 applies for the 11MPCore 683 * and also cores following the GIC v1 spec (ie A9). 684 * GIC v2 defines a larger memory region (0x1000) so this will need 685 * to be extended when we implement A15. 686 */ 687 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s, 688 "gic_cpu", 0x100); 689 for (i = 0; i < NUM_CPU(s); i++) { 690 s->backref[i] = s; 691 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 692 &s->backref[i], "gic_cpu", 0x100); 693 } 694 /* Distributor */ 695 sysbus_init_mmio(sbd, &s->iomem); 696 /* cpu interfaces (one for "current cpu" plus one per cpu) */ 697 for (i = 0; i <= NUM_CPU(s); i++) { 698 sysbus_init_mmio(sbd, &s->cpuiomem[i]); 699 } 700 } 701 702 static void arm_gic_class_init(ObjectClass *klass, void *data) 703 { 704 DeviceClass *dc = DEVICE_CLASS(klass); 705 ARMGICClass *agc = ARM_GIC_CLASS(klass); 706 707 dc->no_user = 1; 708 agc->parent_realize = dc->realize; 709 dc->realize = arm_gic_realize; 710 } 711 712 static const TypeInfo arm_gic_info = { 713 .name = TYPE_ARM_GIC, 714 .parent = TYPE_ARM_GIC_COMMON, 715 .instance_size = sizeof(GICState), 716 .class_init = arm_gic_class_init, 717 .class_size = sizeof(ARMGICClass), 718 }; 719 720 static void arm_gic_register_types(void) 721 { 722 type_register_static(&arm_gic_info); 723 } 724 725 type_init(arm_gic_register_types) 726