1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 #include "sysemu/kvm.h" 29 30 /* #define DEBUG_GIC */ 31 32 #ifdef DEBUG_GIC 33 #define DEBUG_GIC_GATE 1 34 #else 35 #define DEBUG_GIC_GATE 0 36 #endif 37 38 #define DPRINTF(fmt, ...) do { \ 39 if (DEBUG_GIC_GATE) { \ 40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 41 } \ 42 } while (0) 43 44 static const uint8_t gic_id_11mpcore[] = { 45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 46 }; 47 48 static const uint8_t gic_id_gicv1[] = { 49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 50 }; 51 52 static const uint8_t gic_id_gicv2[] = { 53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 54 }; 55 56 static inline int gic_get_current_cpu(GICState *s) 57 { 58 if (s->num_cpu > 1) { 59 return current_cpu->cpu_index; 60 } 61 return 0; 62 } 63 64 static inline int gic_get_current_vcpu(GICState *s) 65 { 66 return gic_get_current_cpu(s) + GIC_NCPU; 67 } 68 69 /* Return true if this GIC config has interrupt groups, which is 70 * true if we're a GICv2, or a GICv1 with the security extensions. 71 */ 72 static inline bool gic_has_groups(GICState *s) 73 { 74 return s->revision == 2 || s->security_extn; 75 } 76 77 /* TODO: Many places that call this routine could be optimized. */ 78 /* Update interrupt status after enabled or pending bits have been changed. */ 79 static void gic_update(GICState *s) 80 { 81 int best_irq; 82 int best_prio; 83 int irq; 84 int irq_level, fiq_level; 85 int cpu; 86 int cm; 87 88 for (cpu = 0; cpu < s->num_cpu; cpu++) { 89 cm = 1 << cpu; 90 s->current_pending[cpu] = 1023; 91 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 92 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 93 qemu_irq_lower(s->parent_irq[cpu]); 94 qemu_irq_lower(s->parent_fiq[cpu]); 95 continue; 96 } 97 best_prio = 0x100; 98 best_irq = 1023; 99 for (irq = 0; irq < s->num_irq; irq++) { 100 if (GIC_DIST_TEST_ENABLED(irq, cm) && 101 gic_test_pending(s, irq, cm) && 102 (!GIC_DIST_TEST_ACTIVE(irq, cm)) && 103 (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { 104 if (GIC_DIST_GET_PRIORITY(irq, cpu) < best_prio) { 105 best_prio = GIC_DIST_GET_PRIORITY(irq, cpu); 106 best_irq = irq; 107 } 108 } 109 } 110 111 if (best_irq != 1023) { 112 trace_gic_update_bestirq(cpu, best_irq, best_prio, 113 s->priority_mask[cpu], s->running_priority[cpu]); 114 } 115 116 irq_level = fiq_level = 0; 117 118 if (best_prio < s->priority_mask[cpu]) { 119 s->current_pending[cpu] = best_irq; 120 if (best_prio < s->running_priority[cpu]) { 121 int group = GIC_DIST_TEST_GROUP(best_irq, cm); 122 123 if (extract32(s->ctlr, group, 1) && 124 extract32(s->cpu_ctlr[cpu], group, 1)) { 125 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 126 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 127 best_irq, cpu); 128 fiq_level = 1; 129 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 130 } else { 131 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 132 best_irq, cpu); 133 irq_level = 1; 134 trace_gic_update_set_irq(cpu, "irq", irq_level); 135 } 136 } 137 } 138 } 139 140 qemu_set_irq(s->parent_irq[cpu], irq_level); 141 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 142 } 143 } 144 145 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 146 int cm, int target) 147 { 148 if (level) { 149 GIC_DIST_SET_LEVEL(irq, cm); 150 if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, cm)) { 151 DPRINTF("Set %d pending mask %x\n", irq, target); 152 GIC_DIST_SET_PENDING(irq, target); 153 } 154 } else { 155 GIC_DIST_CLEAR_LEVEL(irq, cm); 156 } 157 } 158 159 static void gic_set_irq_generic(GICState *s, int irq, int level, 160 int cm, int target) 161 { 162 if (level) { 163 GIC_DIST_SET_LEVEL(irq, cm); 164 DPRINTF("Set %d pending mask %x\n", irq, target); 165 if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) { 166 GIC_DIST_SET_PENDING(irq, target); 167 } 168 } else { 169 GIC_DIST_CLEAR_LEVEL(irq, cm); 170 } 171 } 172 173 /* Process a change in an external IRQ input. */ 174 static void gic_set_irq(void *opaque, int irq, int level) 175 { 176 /* Meaning of the 'irq' parameter: 177 * [0..N-1] : external interrupts 178 * [N..N+31] : PPI (internal) interrupts for CPU 0 179 * [N+32..N+63] : PPI (internal interrupts for CPU 1 180 * ... 181 */ 182 GICState *s = (GICState *)opaque; 183 int cm, target; 184 if (irq < (s->num_irq - GIC_INTERNAL)) { 185 /* The first external input line is internal interrupt 32. */ 186 cm = ALL_CPU_MASK; 187 irq += GIC_INTERNAL; 188 target = GIC_DIST_TARGET(irq); 189 } else { 190 int cpu; 191 irq -= (s->num_irq - GIC_INTERNAL); 192 cpu = irq / GIC_INTERNAL; 193 irq %= GIC_INTERNAL; 194 cm = 1 << cpu; 195 target = cm; 196 } 197 198 assert(irq >= GIC_NR_SGIS); 199 200 if (level == GIC_DIST_TEST_LEVEL(irq, cm)) { 201 return; 202 } 203 204 if (s->revision == REV_11MPCORE) { 205 gic_set_irq_11mpcore(s, irq, level, cm, target); 206 } else { 207 gic_set_irq_generic(s, irq, level, cm, target); 208 } 209 trace_gic_set_irq(irq, level, cm, target); 210 211 gic_update(s); 212 } 213 214 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 215 MemTxAttrs attrs) 216 { 217 uint16_t pending_irq = s->current_pending[cpu]; 218 219 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 220 int group = GIC_DIST_TEST_GROUP(pending_irq, (1 << cpu)); 221 /* On a GIC without the security extensions, reading this register 222 * behaves in the same way as a secure access to a GIC with them. 223 */ 224 bool secure = !s->security_extn || attrs.secure; 225 226 if (group == 0 && !secure) { 227 /* Group0 interrupts hidden from Non-secure access */ 228 return 1023; 229 } 230 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 231 /* Group1 interrupts only seen by Secure access if 232 * AckCtl bit set. 233 */ 234 return 1022; 235 } 236 } 237 return pending_irq; 238 } 239 240 static int gic_get_group_priority(GICState *s, int cpu, int irq) 241 { 242 /* Return the group priority of the specified interrupt 243 * (which is the top bits of its priority, with the number 244 * of bits masked determined by the applicable binary point register). 245 */ 246 int bpr; 247 uint32_t mask; 248 249 if (gic_has_groups(s) && 250 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 251 GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 252 bpr = s->abpr[cpu] - 1; 253 assert(bpr >= 0); 254 } else { 255 bpr = s->bpr[cpu]; 256 } 257 258 /* a BPR of 0 means the group priority bits are [7:1]; 259 * a BPR of 1 means they are [7:2], and so on down to 260 * a BPR of 7 meaning no group priority bits at all. 261 */ 262 mask = ~0U << ((bpr & 7) + 1); 263 264 return GIC_DIST_GET_PRIORITY(irq, cpu) & mask; 265 } 266 267 static void gic_activate_irq(GICState *s, int cpu, int irq) 268 { 269 /* Set the appropriate Active Priority Register bit for this IRQ, 270 * and update the running priority. 271 */ 272 int prio = gic_get_group_priority(s, cpu, irq); 273 int preemption_level = prio >> (GIC_MIN_BPR + 1); 274 int regno = preemption_level / 32; 275 int bitno = preemption_level % 32; 276 277 if (gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 278 s->nsapr[regno][cpu] |= (1 << bitno); 279 } else { 280 s->apr[regno][cpu] |= (1 << bitno); 281 } 282 283 s->running_priority[cpu] = prio; 284 GIC_DIST_SET_ACTIVE(irq, 1 << cpu); 285 } 286 287 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 288 { 289 /* Recalculate the current running priority for this CPU based 290 * on the set bits in the Active Priority Registers. 291 */ 292 int i; 293 for (i = 0; i < GIC_NR_APRS; i++) { 294 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 295 if (!apr) { 296 continue; 297 } 298 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 299 } 300 return 0x100; 301 } 302 303 static void gic_drop_prio(GICState *s, int cpu, int group) 304 { 305 /* Drop the priority of the currently active interrupt in the 306 * specified group. 307 * 308 * Note that we can guarantee (because of the requirement to nest 309 * GICC_IAR reads [which activate an interrupt and raise priority] 310 * with GICC_EOIR writes [which drop the priority for the interrupt]) 311 * that the interrupt we're being called for is the highest priority 312 * active interrupt, meaning that it has the lowest set bit in the 313 * APR registers. 314 * 315 * If the guest does not honour the ordering constraints then the 316 * behaviour of the GIC is UNPREDICTABLE, which for us means that 317 * the values of the APR registers might become incorrect and the 318 * running priority will be wrong, so interrupts that should preempt 319 * might not do so, and interrupts that should not preempt might do so. 320 */ 321 int i; 322 323 for (i = 0; i < GIC_NR_APRS; i++) { 324 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 325 if (!*papr) { 326 continue; 327 } 328 /* Clear lowest set bit */ 329 *papr &= *papr - 1; 330 break; 331 } 332 333 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 334 } 335 336 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 337 { 338 int ret, irq, src; 339 int cm = 1 << cpu; 340 341 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 342 * for the case where this GIC supports grouping and the pending interrupt 343 * is in the wrong group. 344 */ 345 irq = gic_get_current_pending_irq(s, cpu, attrs); 346 trace_gic_acknowledge_irq(cpu, irq); 347 348 if (irq >= GIC_MAXIRQ) { 349 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 350 return irq; 351 } 352 353 if (GIC_DIST_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 354 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 355 return 1023; 356 } 357 358 if (s->revision == REV_11MPCORE) { 359 /* Clear pending flags for both level and edge triggered interrupts. 360 * Level triggered IRQs will be reasserted once they become inactive. 361 */ 362 GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK 363 : cm); 364 ret = irq; 365 } else { 366 if (irq < GIC_NR_SGIS) { 367 /* Lookup the source CPU for the SGI and clear this in the 368 * sgi_pending map. Return the src and clear the overall pending 369 * state on this CPU if the SGI is not pending from any CPUs. 370 */ 371 assert(s->sgi_pending[irq][cpu] != 0); 372 src = ctz32(s->sgi_pending[irq][cpu]); 373 s->sgi_pending[irq][cpu] &= ~(1 << src); 374 if (s->sgi_pending[irq][cpu] == 0) { 375 GIC_DIST_CLEAR_PENDING(irq, 376 GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK 377 : cm); 378 } 379 ret = irq | ((src & 0x7) << 10); 380 } else { 381 /* Clear pending state for both level and edge triggered 382 * interrupts. (level triggered interrupts with an active line 383 * remain pending, see gic_test_pending) 384 */ 385 GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK 386 : cm); 387 ret = irq; 388 } 389 } 390 391 gic_activate_irq(s, cpu, irq); 392 gic_update(s); 393 DPRINTF("ACK %d\n", irq); 394 return ret; 395 } 396 397 void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, 398 MemTxAttrs attrs) 399 { 400 if (s->security_extn && !attrs.secure) { 401 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 402 return; /* Ignore Non-secure access of Group0 IRQ */ 403 } 404 val = 0x80 | (val >> 1); /* Non-secure view */ 405 } 406 407 if (irq < GIC_INTERNAL) { 408 s->priority1[irq][cpu] = val; 409 } else { 410 s->priority2[(irq) - GIC_INTERNAL] = val; 411 } 412 } 413 414 static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, 415 MemTxAttrs attrs) 416 { 417 uint32_t prio = GIC_DIST_GET_PRIORITY(irq, cpu); 418 419 if (s->security_extn && !attrs.secure) { 420 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 421 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 422 } 423 prio = (prio << 1) & 0xff; /* Non-secure view */ 424 } 425 return prio; 426 } 427 428 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 429 MemTxAttrs attrs) 430 { 431 if (s->security_extn && !attrs.secure) { 432 if (s->priority_mask[cpu] & 0x80) { 433 /* Priority Mask in upper half */ 434 pmask = 0x80 | (pmask >> 1); 435 } else { 436 /* Non-secure write ignored if priority mask is in lower half */ 437 return; 438 } 439 } 440 s->priority_mask[cpu] = pmask; 441 } 442 443 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 444 { 445 uint32_t pmask = s->priority_mask[cpu]; 446 447 if (s->security_extn && !attrs.secure) { 448 if (pmask & 0x80) { 449 /* Priority Mask in upper half, return Non-secure view */ 450 pmask = (pmask << 1) & 0xff; 451 } else { 452 /* Priority Mask in lower half, RAZ */ 453 pmask = 0; 454 } 455 } 456 return pmask; 457 } 458 459 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 460 { 461 uint32_t ret = s->cpu_ctlr[cpu]; 462 463 if (s->security_extn && !attrs.secure) { 464 /* Construct the NS banked view of GICC_CTLR from the correct 465 * bits of the S banked view. We don't need to move the bypass 466 * control bits because we don't implement that (IMPDEF) part 467 * of the GIC architecture. 468 */ 469 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 470 } 471 return ret; 472 } 473 474 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 475 MemTxAttrs attrs) 476 { 477 uint32_t mask; 478 479 if (s->security_extn && !attrs.secure) { 480 /* The NS view can only write certain bits in the register; 481 * the rest are unchanged 482 */ 483 mask = GICC_CTLR_EN_GRP1; 484 if (s->revision == 2) { 485 mask |= GICC_CTLR_EOIMODE_NS; 486 } 487 s->cpu_ctlr[cpu] &= ~mask; 488 s->cpu_ctlr[cpu] |= (value << 1) & mask; 489 } else { 490 if (s->revision == 2) { 491 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 492 } else { 493 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 494 } 495 s->cpu_ctlr[cpu] = value & mask; 496 } 497 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 498 "Group1 Interrupts %sabled\n", cpu, 499 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 500 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 501 } 502 503 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 504 { 505 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { 506 /* Idle priority */ 507 return 0xff; 508 } 509 510 if (s->security_extn && !attrs.secure) { 511 if (s->running_priority[cpu] & 0x80) { 512 /* Running priority in upper half of range: return the Non-secure 513 * view of the priority. 514 */ 515 return s->running_priority[cpu] << 1; 516 } else { 517 /* Running priority in lower half of range: RAZ */ 518 return 0; 519 } 520 } else { 521 return s->running_priority[cpu]; 522 } 523 } 524 525 /* Return true if we should split priority drop and interrupt deactivation, 526 * ie whether the relevant EOIMode bit is set. 527 */ 528 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 529 { 530 if (s->revision != 2) { 531 /* Before GICv2 prio-drop and deactivate are not separable */ 532 return false; 533 } 534 if (s->security_extn && !attrs.secure) { 535 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 536 } 537 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 538 } 539 540 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 541 { 542 int cm = 1 << cpu; 543 int group; 544 545 if (irq >= s->num_irq) { 546 /* 547 * This handles two cases: 548 * 1. If software writes the ID of a spurious interrupt [ie 1023] 549 * to the GICC_DIR, the GIC ignores that write. 550 * 2. If software writes the number of a non-existent interrupt 551 * this must be a subcase of "value written is not an active interrupt" 552 * and so this is UNPREDICTABLE. We choose to ignore it. 553 */ 554 return; 555 } 556 557 group = gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm); 558 559 if (!gic_eoi_split(s, cpu, attrs)) { 560 /* This is UNPREDICTABLE; we choose to ignore it */ 561 qemu_log_mask(LOG_GUEST_ERROR, 562 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 563 return; 564 } 565 566 if (s->security_extn && !attrs.secure && !group) { 567 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 568 return; 569 } 570 571 GIC_DIST_CLEAR_ACTIVE(irq, cm); 572 } 573 574 static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 575 { 576 int cm = 1 << cpu; 577 int group; 578 579 DPRINTF("EOI %d\n", irq); 580 if (irq >= s->num_irq) { 581 /* This handles two cases: 582 * 1. If software writes the ID of a spurious interrupt [ie 1023] 583 * to the GICC_EOIR, the GIC ignores that write. 584 * 2. If software writes the number of a non-existent interrupt 585 * this must be a subcase of "value written does not match the last 586 * valid interrupt value read from the Interrupt Acknowledge 587 * register" and so this is UNPREDICTABLE. We choose to ignore it. 588 */ 589 return; 590 } 591 if (s->running_priority[cpu] == 0x100) { 592 return; /* No active IRQ. */ 593 } 594 595 if (s->revision == REV_11MPCORE) { 596 /* Mark level triggered interrupts as pending if they are still 597 raised. */ 598 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq, cm) 599 && GIC_DIST_TEST_LEVEL(irq, cm) 600 && (GIC_DIST_TARGET(irq) & cm) != 0) { 601 DPRINTF("Set %d pending mask %x\n", irq, cm); 602 GIC_DIST_SET_PENDING(irq, cm); 603 } 604 } 605 606 group = gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm); 607 608 if (s->security_extn && !attrs.secure && !group) { 609 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 610 return; 611 } 612 613 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 614 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 615 * i.e. go ahead and complete the irq anyway. 616 */ 617 618 gic_drop_prio(s, cpu, group); 619 620 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 621 if (!gic_eoi_split(s, cpu, attrs)) { 622 GIC_DIST_CLEAR_ACTIVE(irq, cm); 623 } 624 gic_update(s); 625 } 626 627 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 628 { 629 GICState *s = (GICState *)opaque; 630 uint32_t res; 631 int irq; 632 int i; 633 int cpu; 634 int cm; 635 int mask; 636 637 cpu = gic_get_current_cpu(s); 638 cm = 1 << cpu; 639 if (offset < 0x100) { 640 if (offset == 0) { /* GICD_CTLR */ 641 if (s->security_extn && !attrs.secure) { 642 /* The NS bank of this register is just an alias of the 643 * EnableGrp1 bit in the S bank version. 644 */ 645 return extract32(s->ctlr, 1, 1); 646 } else { 647 return s->ctlr; 648 } 649 } 650 if (offset == 4) 651 /* Interrupt Controller Type Register */ 652 return ((s->num_irq / 32) - 1) 653 | ((s->num_cpu - 1) << 5) 654 | (s->security_extn << 10); 655 if (offset < 0x08) 656 return 0; 657 if (offset >= 0x80) { 658 /* Interrupt Group Registers: these RAZ/WI if this is an NS 659 * access to a GIC with the security extensions, or if the GIC 660 * doesn't have groups at all. 661 */ 662 res = 0; 663 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 664 /* Every byte offset holds 8 group status bits */ 665 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 666 if (irq >= s->num_irq) { 667 goto bad_reg; 668 } 669 for (i = 0; i < 8; i++) { 670 if (GIC_DIST_TEST_GROUP(irq + i, cm)) { 671 res |= (1 << i); 672 } 673 } 674 } 675 return res; 676 } 677 goto bad_reg; 678 } else if (offset < 0x200) { 679 /* Interrupt Set/Clear Enable. */ 680 if (offset < 0x180) 681 irq = (offset - 0x100) * 8; 682 else 683 irq = (offset - 0x180) * 8; 684 irq += GIC_BASE_IRQ; 685 if (irq >= s->num_irq) 686 goto bad_reg; 687 res = 0; 688 for (i = 0; i < 8; i++) { 689 if (s->security_extn && !attrs.secure && 690 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 691 continue; /* Ignore Non-secure access of Group0 IRQ */ 692 } 693 694 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 695 res |= (1 << i); 696 } 697 } 698 } else if (offset < 0x300) { 699 /* Interrupt Set/Clear Pending. */ 700 if (offset < 0x280) 701 irq = (offset - 0x200) * 8; 702 else 703 irq = (offset - 0x280) * 8; 704 irq += GIC_BASE_IRQ; 705 if (irq >= s->num_irq) 706 goto bad_reg; 707 res = 0; 708 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 709 for (i = 0; i < 8; i++) { 710 if (s->security_extn && !attrs.secure && 711 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 712 continue; /* Ignore Non-secure access of Group0 IRQ */ 713 } 714 715 if (gic_test_pending(s, irq + i, mask)) { 716 res |= (1 << i); 717 } 718 } 719 } else if (offset < 0x400) { 720 /* Interrupt Set/Clear Active. */ 721 if (offset < 0x380) { 722 irq = (offset - 0x300) * 8; 723 } else if (s->revision == 2) { 724 irq = (offset - 0x380) * 8; 725 } else { 726 goto bad_reg; 727 } 728 729 irq += GIC_BASE_IRQ; 730 if (irq >= s->num_irq) 731 goto bad_reg; 732 res = 0; 733 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 734 for (i = 0; i < 8; i++) { 735 if (s->security_extn && !attrs.secure && 736 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 737 continue; /* Ignore Non-secure access of Group0 IRQ */ 738 } 739 740 if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) { 741 res |= (1 << i); 742 } 743 } 744 } else if (offset < 0x800) { 745 /* Interrupt Priority. */ 746 irq = (offset - 0x400) + GIC_BASE_IRQ; 747 if (irq >= s->num_irq) 748 goto bad_reg; 749 res = gic_dist_get_priority(s, cpu, irq, attrs); 750 } else if (offset < 0xc00) { 751 /* Interrupt CPU Target. */ 752 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 753 /* For uniprocessor GICs these RAZ/WI */ 754 res = 0; 755 } else { 756 irq = (offset - 0x800) + GIC_BASE_IRQ; 757 if (irq >= s->num_irq) { 758 goto bad_reg; 759 } 760 if (irq < 29 && s->revision == REV_11MPCORE) { 761 res = 0; 762 } else if (irq < GIC_INTERNAL) { 763 res = cm; 764 } else { 765 res = GIC_DIST_TARGET(irq); 766 } 767 } 768 } else if (offset < 0xf00) { 769 /* Interrupt Configuration. */ 770 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 771 if (irq >= s->num_irq) 772 goto bad_reg; 773 res = 0; 774 for (i = 0; i < 4; i++) { 775 if (s->security_extn && !attrs.secure && 776 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 777 continue; /* Ignore Non-secure access of Group0 IRQ */ 778 } 779 780 if (GIC_DIST_TEST_MODEL(irq + i)) { 781 res |= (1 << (i * 2)); 782 } 783 if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 784 res |= (2 << (i * 2)); 785 } 786 } 787 } else if (offset < 0xf10) { 788 goto bad_reg; 789 } else if (offset < 0xf30) { 790 if (s->revision == REV_11MPCORE) { 791 goto bad_reg; 792 } 793 794 if (offset < 0xf20) { 795 /* GICD_CPENDSGIRn */ 796 irq = (offset - 0xf10); 797 } else { 798 irq = (offset - 0xf20); 799 /* GICD_SPENDSGIRn */ 800 } 801 802 if (s->security_extn && !attrs.secure && 803 !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 804 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 805 } else { 806 res = s->sgi_pending[irq][cpu]; 807 } 808 } else if (offset < 0xfd0) { 809 goto bad_reg; 810 } else if (offset < 0x1000) { 811 if (offset & 3) { 812 res = 0; 813 } else { 814 switch (s->revision) { 815 case REV_11MPCORE: 816 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 817 break; 818 case 1: 819 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 820 break; 821 case 2: 822 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 823 break; 824 default: 825 res = 0; 826 } 827 } 828 } else { 829 g_assert_not_reached(); 830 } 831 return res; 832 bad_reg: 833 qemu_log_mask(LOG_GUEST_ERROR, 834 "gic_dist_readb: Bad offset %x\n", (int)offset); 835 return 0; 836 } 837 838 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 839 unsigned size, MemTxAttrs attrs) 840 { 841 switch (size) { 842 case 1: 843 *data = gic_dist_readb(opaque, offset, attrs); 844 return MEMTX_OK; 845 case 2: 846 *data = gic_dist_readb(opaque, offset, attrs); 847 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 848 return MEMTX_OK; 849 case 4: 850 *data = gic_dist_readb(opaque, offset, attrs); 851 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 852 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 853 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 854 return MEMTX_OK; 855 default: 856 return MEMTX_ERROR; 857 } 858 } 859 860 static void gic_dist_writeb(void *opaque, hwaddr offset, 861 uint32_t value, MemTxAttrs attrs) 862 { 863 GICState *s = (GICState *)opaque; 864 int irq; 865 int i; 866 int cpu; 867 868 cpu = gic_get_current_cpu(s); 869 if (offset < 0x100) { 870 if (offset == 0) { 871 if (s->security_extn && !attrs.secure) { 872 /* NS version is just an alias of the S version's bit 1 */ 873 s->ctlr = deposit32(s->ctlr, 1, 1, value); 874 } else if (gic_has_groups(s)) { 875 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 876 } else { 877 s->ctlr = value & GICD_CTLR_EN_GRP0; 878 } 879 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 880 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 881 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 882 } else if (offset < 4) { 883 /* ignored. */ 884 } else if (offset >= 0x80) { 885 /* Interrupt Group Registers: RAZ/WI for NS access to secure 886 * GIC, or for GICs without groups. 887 */ 888 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 889 /* Every byte offset holds 8 group status bits */ 890 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 891 if (irq >= s->num_irq) { 892 goto bad_reg; 893 } 894 for (i = 0; i < 8; i++) { 895 /* Group bits are banked for private interrupts */ 896 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 897 if (value & (1 << i)) { 898 /* Group1 (Non-secure) */ 899 GIC_DIST_SET_GROUP(irq + i, cm); 900 } else { 901 /* Group0 (Secure) */ 902 GIC_DIST_CLEAR_GROUP(irq + i, cm); 903 } 904 } 905 } 906 } else { 907 goto bad_reg; 908 } 909 } else if (offset < 0x180) { 910 /* Interrupt Set Enable. */ 911 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 912 if (irq >= s->num_irq) 913 goto bad_reg; 914 if (irq < GIC_NR_SGIS) { 915 value = 0xff; 916 } 917 918 for (i = 0; i < 8; i++) { 919 if (value & (1 << i)) { 920 int mask = 921 (irq < GIC_INTERNAL) ? (1 << cpu) 922 : GIC_DIST_TARGET(irq + i); 923 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 924 925 if (s->security_extn && !attrs.secure && 926 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 927 continue; /* Ignore Non-secure access of Group0 IRQ */ 928 } 929 930 if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) { 931 DPRINTF("Enabled IRQ %d\n", irq + i); 932 trace_gic_enable_irq(irq + i); 933 } 934 GIC_DIST_SET_ENABLED(irq + i, cm); 935 /* If a raised level triggered IRQ enabled then mark 936 is as pending. */ 937 if (GIC_DIST_TEST_LEVEL(irq + i, mask) 938 && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 939 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 940 GIC_DIST_SET_PENDING(irq + i, mask); 941 } 942 } 943 } 944 } else if (offset < 0x200) { 945 /* Interrupt Clear Enable. */ 946 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 947 if (irq >= s->num_irq) 948 goto bad_reg; 949 if (irq < GIC_NR_SGIS) { 950 value = 0; 951 } 952 953 for (i = 0; i < 8; i++) { 954 if (value & (1 << i)) { 955 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 956 957 if (s->security_extn && !attrs.secure && 958 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 959 continue; /* Ignore Non-secure access of Group0 IRQ */ 960 } 961 962 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 963 DPRINTF("Disabled IRQ %d\n", irq + i); 964 trace_gic_disable_irq(irq + i); 965 } 966 GIC_DIST_CLEAR_ENABLED(irq + i, cm); 967 } 968 } 969 } else if (offset < 0x280) { 970 /* Interrupt Set Pending. */ 971 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 972 if (irq >= s->num_irq) 973 goto bad_reg; 974 if (irq < GIC_NR_SGIS) { 975 value = 0; 976 } 977 978 for (i = 0; i < 8; i++) { 979 if (value & (1 << i)) { 980 if (s->security_extn && !attrs.secure && 981 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 982 continue; /* Ignore Non-secure access of Group0 IRQ */ 983 } 984 985 GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i)); 986 } 987 } 988 } else if (offset < 0x300) { 989 /* Interrupt Clear Pending. */ 990 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 991 if (irq >= s->num_irq) 992 goto bad_reg; 993 if (irq < GIC_NR_SGIS) { 994 value = 0; 995 } 996 997 for (i = 0; i < 8; i++) { 998 if (s->security_extn && !attrs.secure && 999 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1000 continue; /* Ignore Non-secure access of Group0 IRQ */ 1001 } 1002 1003 /* ??? This currently clears the pending bit for all CPUs, even 1004 for per-CPU interrupts. It's unclear whether this is the 1005 corect behavior. */ 1006 if (value & (1 << i)) { 1007 GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 1008 } 1009 } 1010 } else if (offset < 0x380) { 1011 /* Interrupt Set Active. */ 1012 if (s->revision != 2) { 1013 goto bad_reg; 1014 } 1015 1016 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 1017 if (irq >= s->num_irq) { 1018 goto bad_reg; 1019 } 1020 1021 /* This register is banked per-cpu for PPIs */ 1022 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; 1023 1024 for (i = 0; i < 8; i++) { 1025 if (s->security_extn && !attrs.secure && 1026 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1027 continue; /* Ignore Non-secure access of Group0 IRQ */ 1028 } 1029 1030 if (value & (1 << i)) { 1031 GIC_DIST_SET_ACTIVE(irq + i, cm); 1032 } 1033 } 1034 } else if (offset < 0x400) { 1035 /* Interrupt Clear Active. */ 1036 if (s->revision != 2) { 1037 goto bad_reg; 1038 } 1039 1040 irq = (offset - 0x380) * 8 + GIC_BASE_IRQ; 1041 if (irq >= s->num_irq) { 1042 goto bad_reg; 1043 } 1044 1045 /* This register is banked per-cpu for PPIs */ 1046 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; 1047 1048 for (i = 0; i < 8; i++) { 1049 if (s->security_extn && !attrs.secure && 1050 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1051 continue; /* Ignore Non-secure access of Group0 IRQ */ 1052 } 1053 1054 if (value & (1 << i)) { 1055 GIC_DIST_CLEAR_ACTIVE(irq + i, cm); 1056 } 1057 } 1058 } else if (offset < 0x800) { 1059 /* Interrupt Priority. */ 1060 irq = (offset - 0x400) + GIC_BASE_IRQ; 1061 if (irq >= s->num_irq) 1062 goto bad_reg; 1063 gic_dist_set_priority(s, cpu, irq, value, attrs); 1064 } else if (offset < 0xc00) { 1065 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 1066 * annoying exception of the 11MPCore's GIC. 1067 */ 1068 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 1069 irq = (offset - 0x800) + GIC_BASE_IRQ; 1070 if (irq >= s->num_irq) { 1071 goto bad_reg; 1072 } 1073 if (irq < 29 && s->revision == REV_11MPCORE) { 1074 value = 0; 1075 } else if (irq < GIC_INTERNAL) { 1076 value = ALL_CPU_MASK; 1077 } 1078 s->irq_target[irq] = value & ALL_CPU_MASK; 1079 } 1080 } else if (offset < 0xf00) { 1081 /* Interrupt Configuration. */ 1082 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1083 if (irq >= s->num_irq) 1084 goto bad_reg; 1085 if (irq < GIC_NR_SGIS) 1086 value |= 0xaa; 1087 for (i = 0; i < 4; i++) { 1088 if (s->security_extn && !attrs.secure && 1089 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1090 continue; /* Ignore Non-secure access of Group0 IRQ */ 1091 } 1092 1093 if (s->revision == REV_11MPCORE) { 1094 if (value & (1 << (i * 2))) { 1095 GIC_DIST_SET_MODEL(irq + i); 1096 } else { 1097 GIC_DIST_CLEAR_MODEL(irq + i); 1098 } 1099 } 1100 if (value & (2 << (i * 2))) { 1101 GIC_DIST_SET_EDGE_TRIGGER(irq + i); 1102 } else { 1103 GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i); 1104 } 1105 } 1106 } else if (offset < 0xf10) { 1107 /* 0xf00 is only handled for 32-bit writes. */ 1108 goto bad_reg; 1109 } else if (offset < 0xf20) { 1110 /* GICD_CPENDSGIRn */ 1111 if (s->revision == REV_11MPCORE) { 1112 goto bad_reg; 1113 } 1114 irq = (offset - 0xf10); 1115 1116 if (!s->security_extn || attrs.secure || 1117 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1118 s->sgi_pending[irq][cpu] &= ~value; 1119 if (s->sgi_pending[irq][cpu] == 0) { 1120 GIC_DIST_CLEAR_PENDING(irq, 1 << cpu); 1121 } 1122 } 1123 } else if (offset < 0xf30) { 1124 /* GICD_SPENDSGIRn */ 1125 if (s->revision == REV_11MPCORE) { 1126 goto bad_reg; 1127 } 1128 irq = (offset - 0xf20); 1129 1130 if (!s->security_extn || attrs.secure || 1131 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1132 GIC_DIST_SET_PENDING(irq, 1 << cpu); 1133 s->sgi_pending[irq][cpu] |= value; 1134 } 1135 } else { 1136 goto bad_reg; 1137 } 1138 gic_update(s); 1139 return; 1140 bad_reg: 1141 qemu_log_mask(LOG_GUEST_ERROR, 1142 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1143 } 1144 1145 static void gic_dist_writew(void *opaque, hwaddr offset, 1146 uint32_t value, MemTxAttrs attrs) 1147 { 1148 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1149 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1150 } 1151 1152 static void gic_dist_writel(void *opaque, hwaddr offset, 1153 uint32_t value, MemTxAttrs attrs) 1154 { 1155 GICState *s = (GICState *)opaque; 1156 if (offset == 0xf00) { 1157 int cpu; 1158 int irq; 1159 int mask; 1160 int target_cpu; 1161 1162 cpu = gic_get_current_cpu(s); 1163 irq = value & 0x3ff; 1164 switch ((value >> 24) & 3) { 1165 case 0: 1166 mask = (value >> 16) & ALL_CPU_MASK; 1167 break; 1168 case 1: 1169 mask = ALL_CPU_MASK ^ (1 << cpu); 1170 break; 1171 case 2: 1172 mask = 1 << cpu; 1173 break; 1174 default: 1175 DPRINTF("Bad Soft Int target filter\n"); 1176 mask = ALL_CPU_MASK; 1177 break; 1178 } 1179 GIC_DIST_SET_PENDING(irq, mask); 1180 target_cpu = ctz32(mask); 1181 while (target_cpu < GIC_NCPU) { 1182 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1183 mask &= ~(1 << target_cpu); 1184 target_cpu = ctz32(mask); 1185 } 1186 gic_update(s); 1187 return; 1188 } 1189 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1190 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1191 } 1192 1193 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1194 unsigned size, MemTxAttrs attrs) 1195 { 1196 switch (size) { 1197 case 1: 1198 gic_dist_writeb(opaque, offset, data, attrs); 1199 return MEMTX_OK; 1200 case 2: 1201 gic_dist_writew(opaque, offset, data, attrs); 1202 return MEMTX_OK; 1203 case 4: 1204 gic_dist_writel(opaque, offset, data, attrs); 1205 return MEMTX_OK; 1206 default: 1207 return MEMTX_ERROR; 1208 } 1209 } 1210 1211 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1212 { 1213 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1214 * second half of GICC_NSAPR. 1215 */ 1216 switch (GIC_MIN_BPR) { 1217 case 0: 1218 if (regno < 2) { 1219 return s->nsapr[regno + 2][cpu]; 1220 } 1221 break; 1222 case 1: 1223 if (regno == 0) { 1224 return s->nsapr[regno + 1][cpu]; 1225 } 1226 break; 1227 case 2: 1228 if (regno == 0) { 1229 return extract32(s->nsapr[0][cpu], 16, 16); 1230 } 1231 break; 1232 case 3: 1233 if (regno == 0) { 1234 return extract32(s->nsapr[0][cpu], 8, 8); 1235 } 1236 break; 1237 default: 1238 g_assert_not_reached(); 1239 } 1240 return 0; 1241 } 1242 1243 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1244 uint32_t value) 1245 { 1246 /* Write the Nonsecure view of GICC_APR<regno>. */ 1247 switch (GIC_MIN_BPR) { 1248 case 0: 1249 if (regno < 2) { 1250 s->nsapr[regno + 2][cpu] = value; 1251 } 1252 break; 1253 case 1: 1254 if (regno == 0) { 1255 s->nsapr[regno + 1][cpu] = value; 1256 } 1257 break; 1258 case 2: 1259 if (regno == 0) { 1260 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1261 } 1262 break; 1263 case 3: 1264 if (regno == 0) { 1265 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1266 } 1267 break; 1268 default: 1269 g_assert_not_reached(); 1270 } 1271 } 1272 1273 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1274 uint64_t *data, MemTxAttrs attrs) 1275 { 1276 switch (offset) { 1277 case 0x00: /* Control */ 1278 *data = gic_get_cpu_control(s, cpu, attrs); 1279 break; 1280 case 0x04: /* Priority mask */ 1281 *data = gic_get_priority_mask(s, cpu, attrs); 1282 break; 1283 case 0x08: /* Binary Point */ 1284 if (s->security_extn && !attrs.secure) { 1285 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1286 /* NS view of BPR when CBPR is 1 */ 1287 *data = MIN(s->bpr[cpu] + 1, 7); 1288 } else { 1289 /* BPR is banked. Non-secure copy stored in ABPR. */ 1290 *data = s->abpr[cpu]; 1291 } 1292 } else { 1293 *data = s->bpr[cpu]; 1294 } 1295 break; 1296 case 0x0c: /* Acknowledge */ 1297 *data = gic_acknowledge_irq(s, cpu, attrs); 1298 break; 1299 case 0x14: /* Running Priority */ 1300 *data = gic_get_running_priority(s, cpu, attrs); 1301 break; 1302 case 0x18: /* Highest Pending Interrupt */ 1303 *data = gic_get_current_pending_irq(s, cpu, attrs); 1304 break; 1305 case 0x1c: /* Aliased Binary Point */ 1306 /* GIC v2, no security: ABPR 1307 * GIC v1, no security: not implemented (RAZ/WI) 1308 * With security extensions, secure access: ABPR (alias of NS BPR) 1309 * With security extensions, nonsecure access: RAZ/WI 1310 */ 1311 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1312 *data = 0; 1313 } else { 1314 *data = s->abpr[cpu]; 1315 } 1316 break; 1317 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1318 { 1319 int regno = (offset - 0xd0) / 4; 1320 1321 if (regno >= GIC_NR_APRS || s->revision != 2) { 1322 *data = 0; 1323 } else if (s->security_extn && !attrs.secure) { 1324 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1325 *data = gic_apr_ns_view(s, regno, cpu); 1326 } else { 1327 *data = s->apr[regno][cpu]; 1328 } 1329 break; 1330 } 1331 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1332 { 1333 int regno = (offset - 0xe0) / 4; 1334 1335 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1336 (s->security_extn && !attrs.secure)) { 1337 *data = 0; 1338 } else { 1339 *data = s->nsapr[regno][cpu]; 1340 } 1341 break; 1342 } 1343 default: 1344 qemu_log_mask(LOG_GUEST_ERROR, 1345 "gic_cpu_read: Bad offset %x\n", (int)offset); 1346 *data = 0; 1347 break; 1348 } 1349 return MEMTX_OK; 1350 } 1351 1352 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1353 uint32_t value, MemTxAttrs attrs) 1354 { 1355 switch (offset) { 1356 case 0x00: /* Control */ 1357 gic_set_cpu_control(s, cpu, value, attrs); 1358 break; 1359 case 0x04: /* Priority mask */ 1360 gic_set_priority_mask(s, cpu, value, attrs); 1361 break; 1362 case 0x08: /* Binary Point */ 1363 if (s->security_extn && !attrs.secure) { 1364 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1365 /* WI when CBPR is 1 */ 1366 return MEMTX_OK; 1367 } else { 1368 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1369 } 1370 } else { 1371 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1372 } 1373 break; 1374 case 0x10: /* End Of Interrupt */ 1375 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1376 return MEMTX_OK; 1377 case 0x1c: /* Aliased Binary Point */ 1378 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1379 /* unimplemented, or NS access: RAZ/WI */ 1380 return MEMTX_OK; 1381 } else { 1382 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1383 } 1384 break; 1385 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1386 { 1387 int regno = (offset - 0xd0) / 4; 1388 1389 if (regno >= GIC_NR_APRS || s->revision != 2) { 1390 return MEMTX_OK; 1391 } 1392 if (s->security_extn && !attrs.secure) { 1393 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1394 gic_apr_write_ns_view(s, regno, cpu, value); 1395 } else { 1396 s->apr[regno][cpu] = value; 1397 } 1398 break; 1399 } 1400 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1401 { 1402 int regno = (offset - 0xe0) / 4; 1403 1404 if (regno >= GIC_NR_APRS || s->revision != 2) { 1405 return MEMTX_OK; 1406 } 1407 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1408 return MEMTX_OK; 1409 } 1410 s->nsapr[regno][cpu] = value; 1411 break; 1412 } 1413 case 0x1000: 1414 /* GICC_DIR */ 1415 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1416 break; 1417 default: 1418 qemu_log_mask(LOG_GUEST_ERROR, 1419 "gic_cpu_write: Bad offset %x\n", (int)offset); 1420 return MEMTX_OK; 1421 } 1422 gic_update(s); 1423 return MEMTX_OK; 1424 } 1425 1426 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1427 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1428 unsigned size, MemTxAttrs attrs) 1429 { 1430 GICState *s = (GICState *)opaque; 1431 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1432 } 1433 1434 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1435 uint64_t value, unsigned size, 1436 MemTxAttrs attrs) 1437 { 1438 GICState *s = (GICState *)opaque; 1439 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1440 } 1441 1442 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1443 * These just decode the opaque pointer into GICState* + cpu id. 1444 */ 1445 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1446 unsigned size, MemTxAttrs attrs) 1447 { 1448 GICState **backref = (GICState **)opaque; 1449 GICState *s = *backref; 1450 int id = (backref - s->backref); 1451 return gic_cpu_read(s, id, addr, data, attrs); 1452 } 1453 1454 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1455 uint64_t value, unsigned size, 1456 MemTxAttrs attrs) 1457 { 1458 GICState **backref = (GICState **)opaque; 1459 GICState *s = *backref; 1460 int id = (backref - s->backref); 1461 return gic_cpu_write(s, id, addr, value, attrs); 1462 } 1463 1464 static const MemoryRegionOps gic_ops[2] = { 1465 { 1466 .read_with_attrs = gic_dist_read, 1467 .write_with_attrs = gic_dist_write, 1468 .endianness = DEVICE_NATIVE_ENDIAN, 1469 }, 1470 { 1471 .read_with_attrs = gic_thiscpu_read, 1472 .write_with_attrs = gic_thiscpu_write, 1473 .endianness = DEVICE_NATIVE_ENDIAN, 1474 } 1475 }; 1476 1477 static const MemoryRegionOps gic_cpu_ops = { 1478 .read_with_attrs = gic_do_cpu_read, 1479 .write_with_attrs = gic_do_cpu_write, 1480 .endianness = DEVICE_NATIVE_ENDIAN, 1481 }; 1482 1483 static void arm_gic_realize(DeviceState *dev, Error **errp) 1484 { 1485 /* Device instance realize function for the GIC sysbus device */ 1486 int i; 1487 GICState *s = ARM_GIC(dev); 1488 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1489 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1490 Error *local_err = NULL; 1491 1492 agc->parent_realize(dev, &local_err); 1493 if (local_err) { 1494 error_propagate(errp, local_err); 1495 return; 1496 } 1497 1498 if (kvm_enabled() && !kvm_arm_supports_user_irq()) { 1499 error_setg(errp, "KVM with user space irqchip only works when the " 1500 "host kernel supports KVM_CAP_ARM_USER_IRQ"); 1501 return; 1502 } 1503 1504 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1505 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL); 1506 1507 /* Extra core-specific regions for the CPU interfaces. This is 1508 * necessary for "franken-GIC" implementations, for example on 1509 * Exynos 4. 1510 * NB that the memory region size of 0x100 applies for the 11MPCore 1511 * and also cores following the GIC v1 spec (ie A9). 1512 * GIC v2 defines a larger memory region (0x1000) so this will need 1513 * to be extended when we implement A15. 1514 */ 1515 for (i = 0; i < s->num_cpu; i++) { 1516 s->backref[i] = s; 1517 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1518 &s->backref[i], "gic_cpu", 0x100); 1519 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1520 } 1521 } 1522 1523 static void arm_gic_class_init(ObjectClass *klass, void *data) 1524 { 1525 DeviceClass *dc = DEVICE_CLASS(klass); 1526 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1527 1528 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); 1529 } 1530 1531 static const TypeInfo arm_gic_info = { 1532 .name = TYPE_ARM_GIC, 1533 .parent = TYPE_ARM_GIC_COMMON, 1534 .instance_size = sizeof(GICState), 1535 .class_init = arm_gic_class_init, 1536 .class_size = sizeof(ARMGICClass), 1537 }; 1538 1539 static void arm_gic_register_types(void) 1540 { 1541 type_register_static(&arm_gic_info); 1542 } 1543 1544 type_init(arm_gic_register_types) 1545