1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 #include "sysemu/kvm.h" 29 30 /* #define DEBUG_GIC */ 31 32 #ifdef DEBUG_GIC 33 #define DEBUG_GIC_GATE 1 34 #else 35 #define DEBUG_GIC_GATE 0 36 #endif 37 38 #define DPRINTF(fmt, ...) do { \ 39 if (DEBUG_GIC_GATE) { \ 40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 41 } \ 42 } while (0) 43 44 static const uint8_t gic_id_11mpcore[] = { 45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 46 }; 47 48 static const uint8_t gic_id_gicv1[] = { 49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 50 }; 51 52 static const uint8_t gic_id_gicv2[] = { 53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 54 }; 55 56 static inline int gic_get_current_cpu(GICState *s) 57 { 58 if (s->num_cpu > 1) { 59 return current_cpu->cpu_index; 60 } 61 return 0; 62 } 63 64 static inline int gic_get_current_vcpu(GICState *s) 65 { 66 return gic_get_current_cpu(s) + GIC_NCPU; 67 } 68 69 /* Return true if this GIC config has interrupt groups, which is 70 * true if we're a GICv2, or a GICv1 with the security extensions. 71 */ 72 static inline bool gic_has_groups(GICState *s) 73 { 74 return s->revision == 2 || s->security_extn; 75 } 76 77 static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs) 78 { 79 return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; 80 } 81 82 /* TODO: Many places that call this routine could be optimized. */ 83 /* Update interrupt status after enabled or pending bits have been changed. */ 84 static void gic_update(GICState *s) 85 { 86 int best_irq; 87 int best_prio; 88 int irq; 89 int irq_level, fiq_level; 90 int cpu; 91 int cm; 92 93 for (cpu = 0; cpu < s->num_cpu; cpu++) { 94 cm = 1 << cpu; 95 s->current_pending[cpu] = 1023; 96 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 97 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 98 qemu_irq_lower(s->parent_irq[cpu]); 99 qemu_irq_lower(s->parent_fiq[cpu]); 100 continue; 101 } 102 best_prio = 0x100; 103 best_irq = 1023; 104 for (irq = 0; irq < s->num_irq; irq++) { 105 if (GIC_DIST_TEST_ENABLED(irq, cm) && 106 gic_test_pending(s, irq, cm) && 107 (!GIC_DIST_TEST_ACTIVE(irq, cm)) && 108 (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { 109 if (GIC_DIST_GET_PRIORITY(irq, cpu) < best_prio) { 110 best_prio = GIC_DIST_GET_PRIORITY(irq, cpu); 111 best_irq = irq; 112 } 113 } 114 } 115 116 if (best_irq != 1023) { 117 trace_gic_update_bestirq(cpu, best_irq, best_prio, 118 s->priority_mask[cpu], s->running_priority[cpu]); 119 } 120 121 irq_level = fiq_level = 0; 122 123 if (best_prio < s->priority_mask[cpu]) { 124 s->current_pending[cpu] = best_irq; 125 if (best_prio < s->running_priority[cpu]) { 126 int group = GIC_DIST_TEST_GROUP(best_irq, cm); 127 128 if (extract32(s->ctlr, group, 1) && 129 extract32(s->cpu_ctlr[cpu], group, 1)) { 130 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 131 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 132 best_irq, cpu); 133 fiq_level = 1; 134 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 135 } else { 136 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 137 best_irq, cpu); 138 irq_level = 1; 139 trace_gic_update_set_irq(cpu, "irq", irq_level); 140 } 141 } 142 } 143 } 144 145 qemu_set_irq(s->parent_irq[cpu], irq_level); 146 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 147 } 148 } 149 150 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 151 int cm, int target) 152 { 153 if (level) { 154 GIC_DIST_SET_LEVEL(irq, cm); 155 if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, cm)) { 156 DPRINTF("Set %d pending mask %x\n", irq, target); 157 GIC_DIST_SET_PENDING(irq, target); 158 } 159 } else { 160 GIC_DIST_CLEAR_LEVEL(irq, cm); 161 } 162 } 163 164 static void gic_set_irq_generic(GICState *s, int irq, int level, 165 int cm, int target) 166 { 167 if (level) { 168 GIC_DIST_SET_LEVEL(irq, cm); 169 DPRINTF("Set %d pending mask %x\n", irq, target); 170 if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) { 171 GIC_DIST_SET_PENDING(irq, target); 172 } 173 } else { 174 GIC_DIST_CLEAR_LEVEL(irq, cm); 175 } 176 } 177 178 /* Process a change in an external IRQ input. */ 179 static void gic_set_irq(void *opaque, int irq, int level) 180 { 181 /* Meaning of the 'irq' parameter: 182 * [0..N-1] : external interrupts 183 * [N..N+31] : PPI (internal) interrupts for CPU 0 184 * [N+32..N+63] : PPI (internal interrupts for CPU 1 185 * ... 186 */ 187 GICState *s = (GICState *)opaque; 188 int cm, target; 189 if (irq < (s->num_irq - GIC_INTERNAL)) { 190 /* The first external input line is internal interrupt 32. */ 191 cm = ALL_CPU_MASK; 192 irq += GIC_INTERNAL; 193 target = GIC_DIST_TARGET(irq); 194 } else { 195 int cpu; 196 irq -= (s->num_irq - GIC_INTERNAL); 197 cpu = irq / GIC_INTERNAL; 198 irq %= GIC_INTERNAL; 199 cm = 1 << cpu; 200 target = cm; 201 } 202 203 assert(irq >= GIC_NR_SGIS); 204 205 if (level == GIC_DIST_TEST_LEVEL(irq, cm)) { 206 return; 207 } 208 209 if (s->revision == REV_11MPCORE) { 210 gic_set_irq_11mpcore(s, irq, level, cm, target); 211 } else { 212 gic_set_irq_generic(s, irq, level, cm, target); 213 } 214 trace_gic_set_irq(irq, level, cm, target); 215 216 gic_update(s); 217 } 218 219 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 220 MemTxAttrs attrs) 221 { 222 uint16_t pending_irq = s->current_pending[cpu]; 223 224 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 225 int group = gic_test_group(s, pending_irq, cpu); 226 227 /* On a GIC without the security extensions, reading this register 228 * behaves in the same way as a secure access to a GIC with them. 229 */ 230 bool secure = !gic_cpu_ns_access(s, cpu, attrs); 231 232 if (group == 0 && !secure) { 233 /* Group0 interrupts hidden from Non-secure access */ 234 return 1023; 235 } 236 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 237 /* Group1 interrupts only seen by Secure access if 238 * AckCtl bit set. 239 */ 240 return 1022; 241 } 242 } 243 return pending_irq; 244 } 245 246 static int gic_get_group_priority(GICState *s, int cpu, int irq) 247 { 248 /* Return the group priority of the specified interrupt 249 * (which is the top bits of its priority, with the number 250 * of bits masked determined by the applicable binary point register). 251 */ 252 int bpr; 253 uint32_t mask; 254 255 if (gic_has_groups(s) && 256 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 257 gic_test_group(s, irq, cpu)) { 258 bpr = s->abpr[cpu] - 1; 259 assert(bpr >= 0); 260 } else { 261 bpr = s->bpr[cpu]; 262 } 263 264 /* a BPR of 0 means the group priority bits are [7:1]; 265 * a BPR of 1 means they are [7:2], and so on down to 266 * a BPR of 7 meaning no group priority bits at all. 267 */ 268 mask = ~0U << ((bpr & 7) + 1); 269 270 return gic_get_priority(s, irq, cpu) & mask; 271 } 272 273 static void gic_activate_irq(GICState *s, int cpu, int irq) 274 { 275 /* Set the appropriate Active Priority Register bit for this IRQ, 276 * and update the running priority. 277 */ 278 int prio = gic_get_group_priority(s, cpu, irq); 279 int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; 280 int preemption_level = prio >> (min_bpr + 1); 281 int regno = preemption_level / 32; 282 int bitno = preemption_level % 32; 283 uint32_t *papr = NULL; 284 285 if (gic_is_vcpu(cpu)) { 286 assert(regno == 0); 287 papr = &s->h_apr[gic_get_vcpu_real_id(cpu)]; 288 } else if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { 289 papr = &s->nsapr[regno][cpu]; 290 } else { 291 papr = &s->apr[regno][cpu]; 292 } 293 294 *papr |= (1 << bitno); 295 296 s->running_priority[cpu] = prio; 297 gic_set_active(s, irq, cpu); 298 } 299 300 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 301 { 302 /* Recalculate the current running priority for this CPU based 303 * on the set bits in the Active Priority Registers. 304 */ 305 int i; 306 307 if (gic_is_vcpu(cpu)) { 308 uint32_t apr = s->h_apr[gic_get_vcpu_real_id(cpu)]; 309 if (apr) { 310 return ctz32(apr) << (GIC_VIRT_MIN_BPR + 1); 311 } else { 312 return 0x100; 313 } 314 } 315 316 for (i = 0; i < GIC_NR_APRS; i++) { 317 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 318 if (!apr) { 319 continue; 320 } 321 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 322 } 323 return 0x100; 324 } 325 326 static void gic_drop_prio(GICState *s, int cpu, int group) 327 { 328 /* Drop the priority of the currently active interrupt in the 329 * specified group. 330 * 331 * Note that we can guarantee (because of the requirement to nest 332 * GICC_IAR reads [which activate an interrupt and raise priority] 333 * with GICC_EOIR writes [which drop the priority for the interrupt]) 334 * that the interrupt we're being called for is the highest priority 335 * active interrupt, meaning that it has the lowest set bit in the 336 * APR registers. 337 * 338 * If the guest does not honour the ordering constraints then the 339 * behaviour of the GIC is UNPREDICTABLE, which for us means that 340 * the values of the APR registers might become incorrect and the 341 * running priority will be wrong, so interrupts that should preempt 342 * might not do so, and interrupts that should not preempt might do so. 343 */ 344 if (gic_is_vcpu(cpu)) { 345 int rcpu = gic_get_vcpu_real_id(cpu); 346 347 if (s->h_apr[rcpu]) { 348 /* Clear lowest set bit */ 349 s->h_apr[rcpu] &= s->h_apr[rcpu] - 1; 350 } 351 } else { 352 int i; 353 354 for (i = 0; i < GIC_NR_APRS; i++) { 355 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 356 if (!*papr) { 357 continue; 358 } 359 /* Clear lowest set bit */ 360 *papr &= *papr - 1; 361 break; 362 } 363 } 364 365 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 366 } 367 368 static inline uint32_t gic_clear_pending_sgi(GICState *s, int irq, int cpu) 369 { 370 int src; 371 uint32_t ret; 372 373 if (!gic_is_vcpu(cpu)) { 374 /* Lookup the source CPU for the SGI and clear this in the 375 * sgi_pending map. Return the src and clear the overall pending 376 * state on this CPU if the SGI is not pending from any CPUs. 377 */ 378 assert(s->sgi_pending[irq][cpu] != 0); 379 src = ctz32(s->sgi_pending[irq][cpu]); 380 s->sgi_pending[irq][cpu] &= ~(1 << src); 381 if (s->sgi_pending[irq][cpu] == 0) { 382 gic_clear_pending(s, irq, cpu); 383 } 384 ret = irq | ((src & 0x7) << 10); 385 } else { 386 uint32_t *lr_entry = gic_get_lr_entry(s, irq, cpu); 387 src = GICH_LR_CPUID(*lr_entry); 388 389 gic_clear_pending(s, irq, cpu); 390 ret = irq | (src << 10); 391 } 392 393 return ret; 394 } 395 396 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 397 { 398 int ret, irq; 399 400 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 401 * for the case where this GIC supports grouping and the pending interrupt 402 * is in the wrong group. 403 */ 404 irq = gic_get_current_pending_irq(s, cpu, attrs); 405 trace_gic_acknowledge_irq(gic_get_vcpu_real_id(cpu), irq); 406 407 if (irq >= GIC_MAXIRQ) { 408 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 409 return irq; 410 } 411 412 if (gic_get_priority(s, irq, cpu) >= s->running_priority[cpu]) { 413 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 414 return 1023; 415 } 416 417 gic_activate_irq(s, cpu, irq); 418 419 if (s->revision == REV_11MPCORE) { 420 /* Clear pending flags for both level and edge triggered interrupts. 421 * Level triggered IRQs will be reasserted once they become inactive. 422 */ 423 gic_clear_pending(s, irq, cpu); 424 ret = irq; 425 } else { 426 if (irq < GIC_NR_SGIS) { 427 ret = gic_clear_pending_sgi(s, irq, cpu); 428 } else { 429 gic_clear_pending(s, irq, cpu); 430 ret = irq; 431 } 432 } 433 434 gic_update(s); 435 DPRINTF("ACK %d\n", irq); 436 return ret; 437 } 438 439 void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, 440 MemTxAttrs attrs) 441 { 442 if (s->security_extn && !attrs.secure) { 443 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 444 return; /* Ignore Non-secure access of Group0 IRQ */ 445 } 446 val = 0x80 | (val >> 1); /* Non-secure view */ 447 } 448 449 if (irq < GIC_INTERNAL) { 450 s->priority1[irq][cpu] = val; 451 } else { 452 s->priority2[(irq) - GIC_INTERNAL] = val; 453 } 454 } 455 456 static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, 457 MemTxAttrs attrs) 458 { 459 uint32_t prio = GIC_DIST_GET_PRIORITY(irq, cpu); 460 461 if (s->security_extn && !attrs.secure) { 462 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 463 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 464 } 465 prio = (prio << 1) & 0xff; /* Non-secure view */ 466 } 467 return prio; 468 } 469 470 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 471 MemTxAttrs attrs) 472 { 473 if (gic_cpu_ns_access(s, cpu, attrs)) { 474 if (s->priority_mask[cpu] & 0x80) { 475 /* Priority Mask in upper half */ 476 pmask = 0x80 | (pmask >> 1); 477 } else { 478 /* Non-secure write ignored if priority mask is in lower half */ 479 return; 480 } 481 } 482 s->priority_mask[cpu] = pmask; 483 } 484 485 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 486 { 487 uint32_t pmask = s->priority_mask[cpu]; 488 489 if (gic_cpu_ns_access(s, cpu, attrs)) { 490 if (pmask & 0x80) { 491 /* Priority Mask in upper half, return Non-secure view */ 492 pmask = (pmask << 1) & 0xff; 493 } else { 494 /* Priority Mask in lower half, RAZ */ 495 pmask = 0; 496 } 497 } 498 return pmask; 499 } 500 501 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 502 { 503 uint32_t ret = s->cpu_ctlr[cpu]; 504 505 if (gic_cpu_ns_access(s, cpu, attrs)) { 506 /* Construct the NS banked view of GICC_CTLR from the correct 507 * bits of the S banked view. We don't need to move the bypass 508 * control bits because we don't implement that (IMPDEF) part 509 * of the GIC architecture. 510 */ 511 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 512 } 513 return ret; 514 } 515 516 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 517 MemTxAttrs attrs) 518 { 519 uint32_t mask; 520 521 if (gic_cpu_ns_access(s, cpu, attrs)) { 522 /* The NS view can only write certain bits in the register; 523 * the rest are unchanged 524 */ 525 mask = GICC_CTLR_EN_GRP1; 526 if (s->revision == 2) { 527 mask |= GICC_CTLR_EOIMODE_NS; 528 } 529 s->cpu_ctlr[cpu] &= ~mask; 530 s->cpu_ctlr[cpu] |= (value << 1) & mask; 531 } else { 532 if (s->revision == 2) { 533 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 534 } else { 535 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 536 } 537 s->cpu_ctlr[cpu] = value & mask; 538 } 539 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 540 "Group1 Interrupts %sabled\n", cpu, 541 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 542 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 543 } 544 545 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 546 { 547 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { 548 /* Idle priority */ 549 return 0xff; 550 } 551 552 if (gic_cpu_ns_access(s, cpu, attrs)) { 553 if (s->running_priority[cpu] & 0x80) { 554 /* Running priority in upper half of range: return the Non-secure 555 * view of the priority. 556 */ 557 return s->running_priority[cpu] << 1; 558 } else { 559 /* Running priority in lower half of range: RAZ */ 560 return 0; 561 } 562 } else { 563 return s->running_priority[cpu]; 564 } 565 } 566 567 /* Return true if we should split priority drop and interrupt deactivation, 568 * ie whether the relevant EOIMode bit is set. 569 */ 570 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 571 { 572 if (s->revision != 2) { 573 /* Before GICv2 prio-drop and deactivate are not separable */ 574 return false; 575 } 576 if (gic_cpu_ns_access(s, cpu, attrs)) { 577 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 578 } 579 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 580 } 581 582 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 583 { 584 int group; 585 586 if (irq >= s->num_irq) { 587 /* 588 * This handles two cases: 589 * 1. If software writes the ID of a spurious interrupt [ie 1023] 590 * to the GICC_DIR, the GIC ignores that write. 591 * 2. If software writes the number of a non-existent interrupt 592 * this must be a subcase of "value written is not an active interrupt" 593 * and so this is UNPREDICTABLE. We choose to ignore it. 594 */ 595 return; 596 } 597 598 group = gic_has_groups(s) && gic_test_group(s, irq, cpu); 599 600 if (!gic_eoi_split(s, cpu, attrs)) { 601 /* This is UNPREDICTABLE; we choose to ignore it */ 602 qemu_log_mask(LOG_GUEST_ERROR, 603 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 604 return; 605 } 606 607 if (gic_cpu_ns_access(s, cpu, attrs) && !group) { 608 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 609 return; 610 } 611 612 gic_clear_active(s, irq, cpu); 613 } 614 615 static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 616 { 617 int cm = 1 << cpu; 618 int group; 619 620 DPRINTF("EOI %d\n", irq); 621 if (irq >= s->num_irq) { 622 /* This handles two cases: 623 * 1. If software writes the ID of a spurious interrupt [ie 1023] 624 * to the GICC_EOIR, the GIC ignores that write. 625 * 2. If software writes the number of a non-existent interrupt 626 * this must be a subcase of "value written does not match the last 627 * valid interrupt value read from the Interrupt Acknowledge 628 * register" and so this is UNPREDICTABLE. We choose to ignore it. 629 */ 630 return; 631 } 632 if (s->running_priority[cpu] == 0x100) { 633 return; /* No active IRQ. */ 634 } 635 636 if (s->revision == REV_11MPCORE) { 637 /* Mark level triggered interrupts as pending if they are still 638 raised. */ 639 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq, cm) 640 && GIC_DIST_TEST_LEVEL(irq, cm) 641 && (GIC_DIST_TARGET(irq) & cm) != 0) { 642 DPRINTF("Set %d pending mask %x\n", irq, cm); 643 GIC_DIST_SET_PENDING(irq, cm); 644 } 645 } 646 647 group = gic_has_groups(s) && gic_test_group(s, irq, cpu); 648 649 if (gic_cpu_ns_access(s, cpu, attrs) && !group) { 650 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 651 return; 652 } 653 654 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 655 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 656 * i.e. go ahead and complete the irq anyway. 657 */ 658 659 gic_drop_prio(s, cpu, group); 660 661 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 662 if (!gic_eoi_split(s, cpu, attrs)) { 663 gic_clear_active(s, irq, cpu); 664 } 665 gic_update(s); 666 } 667 668 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 669 { 670 GICState *s = (GICState *)opaque; 671 uint32_t res; 672 int irq; 673 int i; 674 int cpu; 675 int cm; 676 int mask; 677 678 cpu = gic_get_current_cpu(s); 679 cm = 1 << cpu; 680 if (offset < 0x100) { 681 if (offset == 0) { /* GICD_CTLR */ 682 if (s->security_extn && !attrs.secure) { 683 /* The NS bank of this register is just an alias of the 684 * EnableGrp1 bit in the S bank version. 685 */ 686 return extract32(s->ctlr, 1, 1); 687 } else { 688 return s->ctlr; 689 } 690 } 691 if (offset == 4) 692 /* Interrupt Controller Type Register */ 693 return ((s->num_irq / 32) - 1) 694 | ((s->num_cpu - 1) << 5) 695 | (s->security_extn << 10); 696 if (offset < 0x08) 697 return 0; 698 if (offset >= 0x80) { 699 /* Interrupt Group Registers: these RAZ/WI if this is an NS 700 * access to a GIC with the security extensions, or if the GIC 701 * doesn't have groups at all. 702 */ 703 res = 0; 704 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 705 /* Every byte offset holds 8 group status bits */ 706 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 707 if (irq >= s->num_irq) { 708 goto bad_reg; 709 } 710 for (i = 0; i < 8; i++) { 711 if (GIC_DIST_TEST_GROUP(irq + i, cm)) { 712 res |= (1 << i); 713 } 714 } 715 } 716 return res; 717 } 718 goto bad_reg; 719 } else if (offset < 0x200) { 720 /* Interrupt Set/Clear Enable. */ 721 if (offset < 0x180) 722 irq = (offset - 0x100) * 8; 723 else 724 irq = (offset - 0x180) * 8; 725 irq += GIC_BASE_IRQ; 726 if (irq >= s->num_irq) 727 goto bad_reg; 728 res = 0; 729 for (i = 0; i < 8; i++) { 730 if (s->security_extn && !attrs.secure && 731 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 732 continue; /* Ignore Non-secure access of Group0 IRQ */ 733 } 734 735 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 736 res |= (1 << i); 737 } 738 } 739 } else if (offset < 0x300) { 740 /* Interrupt Set/Clear Pending. */ 741 if (offset < 0x280) 742 irq = (offset - 0x200) * 8; 743 else 744 irq = (offset - 0x280) * 8; 745 irq += GIC_BASE_IRQ; 746 if (irq >= s->num_irq) 747 goto bad_reg; 748 res = 0; 749 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 750 for (i = 0; i < 8; i++) { 751 if (s->security_extn && !attrs.secure && 752 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 753 continue; /* Ignore Non-secure access of Group0 IRQ */ 754 } 755 756 if (gic_test_pending(s, irq + i, mask)) { 757 res |= (1 << i); 758 } 759 } 760 } else if (offset < 0x400) { 761 /* Interrupt Set/Clear Active. */ 762 if (offset < 0x380) { 763 irq = (offset - 0x300) * 8; 764 } else if (s->revision == 2) { 765 irq = (offset - 0x380) * 8; 766 } else { 767 goto bad_reg; 768 } 769 770 irq += GIC_BASE_IRQ; 771 if (irq >= s->num_irq) 772 goto bad_reg; 773 res = 0; 774 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 775 for (i = 0; i < 8; i++) { 776 if (s->security_extn && !attrs.secure && 777 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 778 continue; /* Ignore Non-secure access of Group0 IRQ */ 779 } 780 781 if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) { 782 res |= (1 << i); 783 } 784 } 785 } else if (offset < 0x800) { 786 /* Interrupt Priority. */ 787 irq = (offset - 0x400) + GIC_BASE_IRQ; 788 if (irq >= s->num_irq) 789 goto bad_reg; 790 res = gic_dist_get_priority(s, cpu, irq, attrs); 791 } else if (offset < 0xc00) { 792 /* Interrupt CPU Target. */ 793 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 794 /* For uniprocessor GICs these RAZ/WI */ 795 res = 0; 796 } else { 797 irq = (offset - 0x800) + GIC_BASE_IRQ; 798 if (irq >= s->num_irq) { 799 goto bad_reg; 800 } 801 if (irq < 29 && s->revision == REV_11MPCORE) { 802 res = 0; 803 } else if (irq < GIC_INTERNAL) { 804 res = cm; 805 } else { 806 res = GIC_DIST_TARGET(irq); 807 } 808 } 809 } else if (offset < 0xf00) { 810 /* Interrupt Configuration. */ 811 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 812 if (irq >= s->num_irq) 813 goto bad_reg; 814 res = 0; 815 for (i = 0; i < 4; i++) { 816 if (s->security_extn && !attrs.secure && 817 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 818 continue; /* Ignore Non-secure access of Group0 IRQ */ 819 } 820 821 if (GIC_DIST_TEST_MODEL(irq + i)) { 822 res |= (1 << (i * 2)); 823 } 824 if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 825 res |= (2 << (i * 2)); 826 } 827 } 828 } else if (offset < 0xf10) { 829 goto bad_reg; 830 } else if (offset < 0xf30) { 831 if (s->revision == REV_11MPCORE) { 832 goto bad_reg; 833 } 834 835 if (offset < 0xf20) { 836 /* GICD_CPENDSGIRn */ 837 irq = (offset - 0xf10); 838 } else { 839 irq = (offset - 0xf20); 840 /* GICD_SPENDSGIRn */ 841 } 842 843 if (s->security_extn && !attrs.secure && 844 !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 845 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 846 } else { 847 res = s->sgi_pending[irq][cpu]; 848 } 849 } else if (offset < 0xfd0) { 850 goto bad_reg; 851 } else if (offset < 0x1000) { 852 if (offset & 3) { 853 res = 0; 854 } else { 855 switch (s->revision) { 856 case REV_11MPCORE: 857 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 858 break; 859 case 1: 860 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 861 break; 862 case 2: 863 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 864 break; 865 default: 866 res = 0; 867 } 868 } 869 } else { 870 g_assert_not_reached(); 871 } 872 return res; 873 bad_reg: 874 qemu_log_mask(LOG_GUEST_ERROR, 875 "gic_dist_readb: Bad offset %x\n", (int)offset); 876 return 0; 877 } 878 879 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 880 unsigned size, MemTxAttrs attrs) 881 { 882 switch (size) { 883 case 1: 884 *data = gic_dist_readb(opaque, offset, attrs); 885 return MEMTX_OK; 886 case 2: 887 *data = gic_dist_readb(opaque, offset, attrs); 888 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 889 return MEMTX_OK; 890 case 4: 891 *data = gic_dist_readb(opaque, offset, attrs); 892 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 893 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 894 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 895 return MEMTX_OK; 896 default: 897 return MEMTX_ERROR; 898 } 899 } 900 901 static void gic_dist_writeb(void *opaque, hwaddr offset, 902 uint32_t value, MemTxAttrs attrs) 903 { 904 GICState *s = (GICState *)opaque; 905 int irq; 906 int i; 907 int cpu; 908 909 cpu = gic_get_current_cpu(s); 910 if (offset < 0x100) { 911 if (offset == 0) { 912 if (s->security_extn && !attrs.secure) { 913 /* NS version is just an alias of the S version's bit 1 */ 914 s->ctlr = deposit32(s->ctlr, 1, 1, value); 915 } else if (gic_has_groups(s)) { 916 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 917 } else { 918 s->ctlr = value & GICD_CTLR_EN_GRP0; 919 } 920 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 921 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 922 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 923 } else if (offset < 4) { 924 /* ignored. */ 925 } else if (offset >= 0x80) { 926 /* Interrupt Group Registers: RAZ/WI for NS access to secure 927 * GIC, or for GICs without groups. 928 */ 929 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 930 /* Every byte offset holds 8 group status bits */ 931 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 932 if (irq >= s->num_irq) { 933 goto bad_reg; 934 } 935 for (i = 0; i < 8; i++) { 936 /* Group bits are banked for private interrupts */ 937 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 938 if (value & (1 << i)) { 939 /* Group1 (Non-secure) */ 940 GIC_DIST_SET_GROUP(irq + i, cm); 941 } else { 942 /* Group0 (Secure) */ 943 GIC_DIST_CLEAR_GROUP(irq + i, cm); 944 } 945 } 946 } 947 } else { 948 goto bad_reg; 949 } 950 } else if (offset < 0x180) { 951 /* Interrupt Set Enable. */ 952 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 953 if (irq >= s->num_irq) 954 goto bad_reg; 955 if (irq < GIC_NR_SGIS) { 956 value = 0xff; 957 } 958 959 for (i = 0; i < 8; i++) { 960 if (value & (1 << i)) { 961 int mask = 962 (irq < GIC_INTERNAL) ? (1 << cpu) 963 : GIC_DIST_TARGET(irq + i); 964 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 965 966 if (s->security_extn && !attrs.secure && 967 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 968 continue; /* Ignore Non-secure access of Group0 IRQ */ 969 } 970 971 if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) { 972 DPRINTF("Enabled IRQ %d\n", irq + i); 973 trace_gic_enable_irq(irq + i); 974 } 975 GIC_DIST_SET_ENABLED(irq + i, cm); 976 /* If a raised level triggered IRQ enabled then mark 977 is as pending. */ 978 if (GIC_DIST_TEST_LEVEL(irq + i, mask) 979 && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 980 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 981 GIC_DIST_SET_PENDING(irq + i, mask); 982 } 983 } 984 } 985 } else if (offset < 0x200) { 986 /* Interrupt Clear Enable. */ 987 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 988 if (irq >= s->num_irq) 989 goto bad_reg; 990 if (irq < GIC_NR_SGIS) { 991 value = 0; 992 } 993 994 for (i = 0; i < 8; i++) { 995 if (value & (1 << i)) { 996 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 997 998 if (s->security_extn && !attrs.secure && 999 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1000 continue; /* Ignore Non-secure access of Group0 IRQ */ 1001 } 1002 1003 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 1004 DPRINTF("Disabled IRQ %d\n", irq + i); 1005 trace_gic_disable_irq(irq + i); 1006 } 1007 GIC_DIST_CLEAR_ENABLED(irq + i, cm); 1008 } 1009 } 1010 } else if (offset < 0x280) { 1011 /* Interrupt Set Pending. */ 1012 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 1013 if (irq >= s->num_irq) 1014 goto bad_reg; 1015 if (irq < GIC_NR_SGIS) { 1016 value = 0; 1017 } 1018 1019 for (i = 0; i < 8; i++) { 1020 if (value & (1 << i)) { 1021 if (s->security_extn && !attrs.secure && 1022 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1023 continue; /* Ignore Non-secure access of Group0 IRQ */ 1024 } 1025 1026 GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i)); 1027 } 1028 } 1029 } else if (offset < 0x300) { 1030 /* Interrupt Clear Pending. */ 1031 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 1032 if (irq >= s->num_irq) 1033 goto bad_reg; 1034 if (irq < GIC_NR_SGIS) { 1035 value = 0; 1036 } 1037 1038 for (i = 0; i < 8; i++) { 1039 if (s->security_extn && !attrs.secure && 1040 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1041 continue; /* Ignore Non-secure access of Group0 IRQ */ 1042 } 1043 1044 /* ??? This currently clears the pending bit for all CPUs, even 1045 for per-CPU interrupts. It's unclear whether this is the 1046 corect behavior. */ 1047 if (value & (1 << i)) { 1048 GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 1049 } 1050 } 1051 } else if (offset < 0x380) { 1052 /* Interrupt Set Active. */ 1053 if (s->revision != 2) { 1054 goto bad_reg; 1055 } 1056 1057 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 1058 if (irq >= s->num_irq) { 1059 goto bad_reg; 1060 } 1061 1062 /* This register is banked per-cpu for PPIs */ 1063 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; 1064 1065 for (i = 0; i < 8; i++) { 1066 if (s->security_extn && !attrs.secure && 1067 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1068 continue; /* Ignore Non-secure access of Group0 IRQ */ 1069 } 1070 1071 if (value & (1 << i)) { 1072 GIC_DIST_SET_ACTIVE(irq + i, cm); 1073 } 1074 } 1075 } else if (offset < 0x400) { 1076 /* Interrupt Clear Active. */ 1077 if (s->revision != 2) { 1078 goto bad_reg; 1079 } 1080 1081 irq = (offset - 0x380) * 8 + GIC_BASE_IRQ; 1082 if (irq >= s->num_irq) { 1083 goto bad_reg; 1084 } 1085 1086 /* This register is banked per-cpu for PPIs */ 1087 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; 1088 1089 for (i = 0; i < 8; i++) { 1090 if (s->security_extn && !attrs.secure && 1091 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1092 continue; /* Ignore Non-secure access of Group0 IRQ */ 1093 } 1094 1095 if (value & (1 << i)) { 1096 GIC_DIST_CLEAR_ACTIVE(irq + i, cm); 1097 } 1098 } 1099 } else if (offset < 0x800) { 1100 /* Interrupt Priority. */ 1101 irq = (offset - 0x400) + GIC_BASE_IRQ; 1102 if (irq >= s->num_irq) 1103 goto bad_reg; 1104 gic_dist_set_priority(s, cpu, irq, value, attrs); 1105 } else if (offset < 0xc00) { 1106 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 1107 * annoying exception of the 11MPCore's GIC. 1108 */ 1109 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 1110 irq = (offset - 0x800) + GIC_BASE_IRQ; 1111 if (irq >= s->num_irq) { 1112 goto bad_reg; 1113 } 1114 if (irq < 29 && s->revision == REV_11MPCORE) { 1115 value = 0; 1116 } else if (irq < GIC_INTERNAL) { 1117 value = ALL_CPU_MASK; 1118 } 1119 s->irq_target[irq] = value & ALL_CPU_MASK; 1120 } 1121 } else if (offset < 0xf00) { 1122 /* Interrupt Configuration. */ 1123 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1124 if (irq >= s->num_irq) 1125 goto bad_reg; 1126 if (irq < GIC_NR_SGIS) 1127 value |= 0xaa; 1128 for (i = 0; i < 4; i++) { 1129 if (s->security_extn && !attrs.secure && 1130 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1131 continue; /* Ignore Non-secure access of Group0 IRQ */ 1132 } 1133 1134 if (s->revision == REV_11MPCORE) { 1135 if (value & (1 << (i * 2))) { 1136 GIC_DIST_SET_MODEL(irq + i); 1137 } else { 1138 GIC_DIST_CLEAR_MODEL(irq + i); 1139 } 1140 } 1141 if (value & (2 << (i * 2))) { 1142 GIC_DIST_SET_EDGE_TRIGGER(irq + i); 1143 } else { 1144 GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i); 1145 } 1146 } 1147 } else if (offset < 0xf10) { 1148 /* 0xf00 is only handled for 32-bit writes. */ 1149 goto bad_reg; 1150 } else if (offset < 0xf20) { 1151 /* GICD_CPENDSGIRn */ 1152 if (s->revision == REV_11MPCORE) { 1153 goto bad_reg; 1154 } 1155 irq = (offset - 0xf10); 1156 1157 if (!s->security_extn || attrs.secure || 1158 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1159 s->sgi_pending[irq][cpu] &= ~value; 1160 if (s->sgi_pending[irq][cpu] == 0) { 1161 GIC_DIST_CLEAR_PENDING(irq, 1 << cpu); 1162 } 1163 } 1164 } else if (offset < 0xf30) { 1165 /* GICD_SPENDSGIRn */ 1166 if (s->revision == REV_11MPCORE) { 1167 goto bad_reg; 1168 } 1169 irq = (offset - 0xf20); 1170 1171 if (!s->security_extn || attrs.secure || 1172 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1173 GIC_DIST_SET_PENDING(irq, 1 << cpu); 1174 s->sgi_pending[irq][cpu] |= value; 1175 } 1176 } else { 1177 goto bad_reg; 1178 } 1179 gic_update(s); 1180 return; 1181 bad_reg: 1182 qemu_log_mask(LOG_GUEST_ERROR, 1183 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1184 } 1185 1186 static void gic_dist_writew(void *opaque, hwaddr offset, 1187 uint32_t value, MemTxAttrs attrs) 1188 { 1189 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1190 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1191 } 1192 1193 static void gic_dist_writel(void *opaque, hwaddr offset, 1194 uint32_t value, MemTxAttrs attrs) 1195 { 1196 GICState *s = (GICState *)opaque; 1197 if (offset == 0xf00) { 1198 int cpu; 1199 int irq; 1200 int mask; 1201 int target_cpu; 1202 1203 cpu = gic_get_current_cpu(s); 1204 irq = value & 0x3ff; 1205 switch ((value >> 24) & 3) { 1206 case 0: 1207 mask = (value >> 16) & ALL_CPU_MASK; 1208 break; 1209 case 1: 1210 mask = ALL_CPU_MASK ^ (1 << cpu); 1211 break; 1212 case 2: 1213 mask = 1 << cpu; 1214 break; 1215 default: 1216 DPRINTF("Bad Soft Int target filter\n"); 1217 mask = ALL_CPU_MASK; 1218 break; 1219 } 1220 GIC_DIST_SET_PENDING(irq, mask); 1221 target_cpu = ctz32(mask); 1222 while (target_cpu < GIC_NCPU) { 1223 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1224 mask &= ~(1 << target_cpu); 1225 target_cpu = ctz32(mask); 1226 } 1227 gic_update(s); 1228 return; 1229 } 1230 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1231 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1232 } 1233 1234 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1235 unsigned size, MemTxAttrs attrs) 1236 { 1237 switch (size) { 1238 case 1: 1239 gic_dist_writeb(opaque, offset, data, attrs); 1240 return MEMTX_OK; 1241 case 2: 1242 gic_dist_writew(opaque, offset, data, attrs); 1243 return MEMTX_OK; 1244 case 4: 1245 gic_dist_writel(opaque, offset, data, attrs); 1246 return MEMTX_OK; 1247 default: 1248 return MEMTX_ERROR; 1249 } 1250 } 1251 1252 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1253 { 1254 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1255 * second half of GICC_NSAPR. 1256 */ 1257 switch (GIC_MIN_BPR) { 1258 case 0: 1259 if (regno < 2) { 1260 return s->nsapr[regno + 2][cpu]; 1261 } 1262 break; 1263 case 1: 1264 if (regno == 0) { 1265 return s->nsapr[regno + 1][cpu]; 1266 } 1267 break; 1268 case 2: 1269 if (regno == 0) { 1270 return extract32(s->nsapr[0][cpu], 16, 16); 1271 } 1272 break; 1273 case 3: 1274 if (regno == 0) { 1275 return extract32(s->nsapr[0][cpu], 8, 8); 1276 } 1277 break; 1278 default: 1279 g_assert_not_reached(); 1280 } 1281 return 0; 1282 } 1283 1284 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1285 uint32_t value) 1286 { 1287 /* Write the Nonsecure view of GICC_APR<regno>. */ 1288 switch (GIC_MIN_BPR) { 1289 case 0: 1290 if (regno < 2) { 1291 s->nsapr[regno + 2][cpu] = value; 1292 } 1293 break; 1294 case 1: 1295 if (regno == 0) { 1296 s->nsapr[regno + 1][cpu] = value; 1297 } 1298 break; 1299 case 2: 1300 if (regno == 0) { 1301 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1302 } 1303 break; 1304 case 3: 1305 if (regno == 0) { 1306 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1307 } 1308 break; 1309 default: 1310 g_assert_not_reached(); 1311 } 1312 } 1313 1314 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1315 uint64_t *data, MemTxAttrs attrs) 1316 { 1317 switch (offset) { 1318 case 0x00: /* Control */ 1319 *data = gic_get_cpu_control(s, cpu, attrs); 1320 break; 1321 case 0x04: /* Priority mask */ 1322 *data = gic_get_priority_mask(s, cpu, attrs); 1323 break; 1324 case 0x08: /* Binary Point */ 1325 if (gic_cpu_ns_access(s, cpu, attrs)) { 1326 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1327 /* NS view of BPR when CBPR is 1 */ 1328 *data = MIN(s->bpr[cpu] + 1, 7); 1329 } else { 1330 /* BPR is banked. Non-secure copy stored in ABPR. */ 1331 *data = s->abpr[cpu]; 1332 } 1333 } else { 1334 *data = s->bpr[cpu]; 1335 } 1336 break; 1337 case 0x0c: /* Acknowledge */ 1338 *data = gic_acknowledge_irq(s, cpu, attrs); 1339 break; 1340 case 0x14: /* Running Priority */ 1341 *data = gic_get_running_priority(s, cpu, attrs); 1342 break; 1343 case 0x18: /* Highest Pending Interrupt */ 1344 *data = gic_get_current_pending_irq(s, cpu, attrs); 1345 break; 1346 case 0x1c: /* Aliased Binary Point */ 1347 /* GIC v2, no security: ABPR 1348 * GIC v1, no security: not implemented (RAZ/WI) 1349 * With security extensions, secure access: ABPR (alias of NS BPR) 1350 * With security extensions, nonsecure access: RAZ/WI 1351 */ 1352 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1353 *data = 0; 1354 } else { 1355 *data = s->abpr[cpu]; 1356 } 1357 break; 1358 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1359 { 1360 int regno = (offset - 0xd0) / 4; 1361 1362 if (regno >= GIC_NR_APRS || s->revision != 2) { 1363 *data = 0; 1364 } else if (gic_cpu_ns_access(s, cpu, attrs)) { 1365 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1366 *data = gic_apr_ns_view(s, regno, cpu); 1367 } else { 1368 *data = s->apr[regno][cpu]; 1369 } 1370 break; 1371 } 1372 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1373 { 1374 int regno = (offset - 0xe0) / 4; 1375 1376 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1377 gic_cpu_ns_access(s, cpu, attrs)) { 1378 *data = 0; 1379 } else { 1380 *data = s->nsapr[regno][cpu]; 1381 } 1382 break; 1383 } 1384 default: 1385 qemu_log_mask(LOG_GUEST_ERROR, 1386 "gic_cpu_read: Bad offset %x\n", (int)offset); 1387 *data = 0; 1388 break; 1389 } 1390 return MEMTX_OK; 1391 } 1392 1393 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1394 uint32_t value, MemTxAttrs attrs) 1395 { 1396 switch (offset) { 1397 case 0x00: /* Control */ 1398 gic_set_cpu_control(s, cpu, value, attrs); 1399 break; 1400 case 0x04: /* Priority mask */ 1401 gic_set_priority_mask(s, cpu, value, attrs); 1402 break; 1403 case 0x08: /* Binary Point */ 1404 if (gic_cpu_ns_access(s, cpu, attrs)) { 1405 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1406 /* WI when CBPR is 1 */ 1407 return MEMTX_OK; 1408 } else { 1409 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1410 } 1411 } else { 1412 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1413 } 1414 break; 1415 case 0x10: /* End Of Interrupt */ 1416 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1417 return MEMTX_OK; 1418 case 0x1c: /* Aliased Binary Point */ 1419 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1420 /* unimplemented, or NS access: RAZ/WI */ 1421 return MEMTX_OK; 1422 } else { 1423 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1424 } 1425 break; 1426 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1427 { 1428 int regno = (offset - 0xd0) / 4; 1429 1430 if (regno >= GIC_NR_APRS || s->revision != 2) { 1431 return MEMTX_OK; 1432 } 1433 if (gic_cpu_ns_access(s, cpu, attrs)) { 1434 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1435 gic_apr_write_ns_view(s, regno, cpu, value); 1436 } else { 1437 s->apr[regno][cpu] = value; 1438 } 1439 break; 1440 } 1441 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1442 { 1443 int regno = (offset - 0xe0) / 4; 1444 1445 if (regno >= GIC_NR_APRS || s->revision != 2) { 1446 return MEMTX_OK; 1447 } 1448 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1449 return MEMTX_OK; 1450 } 1451 s->nsapr[regno][cpu] = value; 1452 break; 1453 } 1454 case 0x1000: 1455 /* GICC_DIR */ 1456 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1457 break; 1458 default: 1459 qemu_log_mask(LOG_GUEST_ERROR, 1460 "gic_cpu_write: Bad offset %x\n", (int)offset); 1461 return MEMTX_OK; 1462 } 1463 gic_update(s); 1464 return MEMTX_OK; 1465 } 1466 1467 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1468 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1469 unsigned size, MemTxAttrs attrs) 1470 { 1471 GICState *s = (GICState *)opaque; 1472 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1473 } 1474 1475 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1476 uint64_t value, unsigned size, 1477 MemTxAttrs attrs) 1478 { 1479 GICState *s = (GICState *)opaque; 1480 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1481 } 1482 1483 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1484 * These just decode the opaque pointer into GICState* + cpu id. 1485 */ 1486 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1487 unsigned size, MemTxAttrs attrs) 1488 { 1489 GICState **backref = (GICState **)opaque; 1490 GICState *s = *backref; 1491 int id = (backref - s->backref); 1492 return gic_cpu_read(s, id, addr, data, attrs); 1493 } 1494 1495 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1496 uint64_t value, unsigned size, 1497 MemTxAttrs attrs) 1498 { 1499 GICState **backref = (GICState **)opaque; 1500 GICState *s = *backref; 1501 int id = (backref - s->backref); 1502 return gic_cpu_write(s, id, addr, value, attrs); 1503 } 1504 1505 static const MemoryRegionOps gic_ops[2] = { 1506 { 1507 .read_with_attrs = gic_dist_read, 1508 .write_with_attrs = gic_dist_write, 1509 .endianness = DEVICE_NATIVE_ENDIAN, 1510 }, 1511 { 1512 .read_with_attrs = gic_thiscpu_read, 1513 .write_with_attrs = gic_thiscpu_write, 1514 .endianness = DEVICE_NATIVE_ENDIAN, 1515 } 1516 }; 1517 1518 static const MemoryRegionOps gic_cpu_ops = { 1519 .read_with_attrs = gic_do_cpu_read, 1520 .write_with_attrs = gic_do_cpu_write, 1521 .endianness = DEVICE_NATIVE_ENDIAN, 1522 }; 1523 1524 static void arm_gic_realize(DeviceState *dev, Error **errp) 1525 { 1526 /* Device instance realize function for the GIC sysbus device */ 1527 int i; 1528 GICState *s = ARM_GIC(dev); 1529 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1530 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1531 Error *local_err = NULL; 1532 1533 agc->parent_realize(dev, &local_err); 1534 if (local_err) { 1535 error_propagate(errp, local_err); 1536 return; 1537 } 1538 1539 if (kvm_enabled() && !kvm_arm_supports_user_irq()) { 1540 error_setg(errp, "KVM with user space irqchip only works when the " 1541 "host kernel supports KVM_CAP_ARM_USER_IRQ"); 1542 return; 1543 } 1544 1545 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1546 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL); 1547 1548 /* Extra core-specific regions for the CPU interfaces. This is 1549 * necessary for "franken-GIC" implementations, for example on 1550 * Exynos 4. 1551 * NB that the memory region size of 0x100 applies for the 11MPCore 1552 * and also cores following the GIC v1 spec (ie A9). 1553 * GIC v2 defines a larger memory region (0x1000) so this will need 1554 * to be extended when we implement A15. 1555 */ 1556 for (i = 0; i < s->num_cpu; i++) { 1557 s->backref[i] = s; 1558 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1559 &s->backref[i], "gic_cpu", 0x100); 1560 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1561 } 1562 } 1563 1564 static void arm_gic_class_init(ObjectClass *klass, void *data) 1565 { 1566 DeviceClass *dc = DEVICE_CLASS(klass); 1567 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1568 1569 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); 1570 } 1571 1572 static const TypeInfo arm_gic_info = { 1573 .name = TYPE_ARM_GIC, 1574 .parent = TYPE_ARM_GIC_COMMON, 1575 .instance_size = sizeof(GICState), 1576 .class_init = arm_gic_class_init, 1577 .class_size = sizeof(ARMGICClass), 1578 }; 1579 1580 static void arm_gic_register_types(void) 1581 { 1582 type_register_static(&arm_gic_info); 1583 } 1584 1585 type_init(arm_gic_register_types) 1586