1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 29 /* #define DEBUG_GIC */ 30 31 #ifdef DEBUG_GIC 32 #define DEBUG_GIC_GATE 1 33 #else 34 #define DEBUG_GIC_GATE 0 35 #endif 36 37 #define DPRINTF(fmt, ...) do { \ 38 if (DEBUG_GIC_GATE) { \ 39 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 40 } \ 41 } while (0) 42 43 static const uint8_t gic_id_11mpcore[] = { 44 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 45 }; 46 47 static const uint8_t gic_id_gicv1[] = { 48 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 49 }; 50 51 static const uint8_t gic_id_gicv2[] = { 52 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 53 }; 54 55 static inline int gic_get_current_cpu(GICState *s) 56 { 57 if (s->num_cpu > 1) { 58 return current_cpu->cpu_index; 59 } 60 return 0; 61 } 62 63 /* Return true if this GIC config has interrupt groups, which is 64 * true if we're a GICv2, or a GICv1 with the security extensions. 65 */ 66 static inline bool gic_has_groups(GICState *s) 67 { 68 return s->revision == 2 || s->security_extn; 69 } 70 71 /* TODO: Many places that call this routine could be optimized. */ 72 /* Update interrupt status after enabled or pending bits have been changed. */ 73 void gic_update(GICState *s) 74 { 75 int best_irq; 76 int best_prio; 77 int irq; 78 int irq_level, fiq_level; 79 int cpu; 80 int cm; 81 82 for (cpu = 0; cpu < s->num_cpu; cpu++) { 83 cm = 1 << cpu; 84 s->current_pending[cpu] = 1023; 85 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 86 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 87 qemu_irq_lower(s->parent_irq[cpu]); 88 qemu_irq_lower(s->parent_fiq[cpu]); 89 continue; 90 } 91 best_prio = 0x100; 92 best_irq = 1023; 93 for (irq = 0; irq < s->num_irq; irq++) { 94 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 95 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 96 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 97 best_prio = GIC_GET_PRIORITY(irq, cpu); 98 best_irq = irq; 99 } 100 } 101 } 102 103 if (best_irq != 1023) { 104 trace_gic_update_bestirq(cpu, best_irq, best_prio, 105 s->priority_mask[cpu], s->running_priority[cpu]); 106 } 107 108 irq_level = fiq_level = 0; 109 110 if (best_prio < s->priority_mask[cpu]) { 111 s->current_pending[cpu] = best_irq; 112 if (best_prio < s->running_priority[cpu]) { 113 int group = GIC_TEST_GROUP(best_irq, cm); 114 115 if (extract32(s->ctlr, group, 1) && 116 extract32(s->cpu_ctlr[cpu], group, 1)) { 117 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 118 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 119 best_irq, cpu); 120 fiq_level = 1; 121 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 122 } else { 123 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 124 best_irq, cpu); 125 irq_level = 1; 126 trace_gic_update_set_irq(cpu, "irq", irq_level); 127 } 128 } 129 } 130 } 131 132 qemu_set_irq(s->parent_irq[cpu], irq_level); 133 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 134 } 135 } 136 137 void gic_set_pending_private(GICState *s, int cpu, int irq) 138 { 139 int cm = 1 << cpu; 140 141 if (gic_test_pending(s, irq, cm)) { 142 return; 143 } 144 145 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 146 GIC_SET_PENDING(irq, cm); 147 gic_update(s); 148 } 149 150 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 151 int cm, int target) 152 { 153 if (level) { 154 GIC_SET_LEVEL(irq, cm); 155 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 156 DPRINTF("Set %d pending mask %x\n", irq, target); 157 GIC_SET_PENDING(irq, target); 158 } 159 } else { 160 GIC_CLEAR_LEVEL(irq, cm); 161 } 162 } 163 164 static void gic_set_irq_generic(GICState *s, int irq, int level, 165 int cm, int target) 166 { 167 if (level) { 168 GIC_SET_LEVEL(irq, cm); 169 DPRINTF("Set %d pending mask %x\n", irq, target); 170 if (GIC_TEST_EDGE_TRIGGER(irq)) { 171 GIC_SET_PENDING(irq, target); 172 } 173 } else { 174 GIC_CLEAR_LEVEL(irq, cm); 175 } 176 } 177 178 /* Process a change in an external IRQ input. */ 179 static void gic_set_irq(void *opaque, int irq, int level) 180 { 181 /* Meaning of the 'irq' parameter: 182 * [0..N-1] : external interrupts 183 * [N..N+31] : PPI (internal) interrupts for CPU 0 184 * [N+32..N+63] : PPI (internal interrupts for CPU 1 185 * ... 186 */ 187 GICState *s = (GICState *)opaque; 188 int cm, target; 189 if (irq < (s->num_irq - GIC_INTERNAL)) { 190 /* The first external input line is internal interrupt 32. */ 191 cm = ALL_CPU_MASK; 192 irq += GIC_INTERNAL; 193 target = GIC_TARGET(irq); 194 } else { 195 int cpu; 196 irq -= (s->num_irq - GIC_INTERNAL); 197 cpu = irq / GIC_INTERNAL; 198 irq %= GIC_INTERNAL; 199 cm = 1 << cpu; 200 target = cm; 201 } 202 203 assert(irq >= GIC_NR_SGIS); 204 205 if (level == GIC_TEST_LEVEL(irq, cm)) { 206 return; 207 } 208 209 if (s->revision == REV_11MPCORE) { 210 gic_set_irq_11mpcore(s, irq, level, cm, target); 211 } else { 212 gic_set_irq_generic(s, irq, level, cm, target); 213 } 214 trace_gic_set_irq(irq, level, cm, target); 215 216 gic_update(s); 217 } 218 219 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 220 MemTxAttrs attrs) 221 { 222 uint16_t pending_irq = s->current_pending[cpu]; 223 224 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 225 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 226 /* On a GIC without the security extensions, reading this register 227 * behaves in the same way as a secure access to a GIC with them. 228 */ 229 bool secure = !s->security_extn || attrs.secure; 230 231 if (group == 0 && !secure) { 232 /* Group0 interrupts hidden from Non-secure access */ 233 return 1023; 234 } 235 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 236 /* Group1 interrupts only seen by Secure access if 237 * AckCtl bit set. 238 */ 239 return 1022; 240 } 241 } 242 return pending_irq; 243 } 244 245 static int gic_get_group_priority(GICState *s, int cpu, int irq) 246 { 247 /* Return the group priority of the specified interrupt 248 * (which is the top bits of its priority, with the number 249 * of bits masked determined by the applicable binary point register). 250 */ 251 int bpr; 252 uint32_t mask; 253 254 if (gic_has_groups(s) && 255 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 256 GIC_TEST_GROUP(irq, (1 << cpu))) { 257 bpr = s->abpr[cpu]; 258 } else { 259 bpr = s->bpr[cpu]; 260 } 261 262 /* a BPR of 0 means the group priority bits are [7:1]; 263 * a BPR of 1 means they are [7:2], and so on down to 264 * a BPR of 7 meaning no group priority bits at all. 265 */ 266 mask = ~0U << ((bpr & 7) + 1); 267 268 return GIC_GET_PRIORITY(irq, cpu) & mask; 269 } 270 271 static void gic_activate_irq(GICState *s, int cpu, int irq) 272 { 273 /* Set the appropriate Active Priority Register bit for this IRQ, 274 * and update the running priority. 275 */ 276 int prio = gic_get_group_priority(s, cpu, irq); 277 int preemption_level = prio >> (GIC_MIN_BPR + 1); 278 int regno = preemption_level / 32; 279 int bitno = preemption_level % 32; 280 281 if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { 282 s->nsapr[regno][cpu] |= (1 << bitno); 283 } else { 284 s->apr[regno][cpu] |= (1 << bitno); 285 } 286 287 s->running_priority[cpu] = prio; 288 GIC_SET_ACTIVE(irq, 1 << cpu); 289 } 290 291 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 292 { 293 /* Recalculate the current running priority for this CPU based 294 * on the set bits in the Active Priority Registers. 295 */ 296 int i; 297 for (i = 0; i < GIC_NR_APRS; i++) { 298 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 299 if (!apr) { 300 continue; 301 } 302 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 303 } 304 return 0x100; 305 } 306 307 static void gic_drop_prio(GICState *s, int cpu, int group) 308 { 309 /* Drop the priority of the currently active interrupt in the 310 * specified group. 311 * 312 * Note that we can guarantee (because of the requirement to nest 313 * GICC_IAR reads [which activate an interrupt and raise priority] 314 * with GICC_EOIR writes [which drop the priority for the interrupt]) 315 * that the interrupt we're being called for is the highest priority 316 * active interrupt, meaning that it has the lowest set bit in the 317 * APR registers. 318 * 319 * If the guest does not honour the ordering constraints then the 320 * behaviour of the GIC is UNPREDICTABLE, which for us means that 321 * the values of the APR registers might become incorrect and the 322 * running priority will be wrong, so interrupts that should preempt 323 * might not do so, and interrupts that should not preempt might do so. 324 */ 325 int i; 326 327 for (i = 0; i < GIC_NR_APRS; i++) { 328 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 329 if (!*papr) { 330 continue; 331 } 332 /* Clear lowest set bit */ 333 *papr &= *papr - 1; 334 break; 335 } 336 337 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 338 } 339 340 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 341 { 342 int ret, irq, src; 343 int cm = 1 << cpu; 344 345 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 346 * for the case where this GIC supports grouping and the pending interrupt 347 * is in the wrong group. 348 */ 349 irq = gic_get_current_pending_irq(s, cpu, attrs); 350 trace_gic_acknowledge_irq(cpu, irq); 351 352 if (irq >= GIC_MAXIRQ) { 353 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 354 return irq; 355 } 356 357 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 358 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 359 return 1023; 360 } 361 362 if (s->revision == REV_11MPCORE) { 363 /* Clear pending flags for both level and edge triggered interrupts. 364 * Level triggered IRQs will be reasserted once they become inactive. 365 */ 366 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 367 ret = irq; 368 } else { 369 if (irq < GIC_NR_SGIS) { 370 /* Lookup the source CPU for the SGI and clear this in the 371 * sgi_pending map. Return the src and clear the overall pending 372 * state on this CPU if the SGI is not pending from any CPUs. 373 */ 374 assert(s->sgi_pending[irq][cpu] != 0); 375 src = ctz32(s->sgi_pending[irq][cpu]); 376 s->sgi_pending[irq][cpu] &= ~(1 << src); 377 if (s->sgi_pending[irq][cpu] == 0) { 378 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 379 } 380 ret = irq | ((src & 0x7) << 10); 381 } else { 382 /* Clear pending state for both level and edge triggered 383 * interrupts. (level triggered interrupts with an active line 384 * remain pending, see gic_test_pending) 385 */ 386 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 387 ret = irq; 388 } 389 } 390 391 gic_activate_irq(s, cpu, irq); 392 gic_update(s); 393 DPRINTF("ACK %d\n", irq); 394 return ret; 395 } 396 397 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 398 MemTxAttrs attrs) 399 { 400 if (s->security_extn && !attrs.secure) { 401 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 402 return; /* Ignore Non-secure access of Group0 IRQ */ 403 } 404 val = 0x80 | (val >> 1); /* Non-secure view */ 405 } 406 407 if (irq < GIC_INTERNAL) { 408 s->priority1[irq][cpu] = val; 409 } else { 410 s->priority2[(irq) - GIC_INTERNAL] = val; 411 } 412 } 413 414 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 415 MemTxAttrs attrs) 416 { 417 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 418 419 if (s->security_extn && !attrs.secure) { 420 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 421 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 422 } 423 prio = (prio << 1) & 0xff; /* Non-secure view */ 424 } 425 return prio; 426 } 427 428 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 429 MemTxAttrs attrs) 430 { 431 if (s->security_extn && !attrs.secure) { 432 if (s->priority_mask[cpu] & 0x80) { 433 /* Priority Mask in upper half */ 434 pmask = 0x80 | (pmask >> 1); 435 } else { 436 /* Non-secure write ignored if priority mask is in lower half */ 437 return; 438 } 439 } 440 s->priority_mask[cpu] = pmask; 441 } 442 443 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 444 { 445 uint32_t pmask = s->priority_mask[cpu]; 446 447 if (s->security_extn && !attrs.secure) { 448 if (pmask & 0x80) { 449 /* Priority Mask in upper half, return Non-secure view */ 450 pmask = (pmask << 1) & 0xff; 451 } else { 452 /* Priority Mask in lower half, RAZ */ 453 pmask = 0; 454 } 455 } 456 return pmask; 457 } 458 459 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 460 { 461 uint32_t ret = s->cpu_ctlr[cpu]; 462 463 if (s->security_extn && !attrs.secure) { 464 /* Construct the NS banked view of GICC_CTLR from the correct 465 * bits of the S banked view. We don't need to move the bypass 466 * control bits because we don't implement that (IMPDEF) part 467 * of the GIC architecture. 468 */ 469 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 470 } 471 return ret; 472 } 473 474 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 475 MemTxAttrs attrs) 476 { 477 uint32_t mask; 478 479 if (s->security_extn && !attrs.secure) { 480 /* The NS view can only write certain bits in the register; 481 * the rest are unchanged 482 */ 483 mask = GICC_CTLR_EN_GRP1; 484 if (s->revision == 2) { 485 mask |= GICC_CTLR_EOIMODE_NS; 486 } 487 s->cpu_ctlr[cpu] &= ~mask; 488 s->cpu_ctlr[cpu] |= (value << 1) & mask; 489 } else { 490 if (s->revision == 2) { 491 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 492 } else { 493 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 494 } 495 s->cpu_ctlr[cpu] = value & mask; 496 } 497 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 498 "Group1 Interrupts %sabled\n", cpu, 499 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 500 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 501 } 502 503 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 504 { 505 if (s->security_extn && !attrs.secure) { 506 if (s->running_priority[cpu] & 0x80) { 507 /* Running priority in upper half of range: return the Non-secure 508 * view of the priority. 509 */ 510 return s->running_priority[cpu] << 1; 511 } else { 512 /* Running priority in lower half of range: RAZ */ 513 return 0; 514 } 515 } else { 516 return s->running_priority[cpu]; 517 } 518 } 519 520 /* Return true if we should split priority drop and interrupt deactivation, 521 * ie whether the relevant EOIMode bit is set. 522 */ 523 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 524 { 525 if (s->revision != 2) { 526 /* Before GICv2 prio-drop and deactivate are not separable */ 527 return false; 528 } 529 if (s->security_extn && !attrs.secure) { 530 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 531 } 532 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 533 } 534 535 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 536 { 537 int cm = 1 << cpu; 538 int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 539 540 if (!gic_eoi_split(s, cpu, attrs)) { 541 /* This is UNPREDICTABLE; we choose to ignore it */ 542 qemu_log_mask(LOG_GUEST_ERROR, 543 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 544 return; 545 } 546 547 if (s->security_extn && !attrs.secure && !group) { 548 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 549 return; 550 } 551 552 GIC_CLEAR_ACTIVE(irq, cm); 553 } 554 555 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 556 { 557 int cm = 1 << cpu; 558 int group; 559 560 DPRINTF("EOI %d\n", irq); 561 if (irq >= s->num_irq) { 562 /* This handles two cases: 563 * 1. If software writes the ID of a spurious interrupt [ie 1023] 564 * to the GICC_EOIR, the GIC ignores that write. 565 * 2. If software writes the number of a non-existent interrupt 566 * this must be a subcase of "value written does not match the last 567 * valid interrupt value read from the Interrupt Acknowledge 568 * register" and so this is UNPREDICTABLE. We choose to ignore it. 569 */ 570 return; 571 } 572 if (s->running_priority[cpu] == 0x100) { 573 return; /* No active IRQ. */ 574 } 575 576 if (s->revision == REV_11MPCORE) { 577 /* Mark level triggered interrupts as pending if they are still 578 raised. */ 579 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 580 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 581 DPRINTF("Set %d pending mask %x\n", irq, cm); 582 GIC_SET_PENDING(irq, cm); 583 } 584 } 585 586 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); 587 588 if (s->security_extn && !attrs.secure && !group) { 589 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 590 return; 591 } 592 593 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 594 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 595 * i.e. go ahead and complete the irq anyway. 596 */ 597 598 gic_drop_prio(s, cpu, group); 599 600 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 601 if (!gic_eoi_split(s, cpu, attrs)) { 602 GIC_CLEAR_ACTIVE(irq, cm); 603 } 604 gic_update(s); 605 } 606 607 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 608 { 609 GICState *s = (GICState *)opaque; 610 uint32_t res; 611 int irq; 612 int i; 613 int cpu; 614 int cm; 615 int mask; 616 617 cpu = gic_get_current_cpu(s); 618 cm = 1 << cpu; 619 if (offset < 0x100) { 620 if (offset == 0) { /* GICD_CTLR */ 621 if (s->security_extn && !attrs.secure) { 622 /* The NS bank of this register is just an alias of the 623 * EnableGrp1 bit in the S bank version. 624 */ 625 return extract32(s->ctlr, 1, 1); 626 } else { 627 return s->ctlr; 628 } 629 } 630 if (offset == 4) 631 /* Interrupt Controller Type Register */ 632 return ((s->num_irq / 32) - 1) 633 | ((s->num_cpu - 1) << 5) 634 | (s->security_extn << 10); 635 if (offset < 0x08) 636 return 0; 637 if (offset >= 0x80) { 638 /* Interrupt Group Registers: these RAZ/WI if this is an NS 639 * access to a GIC with the security extensions, or if the GIC 640 * doesn't have groups at all. 641 */ 642 res = 0; 643 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 644 /* Every byte offset holds 8 group status bits */ 645 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 646 if (irq >= s->num_irq) { 647 goto bad_reg; 648 } 649 for (i = 0; i < 8; i++) { 650 if (GIC_TEST_GROUP(irq + i, cm)) { 651 res |= (1 << i); 652 } 653 } 654 } 655 return res; 656 } 657 goto bad_reg; 658 } else if (offset < 0x200) { 659 /* Interrupt Set/Clear Enable. */ 660 if (offset < 0x180) 661 irq = (offset - 0x100) * 8; 662 else 663 irq = (offset - 0x180) * 8; 664 irq += GIC_BASE_IRQ; 665 if (irq >= s->num_irq) 666 goto bad_reg; 667 res = 0; 668 for (i = 0; i < 8; i++) { 669 if (s->security_extn && !attrs.secure && 670 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 671 continue; /* Ignore Non-secure access of Group0 IRQ */ 672 } 673 674 if (GIC_TEST_ENABLED(irq + i, cm)) { 675 res |= (1 << i); 676 } 677 } 678 } else if (offset < 0x300) { 679 /* Interrupt Set/Clear Pending. */ 680 if (offset < 0x280) 681 irq = (offset - 0x200) * 8; 682 else 683 irq = (offset - 0x280) * 8; 684 irq += GIC_BASE_IRQ; 685 if (irq >= s->num_irq) 686 goto bad_reg; 687 res = 0; 688 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 689 for (i = 0; i < 8; i++) { 690 if (s->security_extn && !attrs.secure && 691 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 692 continue; /* Ignore Non-secure access of Group0 IRQ */ 693 } 694 695 if (gic_test_pending(s, irq + i, mask)) { 696 res |= (1 << i); 697 } 698 } 699 } else if (offset < 0x400) { 700 /* Interrupt Active. */ 701 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 702 if (irq >= s->num_irq) 703 goto bad_reg; 704 res = 0; 705 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 706 for (i = 0; i < 8; i++) { 707 if (s->security_extn && !attrs.secure && 708 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 709 continue; /* Ignore Non-secure access of Group0 IRQ */ 710 } 711 712 if (GIC_TEST_ACTIVE(irq + i, mask)) { 713 res |= (1 << i); 714 } 715 } 716 } else if (offset < 0x800) { 717 /* Interrupt Priority. */ 718 irq = (offset - 0x400) + GIC_BASE_IRQ; 719 if (irq >= s->num_irq) 720 goto bad_reg; 721 res = gic_get_priority(s, cpu, irq, attrs); 722 } else if (offset < 0xc00) { 723 /* Interrupt CPU Target. */ 724 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 725 /* For uniprocessor GICs these RAZ/WI */ 726 res = 0; 727 } else { 728 irq = (offset - 0x800) + GIC_BASE_IRQ; 729 if (irq >= s->num_irq) { 730 goto bad_reg; 731 } 732 if (irq >= 29 && irq <= 31) { 733 res = cm; 734 } else { 735 res = GIC_TARGET(irq); 736 } 737 } 738 } else if (offset < 0xf00) { 739 /* Interrupt Configuration. */ 740 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 741 if (irq >= s->num_irq) 742 goto bad_reg; 743 res = 0; 744 for (i = 0; i < 4; i++) { 745 if (s->security_extn && !attrs.secure && 746 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 747 continue; /* Ignore Non-secure access of Group0 IRQ */ 748 } 749 750 if (GIC_TEST_MODEL(irq + i)) 751 res |= (1 << (i * 2)); 752 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 753 res |= (2 << (i * 2)); 754 } 755 } else if (offset < 0xf10) { 756 goto bad_reg; 757 } else if (offset < 0xf30) { 758 if (s->revision == REV_11MPCORE) { 759 goto bad_reg; 760 } 761 762 if (offset < 0xf20) { 763 /* GICD_CPENDSGIRn */ 764 irq = (offset - 0xf10); 765 } else { 766 irq = (offset - 0xf20); 767 /* GICD_SPENDSGIRn */ 768 } 769 770 if (s->security_extn && !attrs.secure && 771 !GIC_TEST_GROUP(irq, 1 << cpu)) { 772 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 773 } else { 774 res = s->sgi_pending[irq][cpu]; 775 } 776 } else if (offset < 0xfd0) { 777 goto bad_reg; 778 } else if (offset < 0x1000) { 779 if (offset & 3) { 780 res = 0; 781 } else { 782 switch (s->revision) { 783 case REV_11MPCORE: 784 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 785 break; 786 case 1: 787 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 788 break; 789 case 2: 790 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 791 break; 792 default: 793 res = 0; 794 } 795 } 796 } else { 797 g_assert_not_reached(); 798 } 799 return res; 800 bad_reg: 801 qemu_log_mask(LOG_GUEST_ERROR, 802 "gic_dist_readb: Bad offset %x\n", (int)offset); 803 return 0; 804 } 805 806 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 807 unsigned size, MemTxAttrs attrs) 808 { 809 switch (size) { 810 case 1: 811 *data = gic_dist_readb(opaque, offset, attrs); 812 return MEMTX_OK; 813 case 2: 814 *data = gic_dist_readb(opaque, offset, attrs); 815 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 816 return MEMTX_OK; 817 case 4: 818 *data = gic_dist_readb(opaque, offset, attrs); 819 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 820 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 821 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 822 return MEMTX_OK; 823 default: 824 return MEMTX_ERROR; 825 } 826 } 827 828 static void gic_dist_writeb(void *opaque, hwaddr offset, 829 uint32_t value, MemTxAttrs attrs) 830 { 831 GICState *s = (GICState *)opaque; 832 int irq; 833 int i; 834 int cpu; 835 836 cpu = gic_get_current_cpu(s); 837 if (offset < 0x100) { 838 if (offset == 0) { 839 if (s->security_extn && !attrs.secure) { 840 /* NS version is just an alias of the S version's bit 1 */ 841 s->ctlr = deposit32(s->ctlr, 1, 1, value); 842 } else if (gic_has_groups(s)) { 843 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 844 } else { 845 s->ctlr = value & GICD_CTLR_EN_GRP0; 846 } 847 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 848 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 849 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 850 } else if (offset < 4) { 851 /* ignored. */ 852 } else if (offset >= 0x80) { 853 /* Interrupt Group Registers: RAZ/WI for NS access to secure 854 * GIC, or for GICs without groups. 855 */ 856 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 857 /* Every byte offset holds 8 group status bits */ 858 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 859 if (irq >= s->num_irq) { 860 goto bad_reg; 861 } 862 for (i = 0; i < 8; i++) { 863 /* Group bits are banked for private interrupts */ 864 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 865 if (value & (1 << i)) { 866 /* Group1 (Non-secure) */ 867 GIC_SET_GROUP(irq + i, cm); 868 } else { 869 /* Group0 (Secure) */ 870 GIC_CLEAR_GROUP(irq + i, cm); 871 } 872 } 873 } 874 } else { 875 goto bad_reg; 876 } 877 } else if (offset < 0x180) { 878 /* Interrupt Set Enable. */ 879 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 880 if (irq >= s->num_irq) 881 goto bad_reg; 882 if (irq < GIC_NR_SGIS) { 883 value = 0xff; 884 } 885 886 for (i = 0; i < 8; i++) { 887 if (value & (1 << i)) { 888 int mask = 889 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 890 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 891 892 if (s->security_extn && !attrs.secure && 893 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 894 continue; /* Ignore Non-secure access of Group0 IRQ */ 895 } 896 897 if (!GIC_TEST_ENABLED(irq + i, cm)) { 898 DPRINTF("Enabled IRQ %d\n", irq + i); 899 trace_gic_enable_irq(irq + i); 900 } 901 GIC_SET_ENABLED(irq + i, cm); 902 /* If a raised level triggered IRQ enabled then mark 903 is as pending. */ 904 if (GIC_TEST_LEVEL(irq + i, mask) 905 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 906 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 907 GIC_SET_PENDING(irq + i, mask); 908 } 909 } 910 } 911 } else if (offset < 0x200) { 912 /* Interrupt Clear Enable. */ 913 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 914 if (irq >= s->num_irq) 915 goto bad_reg; 916 if (irq < GIC_NR_SGIS) { 917 value = 0; 918 } 919 920 for (i = 0; i < 8; i++) { 921 if (value & (1 << i)) { 922 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 923 924 if (s->security_extn && !attrs.secure && 925 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 926 continue; /* Ignore Non-secure access of Group0 IRQ */ 927 } 928 929 if (GIC_TEST_ENABLED(irq + i, cm)) { 930 DPRINTF("Disabled IRQ %d\n", irq + i); 931 trace_gic_disable_irq(irq + i); 932 } 933 GIC_CLEAR_ENABLED(irq + i, cm); 934 } 935 } 936 } else if (offset < 0x280) { 937 /* Interrupt Set Pending. */ 938 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 939 if (irq >= s->num_irq) 940 goto bad_reg; 941 if (irq < GIC_NR_SGIS) { 942 value = 0; 943 } 944 945 for (i = 0; i < 8; i++) { 946 if (value & (1 << i)) { 947 if (s->security_extn && !attrs.secure && 948 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 949 continue; /* Ignore Non-secure access of Group0 IRQ */ 950 } 951 952 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 953 } 954 } 955 } else if (offset < 0x300) { 956 /* Interrupt Clear Pending. */ 957 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 958 if (irq >= s->num_irq) 959 goto bad_reg; 960 if (irq < GIC_NR_SGIS) { 961 value = 0; 962 } 963 964 for (i = 0; i < 8; i++) { 965 if (s->security_extn && !attrs.secure && 966 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 967 continue; /* Ignore Non-secure access of Group0 IRQ */ 968 } 969 970 /* ??? This currently clears the pending bit for all CPUs, even 971 for per-CPU interrupts. It's unclear whether this is the 972 corect behavior. */ 973 if (value & (1 << i)) { 974 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 975 } 976 } 977 } else if (offset < 0x400) { 978 /* Interrupt Active. */ 979 goto bad_reg; 980 } else if (offset < 0x800) { 981 /* Interrupt Priority. */ 982 irq = (offset - 0x400) + GIC_BASE_IRQ; 983 if (irq >= s->num_irq) 984 goto bad_reg; 985 gic_set_priority(s, cpu, irq, value, attrs); 986 } else if (offset < 0xc00) { 987 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 988 * annoying exception of the 11MPCore's GIC. 989 */ 990 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 991 irq = (offset - 0x800) + GIC_BASE_IRQ; 992 if (irq >= s->num_irq) { 993 goto bad_reg; 994 } 995 if (irq < 29) { 996 value = 0; 997 } else if (irq < GIC_INTERNAL) { 998 value = ALL_CPU_MASK; 999 } 1000 s->irq_target[irq] = value & ALL_CPU_MASK; 1001 } 1002 } else if (offset < 0xf00) { 1003 /* Interrupt Configuration. */ 1004 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1005 if (irq >= s->num_irq) 1006 goto bad_reg; 1007 if (irq < GIC_NR_SGIS) 1008 value |= 0xaa; 1009 for (i = 0; i < 4; i++) { 1010 if (s->security_extn && !attrs.secure && 1011 !GIC_TEST_GROUP(irq + i, 1 << cpu)) { 1012 continue; /* Ignore Non-secure access of Group0 IRQ */ 1013 } 1014 1015 if (s->revision == REV_11MPCORE) { 1016 if (value & (1 << (i * 2))) { 1017 GIC_SET_MODEL(irq + i); 1018 } else { 1019 GIC_CLEAR_MODEL(irq + i); 1020 } 1021 } 1022 if (value & (2 << (i * 2))) { 1023 GIC_SET_EDGE_TRIGGER(irq + i); 1024 } else { 1025 GIC_CLEAR_EDGE_TRIGGER(irq + i); 1026 } 1027 } 1028 } else if (offset < 0xf10) { 1029 /* 0xf00 is only handled for 32-bit writes. */ 1030 goto bad_reg; 1031 } else if (offset < 0xf20) { 1032 /* GICD_CPENDSGIRn */ 1033 if (s->revision == REV_11MPCORE) { 1034 goto bad_reg; 1035 } 1036 irq = (offset - 0xf10); 1037 1038 if (!s->security_extn || attrs.secure || 1039 GIC_TEST_GROUP(irq, 1 << cpu)) { 1040 s->sgi_pending[irq][cpu] &= ~value; 1041 if (s->sgi_pending[irq][cpu] == 0) { 1042 GIC_CLEAR_PENDING(irq, 1 << cpu); 1043 } 1044 } 1045 } else if (offset < 0xf30) { 1046 /* GICD_SPENDSGIRn */ 1047 if (s->revision == REV_11MPCORE) { 1048 goto bad_reg; 1049 } 1050 irq = (offset - 0xf20); 1051 1052 if (!s->security_extn || attrs.secure || 1053 GIC_TEST_GROUP(irq, 1 << cpu)) { 1054 GIC_SET_PENDING(irq, 1 << cpu); 1055 s->sgi_pending[irq][cpu] |= value; 1056 } 1057 } else { 1058 goto bad_reg; 1059 } 1060 gic_update(s); 1061 return; 1062 bad_reg: 1063 qemu_log_mask(LOG_GUEST_ERROR, 1064 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1065 } 1066 1067 static void gic_dist_writew(void *opaque, hwaddr offset, 1068 uint32_t value, MemTxAttrs attrs) 1069 { 1070 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1071 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1072 } 1073 1074 static void gic_dist_writel(void *opaque, hwaddr offset, 1075 uint32_t value, MemTxAttrs attrs) 1076 { 1077 GICState *s = (GICState *)opaque; 1078 if (offset == 0xf00) { 1079 int cpu; 1080 int irq; 1081 int mask; 1082 int target_cpu; 1083 1084 cpu = gic_get_current_cpu(s); 1085 irq = value & 0x3ff; 1086 switch ((value >> 24) & 3) { 1087 case 0: 1088 mask = (value >> 16) & ALL_CPU_MASK; 1089 break; 1090 case 1: 1091 mask = ALL_CPU_MASK ^ (1 << cpu); 1092 break; 1093 case 2: 1094 mask = 1 << cpu; 1095 break; 1096 default: 1097 DPRINTF("Bad Soft Int target filter\n"); 1098 mask = ALL_CPU_MASK; 1099 break; 1100 } 1101 GIC_SET_PENDING(irq, mask); 1102 target_cpu = ctz32(mask); 1103 while (target_cpu < GIC_NCPU) { 1104 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1105 mask &= ~(1 << target_cpu); 1106 target_cpu = ctz32(mask); 1107 } 1108 gic_update(s); 1109 return; 1110 } 1111 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1112 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1113 } 1114 1115 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1116 unsigned size, MemTxAttrs attrs) 1117 { 1118 switch (size) { 1119 case 1: 1120 gic_dist_writeb(opaque, offset, data, attrs); 1121 return MEMTX_OK; 1122 case 2: 1123 gic_dist_writew(opaque, offset, data, attrs); 1124 return MEMTX_OK; 1125 case 4: 1126 gic_dist_writel(opaque, offset, data, attrs); 1127 return MEMTX_OK; 1128 default: 1129 return MEMTX_ERROR; 1130 } 1131 } 1132 1133 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1134 { 1135 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1136 * second half of GICC_NSAPR. 1137 */ 1138 switch (GIC_MIN_BPR) { 1139 case 0: 1140 if (regno < 2) { 1141 return s->nsapr[regno + 2][cpu]; 1142 } 1143 break; 1144 case 1: 1145 if (regno == 0) { 1146 return s->nsapr[regno + 1][cpu]; 1147 } 1148 break; 1149 case 2: 1150 if (regno == 0) { 1151 return extract32(s->nsapr[0][cpu], 16, 16); 1152 } 1153 break; 1154 case 3: 1155 if (regno == 0) { 1156 return extract32(s->nsapr[0][cpu], 8, 8); 1157 } 1158 break; 1159 default: 1160 g_assert_not_reached(); 1161 } 1162 return 0; 1163 } 1164 1165 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1166 uint32_t value) 1167 { 1168 /* Write the Nonsecure view of GICC_APR<regno>. */ 1169 switch (GIC_MIN_BPR) { 1170 case 0: 1171 if (regno < 2) { 1172 s->nsapr[regno + 2][cpu] = value; 1173 } 1174 break; 1175 case 1: 1176 if (regno == 0) { 1177 s->nsapr[regno + 1][cpu] = value; 1178 } 1179 break; 1180 case 2: 1181 if (regno == 0) { 1182 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1183 } 1184 break; 1185 case 3: 1186 if (regno == 0) { 1187 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1188 } 1189 break; 1190 default: 1191 g_assert_not_reached(); 1192 } 1193 } 1194 1195 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1196 uint64_t *data, MemTxAttrs attrs) 1197 { 1198 switch (offset) { 1199 case 0x00: /* Control */ 1200 *data = gic_get_cpu_control(s, cpu, attrs); 1201 break; 1202 case 0x04: /* Priority mask */ 1203 *data = gic_get_priority_mask(s, cpu, attrs); 1204 break; 1205 case 0x08: /* Binary Point */ 1206 if (s->security_extn && !attrs.secure) { 1207 /* BPR is banked. Non-secure copy stored in ABPR. */ 1208 *data = s->abpr[cpu]; 1209 } else { 1210 *data = s->bpr[cpu]; 1211 } 1212 break; 1213 case 0x0c: /* Acknowledge */ 1214 *data = gic_acknowledge_irq(s, cpu, attrs); 1215 break; 1216 case 0x14: /* Running Priority */ 1217 *data = gic_get_running_priority(s, cpu, attrs); 1218 break; 1219 case 0x18: /* Highest Pending Interrupt */ 1220 *data = gic_get_current_pending_irq(s, cpu, attrs); 1221 break; 1222 case 0x1c: /* Aliased Binary Point */ 1223 /* GIC v2, no security: ABPR 1224 * GIC v1, no security: not implemented (RAZ/WI) 1225 * With security extensions, secure access: ABPR (alias of NS BPR) 1226 * With security extensions, nonsecure access: RAZ/WI 1227 */ 1228 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1229 *data = 0; 1230 } else { 1231 *data = s->abpr[cpu]; 1232 } 1233 break; 1234 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1235 { 1236 int regno = (offset - 0xd0) / 4; 1237 1238 if (regno >= GIC_NR_APRS || s->revision != 2) { 1239 *data = 0; 1240 } else if (s->security_extn && !attrs.secure) { 1241 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1242 *data = gic_apr_ns_view(s, regno, cpu); 1243 } else { 1244 *data = s->apr[regno][cpu]; 1245 } 1246 break; 1247 } 1248 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1249 { 1250 int regno = (offset - 0xe0) / 4; 1251 1252 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1253 (s->security_extn && !attrs.secure)) { 1254 *data = 0; 1255 } else { 1256 *data = s->nsapr[regno][cpu]; 1257 } 1258 break; 1259 } 1260 default: 1261 qemu_log_mask(LOG_GUEST_ERROR, 1262 "gic_cpu_read: Bad offset %x\n", (int)offset); 1263 return MEMTX_ERROR; 1264 } 1265 return MEMTX_OK; 1266 } 1267 1268 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1269 uint32_t value, MemTxAttrs attrs) 1270 { 1271 switch (offset) { 1272 case 0x00: /* Control */ 1273 gic_set_cpu_control(s, cpu, value, attrs); 1274 break; 1275 case 0x04: /* Priority mask */ 1276 gic_set_priority_mask(s, cpu, value, attrs); 1277 break; 1278 case 0x08: /* Binary Point */ 1279 if (s->security_extn && !attrs.secure) { 1280 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1281 } else { 1282 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1283 } 1284 break; 1285 case 0x10: /* End Of Interrupt */ 1286 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1287 return MEMTX_OK; 1288 case 0x1c: /* Aliased Binary Point */ 1289 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1290 /* unimplemented, or NS access: RAZ/WI */ 1291 return MEMTX_OK; 1292 } else { 1293 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1294 } 1295 break; 1296 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1297 { 1298 int regno = (offset - 0xd0) / 4; 1299 1300 if (regno >= GIC_NR_APRS || s->revision != 2) { 1301 return MEMTX_OK; 1302 } 1303 if (s->security_extn && !attrs.secure) { 1304 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1305 gic_apr_write_ns_view(s, regno, cpu, value); 1306 } else { 1307 s->apr[regno][cpu] = value; 1308 } 1309 break; 1310 } 1311 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1312 { 1313 int regno = (offset - 0xe0) / 4; 1314 1315 if (regno >= GIC_NR_APRS || s->revision != 2) { 1316 return MEMTX_OK; 1317 } 1318 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1319 return MEMTX_OK; 1320 } 1321 s->nsapr[regno][cpu] = value; 1322 break; 1323 } 1324 case 0x1000: 1325 /* GICC_DIR */ 1326 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1327 break; 1328 default: 1329 qemu_log_mask(LOG_GUEST_ERROR, 1330 "gic_cpu_write: Bad offset %x\n", (int)offset); 1331 return MEMTX_ERROR; 1332 } 1333 gic_update(s); 1334 return MEMTX_OK; 1335 } 1336 1337 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1338 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1339 unsigned size, MemTxAttrs attrs) 1340 { 1341 GICState *s = (GICState *)opaque; 1342 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1343 } 1344 1345 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1346 uint64_t value, unsigned size, 1347 MemTxAttrs attrs) 1348 { 1349 GICState *s = (GICState *)opaque; 1350 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1351 } 1352 1353 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1354 * These just decode the opaque pointer into GICState* + cpu id. 1355 */ 1356 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1357 unsigned size, MemTxAttrs attrs) 1358 { 1359 GICState **backref = (GICState **)opaque; 1360 GICState *s = *backref; 1361 int id = (backref - s->backref); 1362 return gic_cpu_read(s, id, addr, data, attrs); 1363 } 1364 1365 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1366 uint64_t value, unsigned size, 1367 MemTxAttrs attrs) 1368 { 1369 GICState **backref = (GICState **)opaque; 1370 GICState *s = *backref; 1371 int id = (backref - s->backref); 1372 return gic_cpu_write(s, id, addr, value, attrs); 1373 } 1374 1375 static const MemoryRegionOps gic_ops[2] = { 1376 { 1377 .read_with_attrs = gic_dist_read, 1378 .write_with_attrs = gic_dist_write, 1379 .endianness = DEVICE_NATIVE_ENDIAN, 1380 }, 1381 { 1382 .read_with_attrs = gic_thiscpu_read, 1383 .write_with_attrs = gic_thiscpu_write, 1384 .endianness = DEVICE_NATIVE_ENDIAN, 1385 } 1386 }; 1387 1388 static const MemoryRegionOps gic_cpu_ops = { 1389 .read_with_attrs = gic_do_cpu_read, 1390 .write_with_attrs = gic_do_cpu_write, 1391 .endianness = DEVICE_NATIVE_ENDIAN, 1392 }; 1393 1394 /* This function is used by nvic model */ 1395 void gic_init_irqs_and_distributor(GICState *s) 1396 { 1397 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1398 } 1399 1400 static void arm_gic_realize(DeviceState *dev, Error **errp) 1401 { 1402 /* Device instance realize function for the GIC sysbus device */ 1403 int i; 1404 GICState *s = ARM_GIC(dev); 1405 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1406 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1407 Error *local_err = NULL; 1408 1409 agc->parent_realize(dev, &local_err); 1410 if (local_err) { 1411 error_propagate(errp, local_err); 1412 return; 1413 } 1414 1415 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1416 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); 1417 1418 /* Extra core-specific regions for the CPU interfaces. This is 1419 * necessary for "franken-GIC" implementations, for example on 1420 * Exynos 4. 1421 * NB that the memory region size of 0x100 applies for the 11MPCore 1422 * and also cores following the GIC v1 spec (ie A9). 1423 * GIC v2 defines a larger memory region (0x1000) so this will need 1424 * to be extended when we implement A15. 1425 */ 1426 for (i = 0; i < s->num_cpu; i++) { 1427 s->backref[i] = s; 1428 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1429 &s->backref[i], "gic_cpu", 0x100); 1430 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1431 } 1432 } 1433 1434 static void arm_gic_class_init(ObjectClass *klass, void *data) 1435 { 1436 DeviceClass *dc = DEVICE_CLASS(klass); 1437 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1438 1439 agc->parent_realize = dc->realize; 1440 dc->realize = arm_gic_realize; 1441 } 1442 1443 static const TypeInfo arm_gic_info = { 1444 .name = TYPE_ARM_GIC, 1445 .parent = TYPE_ARM_GIC_COMMON, 1446 .instance_size = sizeof(GICState), 1447 .class_init = arm_gic_class_init, 1448 .class_size = sizeof(ARMGICClass), 1449 }; 1450 1451 static void arm_gic_register_types(void) 1452 { 1453 type_register_static(&arm_gic_info); 1454 } 1455 1456 type_init(arm_gic_register_types) 1457