1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "gic_internal.h" 24 #include "qapi/error.h" 25 #include "qom/cpu.h" 26 #include "qemu/log.h" 27 #include "trace.h" 28 #include "sysemu/kvm.h" 29 30 /* #define DEBUG_GIC */ 31 32 #ifdef DEBUG_GIC 33 #define DEBUG_GIC_GATE 1 34 #else 35 #define DEBUG_GIC_GATE 0 36 #endif 37 38 #define DPRINTF(fmt, ...) do { \ 39 if (DEBUG_GIC_GATE) { \ 40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ 41 } \ 42 } while (0) 43 44 static const uint8_t gic_id_11mpcore[] = { 45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 46 }; 47 48 static const uint8_t gic_id_gicv1[] = { 49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 50 }; 51 52 static const uint8_t gic_id_gicv2[] = { 53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 54 }; 55 56 static inline int gic_get_current_cpu(GICState *s) 57 { 58 if (s->num_cpu > 1) { 59 return current_cpu->cpu_index; 60 } 61 return 0; 62 } 63 64 static inline int gic_get_current_vcpu(GICState *s) 65 { 66 return gic_get_current_cpu(s) + GIC_NCPU; 67 } 68 69 /* Return true if this GIC config has interrupt groups, which is 70 * true if we're a GICv2, or a GICv1 with the security extensions. 71 */ 72 static inline bool gic_has_groups(GICState *s) 73 { 74 return s->revision == 2 || s->security_extn; 75 } 76 77 static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs) 78 { 79 return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; 80 } 81 82 /* TODO: Many places that call this routine could be optimized. */ 83 /* Update interrupt status after enabled or pending bits have been changed. */ 84 static void gic_update(GICState *s) 85 { 86 int best_irq; 87 int best_prio; 88 int irq; 89 int irq_level, fiq_level; 90 int cpu; 91 int cm; 92 93 for (cpu = 0; cpu < s->num_cpu; cpu++) { 94 cm = 1 << cpu; 95 s->current_pending[cpu] = 1023; 96 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 97 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 98 qemu_irq_lower(s->parent_irq[cpu]); 99 qemu_irq_lower(s->parent_fiq[cpu]); 100 continue; 101 } 102 best_prio = 0x100; 103 best_irq = 1023; 104 for (irq = 0; irq < s->num_irq; irq++) { 105 if (GIC_DIST_TEST_ENABLED(irq, cm) && 106 gic_test_pending(s, irq, cm) && 107 (!GIC_DIST_TEST_ACTIVE(irq, cm)) && 108 (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { 109 if (GIC_DIST_GET_PRIORITY(irq, cpu) < best_prio) { 110 best_prio = GIC_DIST_GET_PRIORITY(irq, cpu); 111 best_irq = irq; 112 } 113 } 114 } 115 116 if (best_irq != 1023) { 117 trace_gic_update_bestirq(cpu, best_irq, best_prio, 118 s->priority_mask[cpu], s->running_priority[cpu]); 119 } 120 121 irq_level = fiq_level = 0; 122 123 if (best_prio < s->priority_mask[cpu]) { 124 s->current_pending[cpu] = best_irq; 125 if (best_prio < s->running_priority[cpu]) { 126 int group = GIC_DIST_TEST_GROUP(best_irq, cm); 127 128 if (extract32(s->ctlr, group, 1) && 129 extract32(s->cpu_ctlr[cpu], group, 1)) { 130 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 131 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 132 best_irq, cpu); 133 fiq_level = 1; 134 trace_gic_update_set_irq(cpu, "fiq", fiq_level); 135 } else { 136 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 137 best_irq, cpu); 138 irq_level = 1; 139 trace_gic_update_set_irq(cpu, "irq", irq_level); 140 } 141 } 142 } 143 } 144 145 qemu_set_irq(s->parent_irq[cpu], irq_level); 146 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 147 } 148 } 149 150 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 151 int cm, int target) 152 { 153 if (level) { 154 GIC_DIST_SET_LEVEL(irq, cm); 155 if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, cm)) { 156 DPRINTF("Set %d pending mask %x\n", irq, target); 157 GIC_DIST_SET_PENDING(irq, target); 158 } 159 } else { 160 GIC_DIST_CLEAR_LEVEL(irq, cm); 161 } 162 } 163 164 static void gic_set_irq_generic(GICState *s, int irq, int level, 165 int cm, int target) 166 { 167 if (level) { 168 GIC_DIST_SET_LEVEL(irq, cm); 169 DPRINTF("Set %d pending mask %x\n", irq, target); 170 if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) { 171 GIC_DIST_SET_PENDING(irq, target); 172 } 173 } else { 174 GIC_DIST_CLEAR_LEVEL(irq, cm); 175 } 176 } 177 178 /* Process a change in an external IRQ input. */ 179 static void gic_set_irq(void *opaque, int irq, int level) 180 { 181 /* Meaning of the 'irq' parameter: 182 * [0..N-1] : external interrupts 183 * [N..N+31] : PPI (internal) interrupts for CPU 0 184 * [N+32..N+63] : PPI (internal interrupts for CPU 1 185 * ... 186 */ 187 GICState *s = (GICState *)opaque; 188 int cm, target; 189 if (irq < (s->num_irq - GIC_INTERNAL)) { 190 /* The first external input line is internal interrupt 32. */ 191 cm = ALL_CPU_MASK; 192 irq += GIC_INTERNAL; 193 target = GIC_DIST_TARGET(irq); 194 } else { 195 int cpu; 196 irq -= (s->num_irq - GIC_INTERNAL); 197 cpu = irq / GIC_INTERNAL; 198 irq %= GIC_INTERNAL; 199 cm = 1 << cpu; 200 target = cm; 201 } 202 203 assert(irq >= GIC_NR_SGIS); 204 205 if (level == GIC_DIST_TEST_LEVEL(irq, cm)) { 206 return; 207 } 208 209 if (s->revision == REV_11MPCORE) { 210 gic_set_irq_11mpcore(s, irq, level, cm, target); 211 } else { 212 gic_set_irq_generic(s, irq, level, cm, target); 213 } 214 trace_gic_set_irq(irq, level, cm, target); 215 216 gic_update(s); 217 } 218 219 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 220 MemTxAttrs attrs) 221 { 222 uint16_t pending_irq = s->current_pending[cpu]; 223 224 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 225 int group = GIC_DIST_TEST_GROUP(pending_irq, (1 << cpu)); 226 /* On a GIC without the security extensions, reading this register 227 * behaves in the same way as a secure access to a GIC with them. 228 */ 229 bool secure = !gic_cpu_ns_access(s, cpu, attrs); 230 231 if (group == 0 && !secure) { 232 /* Group0 interrupts hidden from Non-secure access */ 233 return 1023; 234 } 235 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 236 /* Group1 interrupts only seen by Secure access if 237 * AckCtl bit set. 238 */ 239 return 1022; 240 } 241 } 242 return pending_irq; 243 } 244 245 static int gic_get_group_priority(GICState *s, int cpu, int irq) 246 { 247 /* Return the group priority of the specified interrupt 248 * (which is the top bits of its priority, with the number 249 * of bits masked determined by the applicable binary point register). 250 */ 251 int bpr; 252 uint32_t mask; 253 254 if (gic_has_groups(s) && 255 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && 256 GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 257 bpr = s->abpr[cpu] - 1; 258 assert(bpr >= 0); 259 } else { 260 bpr = s->bpr[cpu]; 261 } 262 263 /* a BPR of 0 means the group priority bits are [7:1]; 264 * a BPR of 1 means they are [7:2], and so on down to 265 * a BPR of 7 meaning no group priority bits at all. 266 */ 267 mask = ~0U << ((bpr & 7) + 1); 268 269 return GIC_DIST_GET_PRIORITY(irq, cpu) & mask; 270 } 271 272 static void gic_activate_irq(GICState *s, int cpu, int irq) 273 { 274 /* Set the appropriate Active Priority Register bit for this IRQ, 275 * and update the running priority. 276 */ 277 int prio = gic_get_group_priority(s, cpu, irq); 278 int preemption_level = prio >> (GIC_MIN_BPR + 1); 279 int regno = preemption_level / 32; 280 int bitno = preemption_level % 32; 281 282 if (gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 283 s->nsapr[regno][cpu] |= (1 << bitno); 284 } else { 285 s->apr[regno][cpu] |= (1 << bitno); 286 } 287 288 s->running_priority[cpu] = prio; 289 GIC_DIST_SET_ACTIVE(irq, 1 << cpu); 290 } 291 292 static int gic_get_prio_from_apr_bits(GICState *s, int cpu) 293 { 294 /* Recalculate the current running priority for this CPU based 295 * on the set bits in the Active Priority Registers. 296 */ 297 int i; 298 for (i = 0; i < GIC_NR_APRS; i++) { 299 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; 300 if (!apr) { 301 continue; 302 } 303 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); 304 } 305 return 0x100; 306 } 307 308 static void gic_drop_prio(GICState *s, int cpu, int group) 309 { 310 /* Drop the priority of the currently active interrupt in the 311 * specified group. 312 * 313 * Note that we can guarantee (because of the requirement to nest 314 * GICC_IAR reads [which activate an interrupt and raise priority] 315 * with GICC_EOIR writes [which drop the priority for the interrupt]) 316 * that the interrupt we're being called for is the highest priority 317 * active interrupt, meaning that it has the lowest set bit in the 318 * APR registers. 319 * 320 * If the guest does not honour the ordering constraints then the 321 * behaviour of the GIC is UNPREDICTABLE, which for us means that 322 * the values of the APR registers might become incorrect and the 323 * running priority will be wrong, so interrupts that should preempt 324 * might not do so, and interrupts that should not preempt might do so. 325 */ 326 int i; 327 328 for (i = 0; i < GIC_NR_APRS; i++) { 329 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; 330 if (!*papr) { 331 continue; 332 } 333 /* Clear lowest set bit */ 334 *papr &= *papr - 1; 335 break; 336 } 337 338 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); 339 } 340 341 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 342 { 343 int ret, irq, src; 344 int cm = 1 << cpu; 345 346 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 347 * for the case where this GIC supports grouping and the pending interrupt 348 * is in the wrong group. 349 */ 350 irq = gic_get_current_pending_irq(s, cpu, attrs); 351 trace_gic_acknowledge_irq(cpu, irq); 352 353 if (irq >= GIC_MAXIRQ) { 354 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 355 return irq; 356 } 357 358 if (GIC_DIST_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 359 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 360 return 1023; 361 } 362 363 if (s->revision == REV_11MPCORE) { 364 /* Clear pending flags for both level and edge triggered interrupts. 365 * Level triggered IRQs will be reasserted once they become inactive. 366 */ 367 GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK 368 : cm); 369 ret = irq; 370 } else { 371 if (irq < GIC_NR_SGIS) { 372 /* Lookup the source CPU for the SGI and clear this in the 373 * sgi_pending map. Return the src and clear the overall pending 374 * state on this CPU if the SGI is not pending from any CPUs. 375 */ 376 assert(s->sgi_pending[irq][cpu] != 0); 377 src = ctz32(s->sgi_pending[irq][cpu]); 378 s->sgi_pending[irq][cpu] &= ~(1 << src); 379 if (s->sgi_pending[irq][cpu] == 0) { 380 GIC_DIST_CLEAR_PENDING(irq, 381 GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK 382 : cm); 383 } 384 ret = irq | ((src & 0x7) << 10); 385 } else { 386 /* Clear pending state for both level and edge triggered 387 * interrupts. (level triggered interrupts with an active line 388 * remain pending, see gic_test_pending) 389 */ 390 GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK 391 : cm); 392 ret = irq; 393 } 394 } 395 396 gic_activate_irq(s, cpu, irq); 397 gic_update(s); 398 DPRINTF("ACK %d\n", irq); 399 return ret; 400 } 401 402 void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, 403 MemTxAttrs attrs) 404 { 405 if (s->security_extn && !attrs.secure) { 406 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 407 return; /* Ignore Non-secure access of Group0 IRQ */ 408 } 409 val = 0x80 | (val >> 1); /* Non-secure view */ 410 } 411 412 if (irq < GIC_INTERNAL) { 413 s->priority1[irq][cpu] = val; 414 } else { 415 s->priority2[(irq) - GIC_INTERNAL] = val; 416 } 417 } 418 419 static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, 420 MemTxAttrs attrs) 421 { 422 uint32_t prio = GIC_DIST_GET_PRIORITY(irq, cpu); 423 424 if (s->security_extn && !attrs.secure) { 425 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { 426 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 427 } 428 prio = (prio << 1) & 0xff; /* Non-secure view */ 429 } 430 return prio; 431 } 432 433 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 434 MemTxAttrs attrs) 435 { 436 if (gic_cpu_ns_access(s, cpu, attrs)) { 437 if (s->priority_mask[cpu] & 0x80) { 438 /* Priority Mask in upper half */ 439 pmask = 0x80 | (pmask >> 1); 440 } else { 441 /* Non-secure write ignored if priority mask is in lower half */ 442 return; 443 } 444 } 445 s->priority_mask[cpu] = pmask; 446 } 447 448 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 449 { 450 uint32_t pmask = s->priority_mask[cpu]; 451 452 if (gic_cpu_ns_access(s, cpu, attrs)) { 453 if (pmask & 0x80) { 454 /* Priority Mask in upper half, return Non-secure view */ 455 pmask = (pmask << 1) & 0xff; 456 } else { 457 /* Priority Mask in lower half, RAZ */ 458 pmask = 0; 459 } 460 } 461 return pmask; 462 } 463 464 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 465 { 466 uint32_t ret = s->cpu_ctlr[cpu]; 467 468 if (gic_cpu_ns_access(s, cpu, attrs)) { 469 /* Construct the NS banked view of GICC_CTLR from the correct 470 * bits of the S banked view. We don't need to move the bypass 471 * control bits because we don't implement that (IMPDEF) part 472 * of the GIC architecture. 473 */ 474 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 475 } 476 return ret; 477 } 478 479 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 480 MemTxAttrs attrs) 481 { 482 uint32_t mask; 483 484 if (gic_cpu_ns_access(s, cpu, attrs)) { 485 /* The NS view can only write certain bits in the register; 486 * the rest are unchanged 487 */ 488 mask = GICC_CTLR_EN_GRP1; 489 if (s->revision == 2) { 490 mask |= GICC_CTLR_EOIMODE_NS; 491 } 492 s->cpu_ctlr[cpu] &= ~mask; 493 s->cpu_ctlr[cpu] |= (value << 1) & mask; 494 } else { 495 if (s->revision == 2) { 496 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 497 } else { 498 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 499 } 500 s->cpu_ctlr[cpu] = value & mask; 501 } 502 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 503 "Group1 Interrupts %sabled\n", cpu, 504 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 505 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 506 } 507 508 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 509 { 510 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { 511 /* Idle priority */ 512 return 0xff; 513 } 514 515 if (gic_cpu_ns_access(s, cpu, attrs)) { 516 if (s->running_priority[cpu] & 0x80) { 517 /* Running priority in upper half of range: return the Non-secure 518 * view of the priority. 519 */ 520 return s->running_priority[cpu] << 1; 521 } else { 522 /* Running priority in lower half of range: RAZ */ 523 return 0; 524 } 525 } else { 526 return s->running_priority[cpu]; 527 } 528 } 529 530 /* Return true if we should split priority drop and interrupt deactivation, 531 * ie whether the relevant EOIMode bit is set. 532 */ 533 static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) 534 { 535 if (s->revision != 2) { 536 /* Before GICv2 prio-drop and deactivate are not separable */ 537 return false; 538 } 539 if (gic_cpu_ns_access(s, cpu, attrs)) { 540 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; 541 } 542 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; 543 } 544 545 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 546 { 547 int cm = 1 << cpu; 548 int group; 549 550 if (irq >= s->num_irq) { 551 /* 552 * This handles two cases: 553 * 1. If software writes the ID of a spurious interrupt [ie 1023] 554 * to the GICC_DIR, the GIC ignores that write. 555 * 2. If software writes the number of a non-existent interrupt 556 * this must be a subcase of "value written is not an active interrupt" 557 * and so this is UNPREDICTABLE. We choose to ignore it. 558 */ 559 return; 560 } 561 562 group = gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm); 563 564 if (!gic_eoi_split(s, cpu, attrs)) { 565 /* This is UNPREDICTABLE; we choose to ignore it */ 566 qemu_log_mask(LOG_GUEST_ERROR, 567 "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); 568 return; 569 } 570 571 if (gic_cpu_ns_access(s, cpu, attrs) && !group) { 572 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); 573 return; 574 } 575 576 GIC_DIST_CLEAR_ACTIVE(irq, cm); 577 } 578 579 static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 580 { 581 int cm = 1 << cpu; 582 int group; 583 584 DPRINTF("EOI %d\n", irq); 585 if (irq >= s->num_irq) { 586 /* This handles two cases: 587 * 1. If software writes the ID of a spurious interrupt [ie 1023] 588 * to the GICC_EOIR, the GIC ignores that write. 589 * 2. If software writes the number of a non-existent interrupt 590 * this must be a subcase of "value written does not match the last 591 * valid interrupt value read from the Interrupt Acknowledge 592 * register" and so this is UNPREDICTABLE. We choose to ignore it. 593 */ 594 return; 595 } 596 if (s->running_priority[cpu] == 0x100) { 597 return; /* No active IRQ. */ 598 } 599 600 if (s->revision == REV_11MPCORE) { 601 /* Mark level triggered interrupts as pending if they are still 602 raised. */ 603 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq, cm) 604 && GIC_DIST_TEST_LEVEL(irq, cm) 605 && (GIC_DIST_TARGET(irq) & cm) != 0) { 606 DPRINTF("Set %d pending mask %x\n", irq, cm); 607 GIC_DIST_SET_PENDING(irq, cm); 608 } 609 } 610 611 group = gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm); 612 613 if (gic_cpu_ns_access(s, cpu, attrs) && !group) { 614 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 615 return; 616 } 617 618 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 619 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 620 * i.e. go ahead and complete the irq anyway. 621 */ 622 623 gic_drop_prio(s, cpu, group); 624 625 /* In GICv2 the guest can choose to split priority-drop and deactivate */ 626 if (!gic_eoi_split(s, cpu, attrs)) { 627 GIC_DIST_CLEAR_ACTIVE(irq, cm); 628 } 629 gic_update(s); 630 } 631 632 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 633 { 634 GICState *s = (GICState *)opaque; 635 uint32_t res; 636 int irq; 637 int i; 638 int cpu; 639 int cm; 640 int mask; 641 642 cpu = gic_get_current_cpu(s); 643 cm = 1 << cpu; 644 if (offset < 0x100) { 645 if (offset == 0) { /* GICD_CTLR */ 646 if (s->security_extn && !attrs.secure) { 647 /* The NS bank of this register is just an alias of the 648 * EnableGrp1 bit in the S bank version. 649 */ 650 return extract32(s->ctlr, 1, 1); 651 } else { 652 return s->ctlr; 653 } 654 } 655 if (offset == 4) 656 /* Interrupt Controller Type Register */ 657 return ((s->num_irq / 32) - 1) 658 | ((s->num_cpu - 1) << 5) 659 | (s->security_extn << 10); 660 if (offset < 0x08) 661 return 0; 662 if (offset >= 0x80) { 663 /* Interrupt Group Registers: these RAZ/WI if this is an NS 664 * access to a GIC with the security extensions, or if the GIC 665 * doesn't have groups at all. 666 */ 667 res = 0; 668 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 669 /* Every byte offset holds 8 group status bits */ 670 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 671 if (irq >= s->num_irq) { 672 goto bad_reg; 673 } 674 for (i = 0; i < 8; i++) { 675 if (GIC_DIST_TEST_GROUP(irq + i, cm)) { 676 res |= (1 << i); 677 } 678 } 679 } 680 return res; 681 } 682 goto bad_reg; 683 } else if (offset < 0x200) { 684 /* Interrupt Set/Clear Enable. */ 685 if (offset < 0x180) 686 irq = (offset - 0x100) * 8; 687 else 688 irq = (offset - 0x180) * 8; 689 irq += GIC_BASE_IRQ; 690 if (irq >= s->num_irq) 691 goto bad_reg; 692 res = 0; 693 for (i = 0; i < 8; i++) { 694 if (s->security_extn && !attrs.secure && 695 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 696 continue; /* Ignore Non-secure access of Group0 IRQ */ 697 } 698 699 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 700 res |= (1 << i); 701 } 702 } 703 } else if (offset < 0x300) { 704 /* Interrupt Set/Clear Pending. */ 705 if (offset < 0x280) 706 irq = (offset - 0x200) * 8; 707 else 708 irq = (offset - 0x280) * 8; 709 irq += GIC_BASE_IRQ; 710 if (irq >= s->num_irq) 711 goto bad_reg; 712 res = 0; 713 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 714 for (i = 0; i < 8; i++) { 715 if (s->security_extn && !attrs.secure && 716 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 717 continue; /* Ignore Non-secure access of Group0 IRQ */ 718 } 719 720 if (gic_test_pending(s, irq + i, mask)) { 721 res |= (1 << i); 722 } 723 } 724 } else if (offset < 0x400) { 725 /* Interrupt Set/Clear Active. */ 726 if (offset < 0x380) { 727 irq = (offset - 0x300) * 8; 728 } else if (s->revision == 2) { 729 irq = (offset - 0x380) * 8; 730 } else { 731 goto bad_reg; 732 } 733 734 irq += GIC_BASE_IRQ; 735 if (irq >= s->num_irq) 736 goto bad_reg; 737 res = 0; 738 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 739 for (i = 0; i < 8; i++) { 740 if (s->security_extn && !attrs.secure && 741 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 742 continue; /* Ignore Non-secure access of Group0 IRQ */ 743 } 744 745 if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) { 746 res |= (1 << i); 747 } 748 } 749 } else if (offset < 0x800) { 750 /* Interrupt Priority. */ 751 irq = (offset - 0x400) + GIC_BASE_IRQ; 752 if (irq >= s->num_irq) 753 goto bad_reg; 754 res = gic_dist_get_priority(s, cpu, irq, attrs); 755 } else if (offset < 0xc00) { 756 /* Interrupt CPU Target. */ 757 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 758 /* For uniprocessor GICs these RAZ/WI */ 759 res = 0; 760 } else { 761 irq = (offset - 0x800) + GIC_BASE_IRQ; 762 if (irq >= s->num_irq) { 763 goto bad_reg; 764 } 765 if (irq < 29 && s->revision == REV_11MPCORE) { 766 res = 0; 767 } else if (irq < GIC_INTERNAL) { 768 res = cm; 769 } else { 770 res = GIC_DIST_TARGET(irq); 771 } 772 } 773 } else if (offset < 0xf00) { 774 /* Interrupt Configuration. */ 775 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 776 if (irq >= s->num_irq) 777 goto bad_reg; 778 res = 0; 779 for (i = 0; i < 4; i++) { 780 if (s->security_extn && !attrs.secure && 781 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 782 continue; /* Ignore Non-secure access of Group0 IRQ */ 783 } 784 785 if (GIC_DIST_TEST_MODEL(irq + i)) { 786 res |= (1 << (i * 2)); 787 } 788 if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 789 res |= (2 << (i * 2)); 790 } 791 } 792 } else if (offset < 0xf10) { 793 goto bad_reg; 794 } else if (offset < 0xf30) { 795 if (s->revision == REV_11MPCORE) { 796 goto bad_reg; 797 } 798 799 if (offset < 0xf20) { 800 /* GICD_CPENDSGIRn */ 801 irq = (offset - 0xf10); 802 } else { 803 irq = (offset - 0xf20); 804 /* GICD_SPENDSGIRn */ 805 } 806 807 if (s->security_extn && !attrs.secure && 808 !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 809 res = 0; /* Ignore Non-secure access of Group0 IRQ */ 810 } else { 811 res = s->sgi_pending[irq][cpu]; 812 } 813 } else if (offset < 0xfd0) { 814 goto bad_reg; 815 } else if (offset < 0x1000) { 816 if (offset & 3) { 817 res = 0; 818 } else { 819 switch (s->revision) { 820 case REV_11MPCORE: 821 res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; 822 break; 823 case 1: 824 res = gic_id_gicv1[(offset - 0xfd0) >> 2]; 825 break; 826 case 2: 827 res = gic_id_gicv2[(offset - 0xfd0) >> 2]; 828 break; 829 default: 830 res = 0; 831 } 832 } 833 } else { 834 g_assert_not_reached(); 835 } 836 return res; 837 bad_reg: 838 qemu_log_mask(LOG_GUEST_ERROR, 839 "gic_dist_readb: Bad offset %x\n", (int)offset); 840 return 0; 841 } 842 843 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 844 unsigned size, MemTxAttrs attrs) 845 { 846 switch (size) { 847 case 1: 848 *data = gic_dist_readb(opaque, offset, attrs); 849 return MEMTX_OK; 850 case 2: 851 *data = gic_dist_readb(opaque, offset, attrs); 852 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 853 return MEMTX_OK; 854 case 4: 855 *data = gic_dist_readb(opaque, offset, attrs); 856 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 857 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 858 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 859 return MEMTX_OK; 860 default: 861 return MEMTX_ERROR; 862 } 863 } 864 865 static void gic_dist_writeb(void *opaque, hwaddr offset, 866 uint32_t value, MemTxAttrs attrs) 867 { 868 GICState *s = (GICState *)opaque; 869 int irq; 870 int i; 871 int cpu; 872 873 cpu = gic_get_current_cpu(s); 874 if (offset < 0x100) { 875 if (offset == 0) { 876 if (s->security_extn && !attrs.secure) { 877 /* NS version is just an alias of the S version's bit 1 */ 878 s->ctlr = deposit32(s->ctlr, 1, 1, value); 879 } else if (gic_has_groups(s)) { 880 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 881 } else { 882 s->ctlr = value & GICD_CTLR_EN_GRP0; 883 } 884 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 885 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 886 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 887 } else if (offset < 4) { 888 /* ignored. */ 889 } else if (offset >= 0x80) { 890 /* Interrupt Group Registers: RAZ/WI for NS access to secure 891 * GIC, or for GICs without groups. 892 */ 893 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 894 /* Every byte offset holds 8 group status bits */ 895 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 896 if (irq >= s->num_irq) { 897 goto bad_reg; 898 } 899 for (i = 0; i < 8; i++) { 900 /* Group bits are banked for private interrupts */ 901 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 902 if (value & (1 << i)) { 903 /* Group1 (Non-secure) */ 904 GIC_DIST_SET_GROUP(irq + i, cm); 905 } else { 906 /* Group0 (Secure) */ 907 GIC_DIST_CLEAR_GROUP(irq + i, cm); 908 } 909 } 910 } 911 } else { 912 goto bad_reg; 913 } 914 } else if (offset < 0x180) { 915 /* Interrupt Set Enable. */ 916 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 917 if (irq >= s->num_irq) 918 goto bad_reg; 919 if (irq < GIC_NR_SGIS) { 920 value = 0xff; 921 } 922 923 for (i = 0; i < 8; i++) { 924 if (value & (1 << i)) { 925 int mask = 926 (irq < GIC_INTERNAL) ? (1 << cpu) 927 : GIC_DIST_TARGET(irq + i); 928 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 929 930 if (s->security_extn && !attrs.secure && 931 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 932 continue; /* Ignore Non-secure access of Group0 IRQ */ 933 } 934 935 if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) { 936 DPRINTF("Enabled IRQ %d\n", irq + i); 937 trace_gic_enable_irq(irq + i); 938 } 939 GIC_DIST_SET_ENABLED(irq + i, cm); 940 /* If a raised level triggered IRQ enabled then mark 941 is as pending. */ 942 if (GIC_DIST_TEST_LEVEL(irq + i, mask) 943 && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { 944 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 945 GIC_DIST_SET_PENDING(irq + i, mask); 946 } 947 } 948 } 949 } else if (offset < 0x200) { 950 /* Interrupt Clear Enable. */ 951 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 952 if (irq >= s->num_irq) 953 goto bad_reg; 954 if (irq < GIC_NR_SGIS) { 955 value = 0; 956 } 957 958 for (i = 0; i < 8; i++) { 959 if (value & (1 << i)) { 960 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 961 962 if (s->security_extn && !attrs.secure && 963 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 964 continue; /* Ignore Non-secure access of Group0 IRQ */ 965 } 966 967 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { 968 DPRINTF("Disabled IRQ %d\n", irq + i); 969 trace_gic_disable_irq(irq + i); 970 } 971 GIC_DIST_CLEAR_ENABLED(irq + i, cm); 972 } 973 } 974 } else if (offset < 0x280) { 975 /* Interrupt Set Pending. */ 976 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 977 if (irq >= s->num_irq) 978 goto bad_reg; 979 if (irq < GIC_NR_SGIS) { 980 value = 0; 981 } 982 983 for (i = 0; i < 8; i++) { 984 if (value & (1 << i)) { 985 if (s->security_extn && !attrs.secure && 986 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 987 continue; /* Ignore Non-secure access of Group0 IRQ */ 988 } 989 990 GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i)); 991 } 992 } 993 } else if (offset < 0x300) { 994 /* Interrupt Clear Pending. */ 995 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 996 if (irq >= s->num_irq) 997 goto bad_reg; 998 if (irq < GIC_NR_SGIS) { 999 value = 0; 1000 } 1001 1002 for (i = 0; i < 8; i++) { 1003 if (s->security_extn && !attrs.secure && 1004 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1005 continue; /* Ignore Non-secure access of Group0 IRQ */ 1006 } 1007 1008 /* ??? This currently clears the pending bit for all CPUs, even 1009 for per-CPU interrupts. It's unclear whether this is the 1010 corect behavior. */ 1011 if (value & (1 << i)) { 1012 GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 1013 } 1014 } 1015 } else if (offset < 0x380) { 1016 /* Interrupt Set Active. */ 1017 if (s->revision != 2) { 1018 goto bad_reg; 1019 } 1020 1021 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 1022 if (irq >= s->num_irq) { 1023 goto bad_reg; 1024 } 1025 1026 /* This register is banked per-cpu for PPIs */ 1027 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; 1028 1029 for (i = 0; i < 8; i++) { 1030 if (s->security_extn && !attrs.secure && 1031 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1032 continue; /* Ignore Non-secure access of Group0 IRQ */ 1033 } 1034 1035 if (value & (1 << i)) { 1036 GIC_DIST_SET_ACTIVE(irq + i, cm); 1037 } 1038 } 1039 } else if (offset < 0x400) { 1040 /* Interrupt Clear Active. */ 1041 if (s->revision != 2) { 1042 goto bad_reg; 1043 } 1044 1045 irq = (offset - 0x380) * 8 + GIC_BASE_IRQ; 1046 if (irq >= s->num_irq) { 1047 goto bad_reg; 1048 } 1049 1050 /* This register is banked per-cpu for PPIs */ 1051 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; 1052 1053 for (i = 0; i < 8; i++) { 1054 if (s->security_extn && !attrs.secure && 1055 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1056 continue; /* Ignore Non-secure access of Group0 IRQ */ 1057 } 1058 1059 if (value & (1 << i)) { 1060 GIC_DIST_CLEAR_ACTIVE(irq + i, cm); 1061 } 1062 } 1063 } else if (offset < 0x800) { 1064 /* Interrupt Priority. */ 1065 irq = (offset - 0x400) + GIC_BASE_IRQ; 1066 if (irq >= s->num_irq) 1067 goto bad_reg; 1068 gic_dist_set_priority(s, cpu, irq, value, attrs); 1069 } else if (offset < 0xc00) { 1070 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 1071 * annoying exception of the 11MPCore's GIC. 1072 */ 1073 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 1074 irq = (offset - 0x800) + GIC_BASE_IRQ; 1075 if (irq >= s->num_irq) { 1076 goto bad_reg; 1077 } 1078 if (irq < 29 && s->revision == REV_11MPCORE) { 1079 value = 0; 1080 } else if (irq < GIC_INTERNAL) { 1081 value = ALL_CPU_MASK; 1082 } 1083 s->irq_target[irq] = value & ALL_CPU_MASK; 1084 } 1085 } else if (offset < 0xf00) { 1086 /* Interrupt Configuration. */ 1087 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 1088 if (irq >= s->num_irq) 1089 goto bad_reg; 1090 if (irq < GIC_NR_SGIS) 1091 value |= 0xaa; 1092 for (i = 0; i < 4; i++) { 1093 if (s->security_extn && !attrs.secure && 1094 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { 1095 continue; /* Ignore Non-secure access of Group0 IRQ */ 1096 } 1097 1098 if (s->revision == REV_11MPCORE) { 1099 if (value & (1 << (i * 2))) { 1100 GIC_DIST_SET_MODEL(irq + i); 1101 } else { 1102 GIC_DIST_CLEAR_MODEL(irq + i); 1103 } 1104 } 1105 if (value & (2 << (i * 2))) { 1106 GIC_DIST_SET_EDGE_TRIGGER(irq + i); 1107 } else { 1108 GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i); 1109 } 1110 } 1111 } else if (offset < 0xf10) { 1112 /* 0xf00 is only handled for 32-bit writes. */ 1113 goto bad_reg; 1114 } else if (offset < 0xf20) { 1115 /* GICD_CPENDSGIRn */ 1116 if (s->revision == REV_11MPCORE) { 1117 goto bad_reg; 1118 } 1119 irq = (offset - 0xf10); 1120 1121 if (!s->security_extn || attrs.secure || 1122 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1123 s->sgi_pending[irq][cpu] &= ~value; 1124 if (s->sgi_pending[irq][cpu] == 0) { 1125 GIC_DIST_CLEAR_PENDING(irq, 1 << cpu); 1126 } 1127 } 1128 } else if (offset < 0xf30) { 1129 /* GICD_SPENDSGIRn */ 1130 if (s->revision == REV_11MPCORE) { 1131 goto bad_reg; 1132 } 1133 irq = (offset - 0xf20); 1134 1135 if (!s->security_extn || attrs.secure || 1136 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { 1137 GIC_DIST_SET_PENDING(irq, 1 << cpu); 1138 s->sgi_pending[irq][cpu] |= value; 1139 } 1140 } else { 1141 goto bad_reg; 1142 } 1143 gic_update(s); 1144 return; 1145 bad_reg: 1146 qemu_log_mask(LOG_GUEST_ERROR, 1147 "gic_dist_writeb: Bad offset %x\n", (int)offset); 1148 } 1149 1150 static void gic_dist_writew(void *opaque, hwaddr offset, 1151 uint32_t value, MemTxAttrs attrs) 1152 { 1153 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 1154 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 1155 } 1156 1157 static void gic_dist_writel(void *opaque, hwaddr offset, 1158 uint32_t value, MemTxAttrs attrs) 1159 { 1160 GICState *s = (GICState *)opaque; 1161 if (offset == 0xf00) { 1162 int cpu; 1163 int irq; 1164 int mask; 1165 int target_cpu; 1166 1167 cpu = gic_get_current_cpu(s); 1168 irq = value & 0x3ff; 1169 switch ((value >> 24) & 3) { 1170 case 0: 1171 mask = (value >> 16) & ALL_CPU_MASK; 1172 break; 1173 case 1: 1174 mask = ALL_CPU_MASK ^ (1 << cpu); 1175 break; 1176 case 2: 1177 mask = 1 << cpu; 1178 break; 1179 default: 1180 DPRINTF("Bad Soft Int target filter\n"); 1181 mask = ALL_CPU_MASK; 1182 break; 1183 } 1184 GIC_DIST_SET_PENDING(irq, mask); 1185 target_cpu = ctz32(mask); 1186 while (target_cpu < GIC_NCPU) { 1187 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 1188 mask &= ~(1 << target_cpu); 1189 target_cpu = ctz32(mask); 1190 } 1191 gic_update(s); 1192 return; 1193 } 1194 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 1195 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 1196 } 1197 1198 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 1199 unsigned size, MemTxAttrs attrs) 1200 { 1201 switch (size) { 1202 case 1: 1203 gic_dist_writeb(opaque, offset, data, attrs); 1204 return MEMTX_OK; 1205 case 2: 1206 gic_dist_writew(opaque, offset, data, attrs); 1207 return MEMTX_OK; 1208 case 4: 1209 gic_dist_writel(opaque, offset, data, attrs); 1210 return MEMTX_OK; 1211 default: 1212 return MEMTX_ERROR; 1213 } 1214 } 1215 1216 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) 1217 { 1218 /* Return the Nonsecure view of GICC_APR<regno>. This is the 1219 * second half of GICC_NSAPR. 1220 */ 1221 switch (GIC_MIN_BPR) { 1222 case 0: 1223 if (regno < 2) { 1224 return s->nsapr[regno + 2][cpu]; 1225 } 1226 break; 1227 case 1: 1228 if (regno == 0) { 1229 return s->nsapr[regno + 1][cpu]; 1230 } 1231 break; 1232 case 2: 1233 if (regno == 0) { 1234 return extract32(s->nsapr[0][cpu], 16, 16); 1235 } 1236 break; 1237 case 3: 1238 if (regno == 0) { 1239 return extract32(s->nsapr[0][cpu], 8, 8); 1240 } 1241 break; 1242 default: 1243 g_assert_not_reached(); 1244 } 1245 return 0; 1246 } 1247 1248 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, 1249 uint32_t value) 1250 { 1251 /* Write the Nonsecure view of GICC_APR<regno>. */ 1252 switch (GIC_MIN_BPR) { 1253 case 0: 1254 if (regno < 2) { 1255 s->nsapr[regno + 2][cpu] = value; 1256 } 1257 break; 1258 case 1: 1259 if (regno == 0) { 1260 s->nsapr[regno + 1][cpu] = value; 1261 } 1262 break; 1263 case 2: 1264 if (regno == 0) { 1265 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); 1266 } 1267 break; 1268 case 3: 1269 if (regno == 0) { 1270 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); 1271 } 1272 break; 1273 default: 1274 g_assert_not_reached(); 1275 } 1276 } 1277 1278 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 1279 uint64_t *data, MemTxAttrs attrs) 1280 { 1281 switch (offset) { 1282 case 0x00: /* Control */ 1283 *data = gic_get_cpu_control(s, cpu, attrs); 1284 break; 1285 case 0x04: /* Priority mask */ 1286 *data = gic_get_priority_mask(s, cpu, attrs); 1287 break; 1288 case 0x08: /* Binary Point */ 1289 if (gic_cpu_ns_access(s, cpu, attrs)) { 1290 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1291 /* NS view of BPR when CBPR is 1 */ 1292 *data = MIN(s->bpr[cpu] + 1, 7); 1293 } else { 1294 /* BPR is banked. Non-secure copy stored in ABPR. */ 1295 *data = s->abpr[cpu]; 1296 } 1297 } else { 1298 *data = s->bpr[cpu]; 1299 } 1300 break; 1301 case 0x0c: /* Acknowledge */ 1302 *data = gic_acknowledge_irq(s, cpu, attrs); 1303 break; 1304 case 0x14: /* Running Priority */ 1305 *data = gic_get_running_priority(s, cpu, attrs); 1306 break; 1307 case 0x18: /* Highest Pending Interrupt */ 1308 *data = gic_get_current_pending_irq(s, cpu, attrs); 1309 break; 1310 case 0x1c: /* Aliased Binary Point */ 1311 /* GIC v2, no security: ABPR 1312 * GIC v1, no security: not implemented (RAZ/WI) 1313 * With security extensions, secure access: ABPR (alias of NS BPR) 1314 * With security extensions, nonsecure access: RAZ/WI 1315 */ 1316 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1317 *data = 0; 1318 } else { 1319 *data = s->abpr[cpu]; 1320 } 1321 break; 1322 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1323 { 1324 int regno = (offset - 0xd0) / 4; 1325 1326 if (regno >= GIC_NR_APRS || s->revision != 2) { 1327 *data = 0; 1328 } else if (gic_cpu_ns_access(s, cpu, attrs)) { 1329 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1330 *data = gic_apr_ns_view(s, regno, cpu); 1331 } else { 1332 *data = s->apr[regno][cpu]; 1333 } 1334 break; 1335 } 1336 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1337 { 1338 int regno = (offset - 0xe0) / 4; 1339 1340 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || 1341 gic_cpu_ns_access(s, cpu, attrs)) { 1342 *data = 0; 1343 } else { 1344 *data = s->nsapr[regno][cpu]; 1345 } 1346 break; 1347 } 1348 default: 1349 qemu_log_mask(LOG_GUEST_ERROR, 1350 "gic_cpu_read: Bad offset %x\n", (int)offset); 1351 *data = 0; 1352 break; 1353 } 1354 return MEMTX_OK; 1355 } 1356 1357 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 1358 uint32_t value, MemTxAttrs attrs) 1359 { 1360 switch (offset) { 1361 case 0x00: /* Control */ 1362 gic_set_cpu_control(s, cpu, value, attrs); 1363 break; 1364 case 0x04: /* Priority mask */ 1365 gic_set_priority_mask(s, cpu, value, attrs); 1366 break; 1367 case 0x08: /* Binary Point */ 1368 if (gic_cpu_ns_access(s, cpu, attrs)) { 1369 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { 1370 /* WI when CBPR is 1 */ 1371 return MEMTX_OK; 1372 } else { 1373 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1374 } 1375 } else { 1376 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 1377 } 1378 break; 1379 case 0x10: /* End Of Interrupt */ 1380 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1381 return MEMTX_OK; 1382 case 0x1c: /* Aliased Binary Point */ 1383 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1384 /* unimplemented, or NS access: RAZ/WI */ 1385 return MEMTX_OK; 1386 } else { 1387 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1388 } 1389 break; 1390 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1391 { 1392 int regno = (offset - 0xd0) / 4; 1393 1394 if (regno >= GIC_NR_APRS || s->revision != 2) { 1395 return MEMTX_OK; 1396 } 1397 if (gic_cpu_ns_access(s, cpu, attrs)) { 1398 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ 1399 gic_apr_write_ns_view(s, regno, cpu, value); 1400 } else { 1401 s->apr[regno][cpu] = value; 1402 } 1403 break; 1404 } 1405 case 0xe0: case 0xe4: case 0xe8: case 0xec: 1406 { 1407 int regno = (offset - 0xe0) / 4; 1408 1409 if (regno >= GIC_NR_APRS || s->revision != 2) { 1410 return MEMTX_OK; 1411 } 1412 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { 1413 return MEMTX_OK; 1414 } 1415 s->nsapr[regno][cpu] = value; 1416 break; 1417 } 1418 case 0x1000: 1419 /* GICC_DIR */ 1420 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); 1421 break; 1422 default: 1423 qemu_log_mask(LOG_GUEST_ERROR, 1424 "gic_cpu_write: Bad offset %x\n", (int)offset); 1425 return MEMTX_OK; 1426 } 1427 gic_update(s); 1428 return MEMTX_OK; 1429 } 1430 1431 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1432 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1433 unsigned size, MemTxAttrs attrs) 1434 { 1435 GICState *s = (GICState *)opaque; 1436 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1437 } 1438 1439 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1440 uint64_t value, unsigned size, 1441 MemTxAttrs attrs) 1442 { 1443 GICState *s = (GICState *)opaque; 1444 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1445 } 1446 1447 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1448 * These just decode the opaque pointer into GICState* + cpu id. 1449 */ 1450 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1451 unsigned size, MemTxAttrs attrs) 1452 { 1453 GICState **backref = (GICState **)opaque; 1454 GICState *s = *backref; 1455 int id = (backref - s->backref); 1456 return gic_cpu_read(s, id, addr, data, attrs); 1457 } 1458 1459 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1460 uint64_t value, unsigned size, 1461 MemTxAttrs attrs) 1462 { 1463 GICState **backref = (GICState **)opaque; 1464 GICState *s = *backref; 1465 int id = (backref - s->backref); 1466 return gic_cpu_write(s, id, addr, value, attrs); 1467 } 1468 1469 static const MemoryRegionOps gic_ops[2] = { 1470 { 1471 .read_with_attrs = gic_dist_read, 1472 .write_with_attrs = gic_dist_write, 1473 .endianness = DEVICE_NATIVE_ENDIAN, 1474 }, 1475 { 1476 .read_with_attrs = gic_thiscpu_read, 1477 .write_with_attrs = gic_thiscpu_write, 1478 .endianness = DEVICE_NATIVE_ENDIAN, 1479 } 1480 }; 1481 1482 static const MemoryRegionOps gic_cpu_ops = { 1483 .read_with_attrs = gic_do_cpu_read, 1484 .write_with_attrs = gic_do_cpu_write, 1485 .endianness = DEVICE_NATIVE_ENDIAN, 1486 }; 1487 1488 static void arm_gic_realize(DeviceState *dev, Error **errp) 1489 { 1490 /* Device instance realize function for the GIC sysbus device */ 1491 int i; 1492 GICState *s = ARM_GIC(dev); 1493 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1494 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1495 Error *local_err = NULL; 1496 1497 agc->parent_realize(dev, &local_err); 1498 if (local_err) { 1499 error_propagate(errp, local_err); 1500 return; 1501 } 1502 1503 if (kvm_enabled() && !kvm_arm_supports_user_irq()) { 1504 error_setg(errp, "KVM with user space irqchip only works when the " 1505 "host kernel supports KVM_CAP_ARM_USER_IRQ"); 1506 return; 1507 } 1508 1509 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ 1510 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL); 1511 1512 /* Extra core-specific regions for the CPU interfaces. This is 1513 * necessary for "franken-GIC" implementations, for example on 1514 * Exynos 4. 1515 * NB that the memory region size of 0x100 applies for the 11MPCore 1516 * and also cores following the GIC v1 spec (ie A9). 1517 * GIC v2 defines a larger memory region (0x1000) so this will need 1518 * to be extended when we implement A15. 1519 */ 1520 for (i = 0; i < s->num_cpu; i++) { 1521 s->backref[i] = s; 1522 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1523 &s->backref[i], "gic_cpu", 0x100); 1524 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); 1525 } 1526 } 1527 1528 static void arm_gic_class_init(ObjectClass *klass, void *data) 1529 { 1530 DeviceClass *dc = DEVICE_CLASS(klass); 1531 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1532 1533 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); 1534 } 1535 1536 static const TypeInfo arm_gic_info = { 1537 .name = TYPE_ARM_GIC, 1538 .parent = TYPE_ARM_GIC_COMMON, 1539 .instance_size = sizeof(GICState), 1540 .class_init = arm_gic_class_init, 1541 .class_size = sizeof(ARMGICClass), 1542 }; 1543 1544 static void arm_gic_register_types(void) 1545 { 1546 type_register_static(&arm_gic_info); 1547 } 1548 1549 type_init(arm_gic_register_types) 1550