1 /* 2 * ARM Generic/Distributed Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 /* This file contains implementation code for the RealView EB interrupt 11 * controller, MPCore distributed interrupt controller and ARMv7-M 12 * Nested Vectored Interrupt Controller. 13 * It is compiled in two ways: 14 * (1) as a standalone file to produce a sysbus device which is a GIC 15 * that can be used on the realview board and as one of the builtin 16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) 17 * (2) by being directly #included into armv7m_nvic.c to produce the 18 * armv7m_nvic device. 19 */ 20 21 #include "hw/sysbus.h" 22 #include "gic_internal.h" 23 #include "qom/cpu.h" 24 25 //#define DEBUG_GIC 26 27 #ifdef DEBUG_GIC 28 #define DPRINTF(fmt, ...) \ 29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) 30 #else 31 #define DPRINTF(fmt, ...) do {} while(0) 32 #endif 33 34 static const uint8_t gic_id[] = { 35 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 36 }; 37 38 #define NUM_CPU(s) ((s)->num_cpu) 39 40 static inline int gic_get_current_cpu(GICState *s) 41 { 42 if (s->num_cpu > 1) { 43 return current_cpu->cpu_index; 44 } 45 return 0; 46 } 47 48 /* Return true if this GIC config has interrupt groups, which is 49 * true if we're a GICv2, or a GICv1 with the security extensions. 50 */ 51 static inline bool gic_has_groups(GICState *s) 52 { 53 return s->revision == 2 || s->security_extn; 54 } 55 56 /* TODO: Many places that call this routine could be optimized. */ 57 /* Update interrupt status after enabled or pending bits have been changed. */ 58 void gic_update(GICState *s) 59 { 60 int best_irq; 61 int best_prio; 62 int irq; 63 int irq_level, fiq_level; 64 int cpu; 65 int cm; 66 67 for (cpu = 0; cpu < NUM_CPU(s); cpu++) { 68 cm = 1 << cpu; 69 s->current_pending[cpu] = 1023; 70 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) 71 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { 72 qemu_irq_lower(s->parent_irq[cpu]); 73 qemu_irq_lower(s->parent_fiq[cpu]); 74 return; 75 } 76 best_prio = 0x100; 77 best_irq = 1023; 78 for (irq = 0; irq < s->num_irq; irq++) { 79 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && 80 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { 81 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { 82 best_prio = GIC_GET_PRIORITY(irq, cpu); 83 best_irq = irq; 84 } 85 } 86 } 87 88 irq_level = fiq_level = 0; 89 90 if (best_prio < s->priority_mask[cpu]) { 91 s->current_pending[cpu] = best_irq; 92 if (best_prio < s->running_priority[cpu]) { 93 int group = GIC_TEST_GROUP(best_irq, cm); 94 95 if (extract32(s->ctlr, group, 1) && 96 extract32(s->cpu_ctlr[cpu], group, 1)) { 97 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { 98 DPRINTF("Raised pending FIQ %d (cpu %d)\n", 99 best_irq, cpu); 100 fiq_level = 1; 101 } else { 102 DPRINTF("Raised pending IRQ %d (cpu %d)\n", 103 best_irq, cpu); 104 irq_level = 1; 105 } 106 } 107 } 108 } 109 110 qemu_set_irq(s->parent_irq[cpu], irq_level); 111 qemu_set_irq(s->parent_fiq[cpu], fiq_level); 112 } 113 } 114 115 void gic_set_pending_private(GICState *s, int cpu, int irq) 116 { 117 int cm = 1 << cpu; 118 119 if (gic_test_pending(s, irq, cm)) { 120 return; 121 } 122 123 DPRINTF("Set %d pending cpu %d\n", irq, cpu); 124 GIC_SET_PENDING(irq, cm); 125 gic_update(s); 126 } 127 128 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 129 int cm, int target) 130 { 131 if (level) { 132 GIC_SET_LEVEL(irq, cm); 133 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { 134 DPRINTF("Set %d pending mask %x\n", irq, target); 135 GIC_SET_PENDING(irq, target); 136 } 137 } else { 138 GIC_CLEAR_LEVEL(irq, cm); 139 } 140 } 141 142 static void gic_set_irq_generic(GICState *s, int irq, int level, 143 int cm, int target) 144 { 145 if (level) { 146 GIC_SET_LEVEL(irq, cm); 147 DPRINTF("Set %d pending mask %x\n", irq, target); 148 if (GIC_TEST_EDGE_TRIGGER(irq)) { 149 GIC_SET_PENDING(irq, target); 150 } 151 } else { 152 GIC_CLEAR_LEVEL(irq, cm); 153 } 154 } 155 156 /* Process a change in an external IRQ input. */ 157 static void gic_set_irq(void *opaque, int irq, int level) 158 { 159 /* Meaning of the 'irq' parameter: 160 * [0..N-1] : external interrupts 161 * [N..N+31] : PPI (internal) interrupts for CPU 0 162 * [N+32..N+63] : PPI (internal interrupts for CPU 1 163 * ... 164 */ 165 GICState *s = (GICState *)opaque; 166 int cm, target; 167 if (irq < (s->num_irq - GIC_INTERNAL)) { 168 /* The first external input line is internal interrupt 32. */ 169 cm = ALL_CPU_MASK; 170 irq += GIC_INTERNAL; 171 target = GIC_TARGET(irq); 172 } else { 173 int cpu; 174 irq -= (s->num_irq - GIC_INTERNAL); 175 cpu = irq / GIC_INTERNAL; 176 irq %= GIC_INTERNAL; 177 cm = 1 << cpu; 178 target = cm; 179 } 180 181 assert(irq >= GIC_NR_SGIS); 182 183 if (level == GIC_TEST_LEVEL(irq, cm)) { 184 return; 185 } 186 187 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 188 gic_set_irq_11mpcore(s, irq, level, cm, target); 189 } else { 190 gic_set_irq_generic(s, irq, level, cm, target); 191 } 192 193 gic_update(s); 194 } 195 196 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, 197 MemTxAttrs attrs) 198 { 199 uint16_t pending_irq = s->current_pending[cpu]; 200 201 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { 202 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); 203 /* On a GIC without the security extensions, reading this register 204 * behaves in the same way as a secure access to a GIC with them. 205 */ 206 bool secure = !s->security_extn || attrs.secure; 207 208 if (group == 0 && !secure) { 209 /* Group0 interrupts hidden from Non-secure access */ 210 return 1023; 211 } 212 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { 213 /* Group1 interrupts only seen by Secure access if 214 * AckCtl bit set. 215 */ 216 return 1022; 217 } 218 } 219 return pending_irq; 220 } 221 222 static void gic_set_running_irq(GICState *s, int cpu, int irq) 223 { 224 s->running_irq[cpu] = irq; 225 if (irq == 1023) { 226 s->running_priority[cpu] = 0x100; 227 } else { 228 s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); 229 } 230 gic_update(s); 231 } 232 233 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 234 { 235 int ret, irq, src; 236 int cm = 1 << cpu; 237 238 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately 239 * for the case where this GIC supports grouping and the pending interrupt 240 * is in the wrong group. 241 */ 242 irq = gic_get_current_pending_irq(s, cpu, attrs);; 243 244 if (irq >= GIC_MAXIRQ) { 245 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); 246 return irq; 247 } 248 249 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { 250 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); 251 return 1023; 252 } 253 s->last_active[irq][cpu] = s->running_irq[cpu]; 254 255 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 256 /* Clear pending flags for both level and edge triggered interrupts. 257 * Level triggered IRQs will be reasserted once they become inactive. 258 */ 259 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 260 ret = irq; 261 } else { 262 if (irq < GIC_NR_SGIS) { 263 /* Lookup the source CPU for the SGI and clear this in the 264 * sgi_pending map. Return the src and clear the overall pending 265 * state on this CPU if the SGI is not pending from any CPUs. 266 */ 267 assert(s->sgi_pending[irq][cpu] != 0); 268 src = ctz32(s->sgi_pending[irq][cpu]); 269 s->sgi_pending[irq][cpu] &= ~(1 << src); 270 if (s->sgi_pending[irq][cpu] == 0) { 271 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 272 } 273 ret = irq | ((src & 0x7) << 10); 274 } else { 275 /* Clear pending state for both level and edge triggered 276 * interrupts. (level triggered interrupts with an active line 277 * remain pending, see gic_test_pending) 278 */ 279 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); 280 ret = irq; 281 } 282 } 283 284 gic_set_running_irq(s, cpu, irq); 285 DPRINTF("ACK %d\n", irq); 286 return ret; 287 } 288 289 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, 290 MemTxAttrs attrs) 291 { 292 if (s->security_extn && !attrs.secure) { 293 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 294 return; /* Ignore Non-secure access of Group0 IRQ */ 295 } 296 val = 0x80 | (val >> 1); /* Non-secure view */ 297 } 298 299 if (irq < GIC_INTERNAL) { 300 s->priority1[irq][cpu] = val; 301 } else { 302 s->priority2[(irq) - GIC_INTERNAL] = val; 303 } 304 } 305 306 static uint32_t gic_get_priority(GICState *s, int cpu, int irq, 307 MemTxAttrs attrs) 308 { 309 uint32_t prio = GIC_GET_PRIORITY(irq, cpu); 310 311 if (s->security_extn && !attrs.secure) { 312 if (!GIC_TEST_GROUP(irq, (1 << cpu))) { 313 return 0; /* Non-secure access cannot read priority of Group0 IRQ */ 314 } 315 prio = (prio << 1) & 0xff; /* Non-secure view */ 316 } 317 return prio; 318 } 319 320 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, 321 MemTxAttrs attrs) 322 { 323 if (s->security_extn && !attrs.secure) { 324 if (s->priority_mask[cpu] & 0x80) { 325 /* Priority Mask in upper half */ 326 pmask = 0x80 | (pmask >> 1); 327 } else { 328 /* Non-secure write ignored if priority mask is in lower half */ 329 return; 330 } 331 } 332 s->priority_mask[cpu] = pmask; 333 } 334 335 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) 336 { 337 uint32_t pmask = s->priority_mask[cpu]; 338 339 if (s->security_extn && !attrs.secure) { 340 if (pmask & 0x80) { 341 /* Priority Mask in upper half, return Non-secure view */ 342 pmask = (pmask << 1) & 0xff; 343 } else { 344 /* Priority Mask in lower half, RAZ */ 345 pmask = 0; 346 } 347 } 348 return pmask; 349 } 350 351 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) 352 { 353 uint32_t ret = s->cpu_ctlr[cpu]; 354 355 if (s->security_extn && !attrs.secure) { 356 /* Construct the NS banked view of GICC_CTLR from the correct 357 * bits of the S banked view. We don't need to move the bypass 358 * control bits because we don't implement that (IMPDEF) part 359 * of the GIC architecture. 360 */ 361 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; 362 } 363 return ret; 364 } 365 366 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, 367 MemTxAttrs attrs) 368 { 369 uint32_t mask; 370 371 if (s->security_extn && !attrs.secure) { 372 /* The NS view can only write certain bits in the register; 373 * the rest are unchanged 374 */ 375 mask = GICC_CTLR_EN_GRP1; 376 if (s->revision == 2) { 377 mask |= GICC_CTLR_EOIMODE_NS; 378 } 379 s->cpu_ctlr[cpu] &= ~mask; 380 s->cpu_ctlr[cpu] |= (value << 1) & mask; 381 } else { 382 if (s->revision == 2) { 383 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; 384 } else { 385 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; 386 } 387 s->cpu_ctlr[cpu] = value & mask; 388 } 389 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " 390 "Group1 Interrupts %sabled\n", cpu, 391 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", 392 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); 393 } 394 395 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) 396 { 397 if (s->security_extn && !attrs.secure) { 398 if (s->running_priority[cpu] & 0x80) { 399 /* Running priority in upper half of range: return the Non-secure 400 * view of the priority. 401 */ 402 return s->running_priority[cpu] << 1; 403 } else { 404 /* Running priority in lower half of range: RAZ */ 405 return 0; 406 } 407 } else { 408 return s->running_priority[cpu]; 409 } 410 } 411 412 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 413 { 414 int update = 0; 415 int cm = 1 << cpu; 416 DPRINTF("EOI %d\n", irq); 417 if (irq >= s->num_irq) { 418 /* This handles two cases: 419 * 1. If software writes the ID of a spurious interrupt [ie 1023] 420 * to the GICC_EOIR, the GIC ignores that write. 421 * 2. If software writes the number of a non-existent interrupt 422 * this must be a subcase of "value written does not match the last 423 * valid interrupt value read from the Interrupt Acknowledge 424 * register" and so this is UNPREDICTABLE. We choose to ignore it. 425 */ 426 return; 427 } 428 if (s->running_irq[cpu] == 1023) 429 return; /* No active IRQ. */ 430 431 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 432 /* Mark level triggered interrupts as pending if they are still 433 raised. */ 434 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) 435 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { 436 DPRINTF("Set %d pending mask %x\n", irq, cm); 437 GIC_SET_PENDING(irq, cm); 438 update = 1; 439 } 440 } 441 442 if (s->security_extn && !attrs.secure && !GIC_TEST_GROUP(irq, cm)) { 443 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); 444 return; 445 } 446 447 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 448 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, 449 * i.e. go ahead and complete the irq anyway. 450 */ 451 452 if (irq != s->running_irq[cpu]) { 453 /* Complete an IRQ that is not currently running. */ 454 int tmp = s->running_irq[cpu]; 455 while (s->last_active[tmp][cpu] != 1023) { 456 if (s->last_active[tmp][cpu] == irq) { 457 s->last_active[tmp][cpu] = s->last_active[irq][cpu]; 458 break; 459 } 460 tmp = s->last_active[tmp][cpu]; 461 } 462 if (update) { 463 gic_update(s); 464 } 465 } else { 466 /* Complete the current running IRQ. */ 467 gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); 468 } 469 } 470 471 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 472 { 473 GICState *s = (GICState *)opaque; 474 uint32_t res; 475 int irq; 476 int i; 477 int cpu; 478 int cm; 479 int mask; 480 481 cpu = gic_get_current_cpu(s); 482 cm = 1 << cpu; 483 if (offset < 0x100) { 484 if (offset == 0) { /* GICD_CTLR */ 485 if (s->security_extn && !attrs.secure) { 486 /* The NS bank of this register is just an alias of the 487 * EnableGrp1 bit in the S bank version. 488 */ 489 return extract32(s->ctlr, 1, 1); 490 } else { 491 return s->ctlr; 492 } 493 } 494 if (offset == 4) 495 /* Interrupt Controller Type Register */ 496 return ((s->num_irq / 32) - 1) 497 | ((NUM_CPU(s) - 1) << 5) 498 | (s->security_extn << 10); 499 if (offset < 0x08) 500 return 0; 501 if (offset >= 0x80) { 502 /* Interrupt Group Registers: these RAZ/WI if this is an NS 503 * access to a GIC with the security extensions, or if the GIC 504 * doesn't have groups at all. 505 */ 506 res = 0; 507 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 508 /* Every byte offset holds 8 group status bits */ 509 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; 510 if (irq >= s->num_irq) { 511 goto bad_reg; 512 } 513 for (i = 0; i < 8; i++) { 514 if (GIC_TEST_GROUP(irq + i, cm)) { 515 res |= (1 << i); 516 } 517 } 518 } 519 return res; 520 } 521 goto bad_reg; 522 } else if (offset < 0x200) { 523 /* Interrupt Set/Clear Enable. */ 524 if (offset < 0x180) 525 irq = (offset - 0x100) * 8; 526 else 527 irq = (offset - 0x180) * 8; 528 irq += GIC_BASE_IRQ; 529 if (irq >= s->num_irq) 530 goto bad_reg; 531 res = 0; 532 for (i = 0; i < 8; i++) { 533 if (GIC_TEST_ENABLED(irq + i, cm)) { 534 res |= (1 << i); 535 } 536 } 537 } else if (offset < 0x300) { 538 /* Interrupt Set/Clear Pending. */ 539 if (offset < 0x280) 540 irq = (offset - 0x200) * 8; 541 else 542 irq = (offset - 0x280) * 8; 543 irq += GIC_BASE_IRQ; 544 if (irq >= s->num_irq) 545 goto bad_reg; 546 res = 0; 547 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 548 for (i = 0; i < 8; i++) { 549 if (gic_test_pending(s, irq + i, mask)) { 550 res |= (1 << i); 551 } 552 } 553 } else if (offset < 0x400) { 554 /* Interrupt Active. */ 555 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; 556 if (irq >= s->num_irq) 557 goto bad_reg; 558 res = 0; 559 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; 560 for (i = 0; i < 8; i++) { 561 if (GIC_TEST_ACTIVE(irq + i, mask)) { 562 res |= (1 << i); 563 } 564 } 565 } else if (offset < 0x800) { 566 /* Interrupt Priority. */ 567 irq = (offset - 0x400) + GIC_BASE_IRQ; 568 if (irq >= s->num_irq) 569 goto bad_reg; 570 res = gic_get_priority(s, cpu, irq, attrs); 571 } else if (offset < 0xc00) { 572 /* Interrupt CPU Target. */ 573 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { 574 /* For uniprocessor GICs these RAZ/WI */ 575 res = 0; 576 } else { 577 irq = (offset - 0x800) + GIC_BASE_IRQ; 578 if (irq >= s->num_irq) { 579 goto bad_reg; 580 } 581 if (irq >= 29 && irq <= 31) { 582 res = cm; 583 } else { 584 res = GIC_TARGET(irq); 585 } 586 } 587 } else if (offset < 0xf00) { 588 /* Interrupt Configuration. */ 589 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 590 if (irq >= s->num_irq) 591 goto bad_reg; 592 res = 0; 593 for (i = 0; i < 4; i++) { 594 if (GIC_TEST_MODEL(irq + i)) 595 res |= (1 << (i * 2)); 596 if (GIC_TEST_EDGE_TRIGGER(irq + i)) 597 res |= (2 << (i * 2)); 598 } 599 } else if (offset < 0xf10) { 600 goto bad_reg; 601 } else if (offset < 0xf30) { 602 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 603 goto bad_reg; 604 } 605 606 if (offset < 0xf20) { 607 /* GICD_CPENDSGIRn */ 608 irq = (offset - 0xf10); 609 } else { 610 irq = (offset - 0xf20); 611 /* GICD_SPENDSGIRn */ 612 } 613 614 res = s->sgi_pending[irq][cpu]; 615 } else if (offset < 0xfe0) { 616 goto bad_reg; 617 } else /* offset >= 0xfe0 */ { 618 if (offset & 3) { 619 res = 0; 620 } else { 621 res = gic_id[(offset - 0xfe0) >> 2]; 622 } 623 } 624 return res; 625 bad_reg: 626 qemu_log_mask(LOG_GUEST_ERROR, 627 "gic_dist_readb: Bad offset %x\n", (int)offset); 628 return 0; 629 } 630 631 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, 632 unsigned size, MemTxAttrs attrs) 633 { 634 switch (size) { 635 case 1: 636 *data = gic_dist_readb(opaque, offset, attrs); 637 return MEMTX_OK; 638 case 2: 639 *data = gic_dist_readb(opaque, offset, attrs); 640 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 641 return MEMTX_OK; 642 case 4: 643 *data = gic_dist_readb(opaque, offset, attrs); 644 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; 645 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; 646 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; 647 return MEMTX_OK; 648 default: 649 return MEMTX_ERROR; 650 } 651 } 652 653 static void gic_dist_writeb(void *opaque, hwaddr offset, 654 uint32_t value, MemTxAttrs attrs) 655 { 656 GICState *s = (GICState *)opaque; 657 int irq; 658 int i; 659 int cpu; 660 661 cpu = gic_get_current_cpu(s); 662 if (offset < 0x100) { 663 if (offset == 0) { 664 if (s->security_extn && !attrs.secure) { 665 /* NS version is just an alias of the S version's bit 1 */ 666 s->ctlr = deposit32(s->ctlr, 1, 1, value); 667 } else if (gic_has_groups(s)) { 668 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); 669 } else { 670 s->ctlr = value & GICD_CTLR_EN_GRP0; 671 } 672 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", 673 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", 674 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); 675 } else if (offset < 4) { 676 /* ignored. */ 677 } else if (offset >= 0x80) { 678 /* Interrupt Group Registers: RAZ/WI for NS access to secure 679 * GIC, or for GICs without groups. 680 */ 681 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { 682 /* Every byte offset holds 8 group status bits */ 683 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; 684 if (irq >= s->num_irq) { 685 goto bad_reg; 686 } 687 for (i = 0; i < 8; i++) { 688 /* Group bits are banked for private interrupts */ 689 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 690 if (value & (1 << i)) { 691 /* Group1 (Non-secure) */ 692 GIC_SET_GROUP(irq + i, cm); 693 } else { 694 /* Group0 (Secure) */ 695 GIC_CLEAR_GROUP(irq + i, cm); 696 } 697 } 698 } 699 } else { 700 goto bad_reg; 701 } 702 } else if (offset < 0x180) { 703 /* Interrupt Set Enable. */ 704 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; 705 if (irq >= s->num_irq) 706 goto bad_reg; 707 if (irq < GIC_NR_SGIS) { 708 value = 0xff; 709 } 710 711 for (i = 0; i < 8; i++) { 712 if (value & (1 << i)) { 713 int mask = 714 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); 715 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 716 717 if (!GIC_TEST_ENABLED(irq + i, cm)) { 718 DPRINTF("Enabled IRQ %d\n", irq + i); 719 } 720 GIC_SET_ENABLED(irq + i, cm); 721 /* If a raised level triggered IRQ enabled then mark 722 is as pending. */ 723 if (GIC_TEST_LEVEL(irq + i, mask) 724 && !GIC_TEST_EDGE_TRIGGER(irq + i)) { 725 DPRINTF("Set %d pending mask %x\n", irq + i, mask); 726 GIC_SET_PENDING(irq + i, mask); 727 } 728 } 729 } 730 } else if (offset < 0x200) { 731 /* Interrupt Clear Enable. */ 732 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; 733 if (irq >= s->num_irq) 734 goto bad_reg; 735 if (irq < GIC_NR_SGIS) { 736 value = 0; 737 } 738 739 for (i = 0; i < 8; i++) { 740 if (value & (1 << i)) { 741 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; 742 743 if (GIC_TEST_ENABLED(irq + i, cm)) { 744 DPRINTF("Disabled IRQ %d\n", irq + i); 745 } 746 GIC_CLEAR_ENABLED(irq + i, cm); 747 } 748 } 749 } else if (offset < 0x280) { 750 /* Interrupt Set Pending. */ 751 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; 752 if (irq >= s->num_irq) 753 goto bad_reg; 754 if (irq < GIC_NR_SGIS) { 755 value = 0; 756 } 757 758 for (i = 0; i < 8; i++) { 759 if (value & (1 << i)) { 760 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); 761 } 762 } 763 } else if (offset < 0x300) { 764 /* Interrupt Clear Pending. */ 765 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; 766 if (irq >= s->num_irq) 767 goto bad_reg; 768 if (irq < GIC_NR_SGIS) { 769 value = 0; 770 } 771 772 for (i = 0; i < 8; i++) { 773 /* ??? This currently clears the pending bit for all CPUs, even 774 for per-CPU interrupts. It's unclear whether this is the 775 corect behavior. */ 776 if (value & (1 << i)) { 777 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); 778 } 779 } 780 } else if (offset < 0x400) { 781 /* Interrupt Active. */ 782 goto bad_reg; 783 } else if (offset < 0x800) { 784 /* Interrupt Priority. */ 785 irq = (offset - 0x400) + GIC_BASE_IRQ; 786 if (irq >= s->num_irq) 787 goto bad_reg; 788 gic_set_priority(s, cpu, irq, value, attrs); 789 } else if (offset < 0xc00) { 790 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the 791 * annoying exception of the 11MPCore's GIC. 792 */ 793 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { 794 irq = (offset - 0x800) + GIC_BASE_IRQ; 795 if (irq >= s->num_irq) { 796 goto bad_reg; 797 } 798 if (irq < 29) { 799 value = 0; 800 } else if (irq < GIC_INTERNAL) { 801 value = ALL_CPU_MASK; 802 } 803 s->irq_target[irq] = value & ALL_CPU_MASK; 804 } 805 } else if (offset < 0xf00) { 806 /* Interrupt Configuration. */ 807 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; 808 if (irq >= s->num_irq) 809 goto bad_reg; 810 if (irq < GIC_NR_SGIS) 811 value |= 0xaa; 812 for (i = 0; i < 4; i++) { 813 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 814 if (value & (1 << (i * 2))) { 815 GIC_SET_MODEL(irq + i); 816 } else { 817 GIC_CLEAR_MODEL(irq + i); 818 } 819 } 820 if (value & (2 << (i * 2))) { 821 GIC_SET_EDGE_TRIGGER(irq + i); 822 } else { 823 GIC_CLEAR_EDGE_TRIGGER(irq + i); 824 } 825 } 826 } else if (offset < 0xf10) { 827 /* 0xf00 is only handled for 32-bit writes. */ 828 goto bad_reg; 829 } else if (offset < 0xf20) { 830 /* GICD_CPENDSGIRn */ 831 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 832 goto bad_reg; 833 } 834 irq = (offset - 0xf10); 835 836 s->sgi_pending[irq][cpu] &= ~value; 837 if (s->sgi_pending[irq][cpu] == 0) { 838 GIC_CLEAR_PENDING(irq, 1 << cpu); 839 } 840 } else if (offset < 0xf30) { 841 /* GICD_SPENDSGIRn */ 842 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { 843 goto bad_reg; 844 } 845 irq = (offset - 0xf20); 846 847 GIC_SET_PENDING(irq, 1 << cpu); 848 s->sgi_pending[irq][cpu] |= value; 849 } else { 850 goto bad_reg; 851 } 852 gic_update(s); 853 return; 854 bad_reg: 855 qemu_log_mask(LOG_GUEST_ERROR, 856 "gic_dist_writeb: Bad offset %x\n", (int)offset); 857 } 858 859 static void gic_dist_writew(void *opaque, hwaddr offset, 860 uint32_t value, MemTxAttrs attrs) 861 { 862 gic_dist_writeb(opaque, offset, value & 0xff, attrs); 863 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); 864 } 865 866 static void gic_dist_writel(void *opaque, hwaddr offset, 867 uint32_t value, MemTxAttrs attrs) 868 { 869 GICState *s = (GICState *)opaque; 870 if (offset == 0xf00) { 871 int cpu; 872 int irq; 873 int mask; 874 int target_cpu; 875 876 cpu = gic_get_current_cpu(s); 877 irq = value & 0x3ff; 878 switch ((value >> 24) & 3) { 879 case 0: 880 mask = (value >> 16) & ALL_CPU_MASK; 881 break; 882 case 1: 883 mask = ALL_CPU_MASK ^ (1 << cpu); 884 break; 885 case 2: 886 mask = 1 << cpu; 887 break; 888 default: 889 DPRINTF("Bad Soft Int target filter\n"); 890 mask = ALL_CPU_MASK; 891 break; 892 } 893 GIC_SET_PENDING(irq, mask); 894 target_cpu = ctz32(mask); 895 while (target_cpu < GIC_NCPU) { 896 s->sgi_pending[irq][target_cpu] |= (1 << cpu); 897 mask &= ~(1 << target_cpu); 898 target_cpu = ctz32(mask); 899 } 900 gic_update(s); 901 return; 902 } 903 gic_dist_writew(opaque, offset, value & 0xffff, attrs); 904 gic_dist_writew(opaque, offset + 2, value >> 16, attrs); 905 } 906 907 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, 908 unsigned size, MemTxAttrs attrs) 909 { 910 switch (size) { 911 case 1: 912 gic_dist_writeb(opaque, offset, data, attrs); 913 return MEMTX_OK; 914 case 2: 915 gic_dist_writew(opaque, offset, data, attrs); 916 return MEMTX_OK; 917 case 4: 918 gic_dist_writel(opaque, offset, data, attrs); 919 return MEMTX_OK; 920 default: 921 return MEMTX_ERROR; 922 } 923 } 924 925 static const MemoryRegionOps gic_dist_ops = { 926 .read_with_attrs = gic_dist_read, 927 .write_with_attrs = gic_dist_write, 928 .endianness = DEVICE_NATIVE_ENDIAN, 929 }; 930 931 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, 932 uint64_t *data, MemTxAttrs attrs) 933 { 934 switch (offset) { 935 case 0x00: /* Control */ 936 *data = gic_get_cpu_control(s, cpu, attrs); 937 break; 938 case 0x04: /* Priority mask */ 939 *data = gic_get_priority_mask(s, cpu, attrs); 940 break; 941 case 0x08: /* Binary Point */ 942 if (s->security_extn && !attrs.secure) { 943 /* BPR is banked. Non-secure copy stored in ABPR. */ 944 *data = s->abpr[cpu]; 945 } else { 946 *data = s->bpr[cpu]; 947 } 948 break; 949 case 0x0c: /* Acknowledge */ 950 *data = gic_acknowledge_irq(s, cpu, attrs); 951 break; 952 case 0x14: /* Running Priority */ 953 *data = gic_get_running_priority(s, cpu, attrs); 954 break; 955 case 0x18: /* Highest Pending Interrupt */ 956 *data = gic_get_current_pending_irq(s, cpu, attrs); 957 break; 958 case 0x1c: /* Aliased Binary Point */ 959 /* GIC v2, no security: ABPR 960 * GIC v1, no security: not implemented (RAZ/WI) 961 * With security extensions, secure access: ABPR (alias of NS BPR) 962 * With security extensions, nonsecure access: RAZ/WI 963 */ 964 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 965 *data = 0; 966 } else { 967 *data = s->abpr[cpu]; 968 } 969 break; 970 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 971 *data = s->apr[(offset - 0xd0) / 4][cpu]; 972 break; 973 default: 974 qemu_log_mask(LOG_GUEST_ERROR, 975 "gic_cpu_read: Bad offset %x\n", (int)offset); 976 return MEMTX_ERROR; 977 } 978 return MEMTX_OK; 979 } 980 981 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, 982 uint32_t value, MemTxAttrs attrs) 983 { 984 switch (offset) { 985 case 0x00: /* Control */ 986 gic_set_cpu_control(s, cpu, value, attrs); 987 break; 988 case 0x04: /* Priority mask */ 989 gic_set_priority_mask(s, cpu, value, attrs); 990 break; 991 case 0x08: /* Binary Point */ 992 if (s->security_extn && !attrs.secure) { 993 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 994 } else { 995 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); 996 } 997 break; 998 case 0x10: /* End Of Interrupt */ 999 gic_complete_irq(s, cpu, value & 0x3ff, attrs); 1000 return MEMTX_OK; 1001 case 0x1c: /* Aliased Binary Point */ 1002 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { 1003 /* unimplemented, or NS access: RAZ/WI */ 1004 return MEMTX_OK; 1005 } else { 1006 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); 1007 } 1008 break; 1009 case 0xd0: case 0xd4: case 0xd8: case 0xdc: 1010 qemu_log_mask(LOG_UNIMP, "Writing APR not implemented\n"); 1011 break; 1012 default: 1013 qemu_log_mask(LOG_GUEST_ERROR, 1014 "gic_cpu_write: Bad offset %x\n", (int)offset); 1015 return MEMTX_ERROR; 1016 } 1017 gic_update(s); 1018 return MEMTX_OK; 1019 } 1020 1021 /* Wrappers to read/write the GIC CPU interface for the current CPU */ 1022 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, 1023 unsigned size, MemTxAttrs attrs) 1024 { 1025 GICState *s = (GICState *)opaque; 1026 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); 1027 } 1028 1029 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, 1030 uint64_t value, unsigned size, 1031 MemTxAttrs attrs) 1032 { 1033 GICState *s = (GICState *)opaque; 1034 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); 1035 } 1036 1037 /* Wrappers to read/write the GIC CPU interface for a specific CPU. 1038 * These just decode the opaque pointer into GICState* + cpu id. 1039 */ 1040 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, 1041 unsigned size, MemTxAttrs attrs) 1042 { 1043 GICState **backref = (GICState **)opaque; 1044 GICState *s = *backref; 1045 int id = (backref - s->backref); 1046 return gic_cpu_read(s, id, addr, data, attrs); 1047 } 1048 1049 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, 1050 uint64_t value, unsigned size, 1051 MemTxAttrs attrs) 1052 { 1053 GICState **backref = (GICState **)opaque; 1054 GICState *s = *backref; 1055 int id = (backref - s->backref); 1056 return gic_cpu_write(s, id, addr, value, attrs); 1057 } 1058 1059 static const MemoryRegionOps gic_thiscpu_ops = { 1060 .read_with_attrs = gic_thiscpu_read, 1061 .write_with_attrs = gic_thiscpu_write, 1062 .endianness = DEVICE_NATIVE_ENDIAN, 1063 }; 1064 1065 static const MemoryRegionOps gic_cpu_ops = { 1066 .read_with_attrs = gic_do_cpu_read, 1067 .write_with_attrs = gic_do_cpu_write, 1068 .endianness = DEVICE_NATIVE_ENDIAN, 1069 }; 1070 1071 void gic_init_irqs_and_distributor(GICState *s) 1072 { 1073 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 1074 int i; 1075 1076 i = s->num_irq - GIC_INTERNAL; 1077 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. 1078 * GPIO array layout is thus: 1079 * [0..N-1] SPIs 1080 * [N..N+31] PPIs for CPU 0 1081 * [N+32..N+63] PPIs for CPU 1 1082 * ... 1083 */ 1084 if (s->revision != REV_NVIC) { 1085 i += (GIC_INTERNAL * s->num_cpu); 1086 } 1087 qdev_init_gpio_in(DEVICE(s), gic_set_irq, i); 1088 for (i = 0; i < NUM_CPU(s); i++) { 1089 sysbus_init_irq(sbd, &s->parent_irq[i]); 1090 } 1091 for (i = 0; i < NUM_CPU(s); i++) { 1092 sysbus_init_irq(sbd, &s->parent_fiq[i]); 1093 } 1094 memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, 1095 "gic_dist", 0x1000); 1096 } 1097 1098 static void arm_gic_realize(DeviceState *dev, Error **errp) 1099 { 1100 /* Device instance realize function for the GIC sysbus device */ 1101 int i; 1102 GICState *s = ARM_GIC(dev); 1103 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1104 ARMGICClass *agc = ARM_GIC_GET_CLASS(s); 1105 Error *local_err = NULL; 1106 1107 agc->parent_realize(dev, &local_err); 1108 if (local_err) { 1109 error_propagate(errp, local_err); 1110 return; 1111 } 1112 1113 gic_init_irqs_and_distributor(s); 1114 1115 /* Memory regions for the CPU interfaces (NVIC doesn't have these): 1116 * a region for "CPU interface for this core", then a region for 1117 * "CPU interface for core 0", "for core 1", ... 1118 * NB that the memory region size of 0x100 applies for the 11MPCore 1119 * and also cores following the GIC v1 spec (ie A9). 1120 * GIC v2 defines a larger memory region (0x1000) so this will need 1121 * to be extended when we implement A15. 1122 */ 1123 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s, 1124 "gic_cpu", 0x100); 1125 for (i = 0; i < NUM_CPU(s); i++) { 1126 s->backref[i] = s; 1127 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, 1128 &s->backref[i], "gic_cpu", 0x100); 1129 } 1130 /* Distributor */ 1131 sysbus_init_mmio(sbd, &s->iomem); 1132 /* cpu interfaces (one for "current cpu" plus one per cpu) */ 1133 for (i = 0; i <= NUM_CPU(s); i++) { 1134 sysbus_init_mmio(sbd, &s->cpuiomem[i]); 1135 } 1136 } 1137 1138 static void arm_gic_class_init(ObjectClass *klass, void *data) 1139 { 1140 DeviceClass *dc = DEVICE_CLASS(klass); 1141 ARMGICClass *agc = ARM_GIC_CLASS(klass); 1142 1143 agc->parent_realize = dc->realize; 1144 dc->realize = arm_gic_realize; 1145 } 1146 1147 static const TypeInfo arm_gic_info = { 1148 .name = TYPE_ARM_GIC, 1149 .parent = TYPE_ARM_GIC_COMMON, 1150 .instance_size = sizeof(GICState), 1151 .class_init = arm_gic_class_init, 1152 .class_size = sizeof(ARMGICClass), 1153 }; 1154 1155 static void arm_gic_register_types(void) 1156 { 1157 type_register_static(&arm_gic_info); 1158 } 1159 1160 type_init(arm_gic_register_types) 1161