1 /* 2 * APIC support - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * Copyright (c) 2011 Jan Kiszka, Siemens AG 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qemu/module.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "qapi/visitor.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/apic_internal.h" 29 #include "trace.h" 30 #include "sysemu/hax.h" 31 #include "sysemu/kvm.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/sysbus.h" 34 #include "migration/vmstate.h" 35 36 static int apic_irq_delivered; 37 bool apic_report_tpr_access; 38 39 void cpu_set_apic_base(DeviceState *dev, uint64_t val) 40 { 41 trace_cpu_set_apic_base(val); 42 43 if (dev) { 44 APICCommonState *s = APIC_COMMON(dev); 45 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 46 /* switching to x2APIC, reset possibly modified xAPIC ID */ 47 if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) && 48 (val & MSR_IA32_APICBASE_EXTD)) { 49 s->id = s->initial_apic_id; 50 } 51 info->set_base(s, val); 52 } 53 } 54 55 uint64_t cpu_get_apic_base(DeviceState *dev) 56 { 57 if (dev) { 58 APICCommonState *s = APIC_COMMON(dev); 59 trace_cpu_get_apic_base((uint64_t)s->apicbase); 60 return s->apicbase; 61 } else { 62 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); 63 return MSR_IA32_APICBASE_BSP; 64 } 65 } 66 67 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val) 68 { 69 APICCommonState *s; 70 APICCommonClass *info; 71 72 if (!dev) { 73 return; 74 } 75 76 s = APIC_COMMON(dev); 77 info = APIC_COMMON_GET_CLASS(s); 78 79 info->set_tpr(s, val); 80 } 81 82 uint8_t cpu_get_apic_tpr(DeviceState *dev) 83 { 84 APICCommonState *s; 85 APICCommonClass *info; 86 87 if (!dev) { 88 return 0; 89 } 90 91 s = APIC_COMMON(dev); 92 info = APIC_COMMON_GET_CLASS(s); 93 94 return info->get_tpr(s); 95 } 96 97 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable) 98 { 99 APICCommonState *s = APIC_COMMON(dev); 100 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 101 102 apic_report_tpr_access = enable; 103 if (info->enable_tpr_reporting) { 104 info->enable_tpr_reporting(s, enable); 105 } 106 } 107 108 void apic_enable_vapic(DeviceState *dev, hwaddr paddr) 109 { 110 APICCommonState *s = APIC_COMMON(dev); 111 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 112 113 s->vapic_paddr = paddr; 114 info->vapic_base_update(s); 115 } 116 117 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip, 118 TPRAccess access) 119 { 120 APICCommonState *s = APIC_COMMON(dev); 121 122 vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access); 123 } 124 125 void apic_report_irq_delivered(int delivered) 126 { 127 apic_irq_delivered += delivered; 128 129 trace_apic_report_irq_delivered(apic_irq_delivered); 130 } 131 132 void apic_reset_irq_delivered(void) 133 { 134 /* Copy this into a local variable to encourage gcc to emit a plain 135 * register for a sys/sdt.h marker. For details on this workaround, see: 136 * https://sourceware.org/bugzilla/show_bug.cgi?id=13296 137 */ 138 volatile int a_i_d = apic_irq_delivered; 139 trace_apic_reset_irq_delivered(a_i_d); 140 141 apic_irq_delivered = 0; 142 } 143 144 int apic_get_irq_delivered(void) 145 { 146 trace_apic_get_irq_delivered(apic_irq_delivered); 147 148 return apic_irq_delivered; 149 } 150 151 void apic_deliver_nmi(DeviceState *dev) 152 { 153 APICCommonState *s = APIC_COMMON(dev); 154 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 155 156 info->external_nmi(s); 157 } 158 159 bool apic_next_timer(APICCommonState *s, int64_t current_time) 160 { 161 int64_t d; 162 163 /* We need to store the timer state separately to support APIC 164 * implementations that maintain a non-QEMU timer, e.g. inside the 165 * host kernel. This open-coded state allows us to migrate between 166 * both models. */ 167 s->timer_expiry = -1; 168 169 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) { 170 return false; 171 } 172 173 d = (current_time - s->initial_count_load_time) >> s->count_shift; 174 175 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 176 if (!s->initial_count) { 177 return false; 178 } 179 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * 180 ((uint64_t)s->initial_count + 1); 181 } else { 182 if (d >= s->initial_count) { 183 return false; 184 } 185 d = (uint64_t)s->initial_count + 1; 186 } 187 s->next_time = s->initial_count_load_time + (d << s->count_shift); 188 s->timer_expiry = s->next_time; 189 return true; 190 } 191 192 void apic_init_reset(DeviceState *dev) 193 { 194 APICCommonState *s; 195 APICCommonClass *info; 196 int i; 197 198 if (!dev) { 199 return; 200 } 201 s = APIC_COMMON(dev); 202 s->tpr = 0; 203 s->spurious_vec = 0xff; 204 s->log_dest = 0; 205 s->dest_mode = 0xf; 206 memset(s->isr, 0, sizeof(s->isr)); 207 memset(s->tmr, 0, sizeof(s->tmr)); 208 memset(s->irr, 0, sizeof(s->irr)); 209 for (i = 0; i < APIC_LVT_NB; i++) { 210 s->lvt[i] = APIC_LVT_MASKED; 211 } 212 s->esr = 0; 213 memset(s->icr, 0, sizeof(s->icr)); 214 s->divide_conf = 0; 215 s->count_shift = 0; 216 s->initial_count = 0; 217 s->initial_count_load_time = 0; 218 s->next_time = 0; 219 s->wait_for_sipi = !cpu_is_bsp(s->cpu); 220 221 if (s->timer) { 222 timer_del(s->timer); 223 } 224 s->timer_expiry = -1; 225 226 info = APIC_COMMON_GET_CLASS(s); 227 if (info->reset) { 228 info->reset(s); 229 } 230 } 231 232 void apic_designate_bsp(DeviceState *dev, bool bsp) 233 { 234 if (dev == NULL) { 235 return; 236 } 237 238 APICCommonState *s = APIC_COMMON(dev); 239 if (bsp) { 240 s->apicbase |= MSR_IA32_APICBASE_BSP; 241 } else { 242 s->apicbase &= ~MSR_IA32_APICBASE_BSP; 243 } 244 } 245 246 static void apic_reset_common(DeviceState *dev) 247 { 248 APICCommonState *s = APIC_COMMON(dev); 249 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 250 uint32_t bsp; 251 252 bsp = s->apicbase & MSR_IA32_APICBASE_BSP; 253 s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; 254 s->id = s->initial_apic_id; 255 256 apic_reset_irq_delivered(); 257 258 s->vapic_paddr = 0; 259 info->vapic_base_update(s); 260 261 apic_init_reset(dev); 262 } 263 264 static const VMStateDescription vmstate_apic_common; 265 266 static void apic_common_realize(DeviceState *dev, Error **errp) 267 { 268 APICCommonState *s = APIC_COMMON(dev); 269 APICCommonClass *info; 270 static DeviceState *vapic; 271 int instance_id = s->id; 272 273 info = APIC_COMMON_GET_CLASS(s); 274 info->realize(dev, errp); 275 276 /* Note: We need at least 1M to map the VAPIC option ROM */ 277 if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && 278 !hax_enabled() && ram_size >= 1024 * 1024) { 279 vapic = sysbus_create_simple("kvmvapic", -1, NULL); 280 } 281 s->vapic = vapic; 282 if (apic_report_tpr_access && info->enable_tpr_reporting) { 283 info->enable_tpr_reporting(s, true); 284 } 285 286 if (s->legacy_instance_id) { 287 instance_id = -1; 288 } 289 vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common, 290 s, -1, 0, NULL); 291 } 292 293 static void apic_common_unrealize(DeviceState *dev, Error **errp) 294 { 295 APICCommonState *s = APIC_COMMON(dev); 296 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 297 298 vmstate_unregister(NULL, &vmstate_apic_common, s); 299 info->unrealize(dev, errp); 300 301 if (apic_report_tpr_access && info->enable_tpr_reporting) { 302 info->enable_tpr_reporting(s, false); 303 } 304 } 305 306 static int apic_pre_load(void *opaque) 307 { 308 APICCommonState *s = APIC_COMMON(opaque); 309 310 /* The default is !cpu_is_bsp(s->cpu), but the common value is 0 311 * so that's what apic_common_sipi_needed checks for. Reset to 312 * the value that is assumed when the apic_sipi subsection is 313 * absent. 314 */ 315 s->wait_for_sipi = 0; 316 return 0; 317 } 318 319 static int apic_dispatch_pre_save(void *opaque) 320 { 321 APICCommonState *s = APIC_COMMON(opaque); 322 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 323 324 if (info->pre_save) { 325 info->pre_save(s); 326 } 327 328 return 0; 329 } 330 331 static int apic_dispatch_post_load(void *opaque, int version_id) 332 { 333 APICCommonState *s = APIC_COMMON(opaque); 334 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 335 336 if (info->post_load) { 337 info->post_load(s); 338 } 339 return 0; 340 } 341 342 static bool apic_common_sipi_needed(void *opaque) 343 { 344 APICCommonState *s = APIC_COMMON(opaque); 345 return s->wait_for_sipi != 0; 346 } 347 348 static const VMStateDescription vmstate_apic_common_sipi = { 349 .name = "apic_sipi", 350 .version_id = 1, 351 .minimum_version_id = 1, 352 .needed = apic_common_sipi_needed, 353 .fields = (VMStateField[]) { 354 VMSTATE_INT32(sipi_vector, APICCommonState), 355 VMSTATE_INT32(wait_for_sipi, APICCommonState), 356 VMSTATE_END_OF_LIST() 357 } 358 }; 359 360 static const VMStateDescription vmstate_apic_common = { 361 .name = "apic", 362 .version_id = 3, 363 .minimum_version_id = 3, 364 .pre_load = apic_pre_load, 365 .pre_save = apic_dispatch_pre_save, 366 .post_load = apic_dispatch_post_load, 367 .fields = (VMStateField[]) { 368 VMSTATE_UINT32(apicbase, APICCommonState), 369 VMSTATE_UINT8(id, APICCommonState), 370 VMSTATE_UINT8(arb_id, APICCommonState), 371 VMSTATE_UINT8(tpr, APICCommonState), 372 VMSTATE_UINT32(spurious_vec, APICCommonState), 373 VMSTATE_UINT8(log_dest, APICCommonState), 374 VMSTATE_UINT8(dest_mode, APICCommonState), 375 VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), 376 VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), 377 VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), 378 VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), 379 VMSTATE_UINT32(esr, APICCommonState), 380 VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), 381 VMSTATE_UINT32(divide_conf, APICCommonState), 382 VMSTATE_INT32(count_shift, APICCommonState), 383 VMSTATE_UINT32(initial_count, APICCommonState), 384 VMSTATE_INT64(initial_count_load_time, APICCommonState), 385 VMSTATE_INT64(next_time, APICCommonState), 386 VMSTATE_INT64(timer_expiry, 387 APICCommonState), /* open-coded timer state */ 388 VMSTATE_END_OF_LIST() 389 }, 390 .subsections = (const VMStateDescription*[]) { 391 &vmstate_apic_common_sipi, 392 NULL 393 } 394 }; 395 396 static Property apic_properties_common[] = { 397 DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14), 398 DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, 399 true), 400 DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id, 401 false), 402 DEFINE_PROP_END_OF_LIST(), 403 }; 404 405 static void apic_common_get_id(Object *obj, Visitor *v, const char *name, 406 void *opaque, Error **errp) 407 { 408 APICCommonState *s = APIC_COMMON(obj); 409 uint32_t value; 410 411 value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id; 412 visit_type_uint32(v, name, &value, errp); 413 } 414 415 static void apic_common_set_id(Object *obj, Visitor *v, const char *name, 416 void *opaque, Error **errp) 417 { 418 APICCommonState *s = APIC_COMMON(obj); 419 DeviceState *dev = DEVICE(obj); 420 Error *local_err = NULL; 421 uint32_t value; 422 423 if (dev->realized) { 424 qdev_prop_set_after_realize(dev, name, errp); 425 return; 426 } 427 428 visit_type_uint32(v, name, &value, &local_err); 429 if (local_err) { 430 error_propagate(errp, local_err); 431 return; 432 } 433 434 s->initial_apic_id = value; 435 s->id = (uint8_t)value; 436 } 437 438 static void apic_common_initfn(Object *obj) 439 { 440 APICCommonState *s = APIC_COMMON(obj); 441 442 s->id = s->initial_apic_id = -1; 443 object_property_add(obj, "id", "uint32", 444 apic_common_get_id, 445 apic_common_set_id, NULL, NULL, NULL); 446 } 447 448 static void apic_common_class_init(ObjectClass *klass, void *data) 449 { 450 DeviceClass *dc = DEVICE_CLASS(klass); 451 452 dc->reset = apic_reset_common; 453 dc->props = apic_properties_common; 454 dc->realize = apic_common_realize; 455 dc->unrealize = apic_common_unrealize; 456 /* 457 * Reason: APIC and CPU need to be wired up by 458 * x86_cpu_apic_create() 459 */ 460 dc->user_creatable = false; 461 } 462 463 static const TypeInfo apic_common_type = { 464 .name = TYPE_APIC_COMMON, 465 .parent = TYPE_DEVICE, 466 .instance_size = sizeof(APICCommonState), 467 .instance_init = apic_common_initfn, 468 .class_size = sizeof(APICCommonClass), 469 .class_init = apic_common_class_init, 470 .abstract = true, 471 }; 472 473 static void apic_common_register_types(void) 474 { 475 type_register_static(&apic_common_type); 476 } 477 478 type_init(apic_common_register_types) 479