1 /* 2 * APIC support - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * Copyright (c) 2011 Jan Kiszka, Siemens AG 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qemu/module.h" 24 #include "qapi/error.h" 25 #include "qapi/visitor.h" 26 #include "hw/i386/apic.h" 27 #include "hw/i386/apic_internal.h" 28 #include "hw/intc/kvm_irqcount.h" 29 #include "trace.h" 30 #include "hw/boards.h" 31 #include "sysemu/hax.h" 32 #include "sysemu/kvm.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/sysbus.h" 35 #include "migration/vmstate.h" 36 37 bool apic_report_tpr_access; 38 39 void cpu_set_apic_base(DeviceState *dev, uint64_t val) 40 { 41 trace_cpu_set_apic_base(val); 42 43 if (dev) { 44 APICCommonState *s = APIC_COMMON(dev); 45 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 46 /* switching to x2APIC, reset possibly modified xAPIC ID */ 47 if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) && 48 (val & MSR_IA32_APICBASE_EXTD)) { 49 s->id = s->initial_apic_id; 50 } 51 info->set_base(s, val); 52 } 53 } 54 55 uint64_t cpu_get_apic_base(DeviceState *dev) 56 { 57 if (dev) { 58 APICCommonState *s = APIC_COMMON(dev); 59 trace_cpu_get_apic_base((uint64_t)s->apicbase); 60 return s->apicbase; 61 } else { 62 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); 63 return MSR_IA32_APICBASE_BSP; 64 } 65 } 66 67 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val) 68 { 69 APICCommonState *s; 70 APICCommonClass *info; 71 72 if (!dev) { 73 return; 74 } 75 76 s = APIC_COMMON(dev); 77 info = APIC_COMMON_GET_CLASS(s); 78 79 info->set_tpr(s, val); 80 } 81 82 uint8_t cpu_get_apic_tpr(DeviceState *dev) 83 { 84 APICCommonState *s; 85 APICCommonClass *info; 86 87 if (!dev) { 88 return 0; 89 } 90 91 s = APIC_COMMON(dev); 92 info = APIC_COMMON_GET_CLASS(s); 93 94 return info->get_tpr(s); 95 } 96 97 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable) 98 { 99 APICCommonState *s = APIC_COMMON(dev); 100 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 101 102 apic_report_tpr_access = enable; 103 if (info->enable_tpr_reporting) { 104 info->enable_tpr_reporting(s, enable); 105 } 106 } 107 108 void apic_enable_vapic(DeviceState *dev, hwaddr paddr) 109 { 110 APICCommonState *s = APIC_COMMON(dev); 111 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 112 113 s->vapic_paddr = paddr; 114 info->vapic_base_update(s); 115 } 116 117 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip, 118 TPRAccess access) 119 { 120 APICCommonState *s = APIC_COMMON(dev); 121 122 vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access); 123 } 124 125 void apic_deliver_nmi(DeviceState *dev) 126 { 127 APICCommonState *s = APIC_COMMON(dev); 128 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 129 130 info->external_nmi(s); 131 } 132 133 bool apic_next_timer(APICCommonState *s, int64_t current_time) 134 { 135 int64_t d; 136 137 /* We need to store the timer state separately to support APIC 138 * implementations that maintain a non-QEMU timer, e.g. inside the 139 * host kernel. This open-coded state allows us to migrate between 140 * both models. */ 141 s->timer_expiry = -1; 142 143 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) { 144 return false; 145 } 146 147 d = (current_time - s->initial_count_load_time) >> s->count_shift; 148 149 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 150 if (!s->initial_count) { 151 return false; 152 } 153 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * 154 ((uint64_t)s->initial_count + 1); 155 } else { 156 if (d >= s->initial_count) { 157 return false; 158 } 159 d = (uint64_t)s->initial_count + 1; 160 } 161 s->next_time = s->initial_count_load_time + (d << s->count_shift); 162 s->timer_expiry = s->next_time; 163 return true; 164 } 165 166 uint32_t apic_get_current_count(APICCommonState *s) 167 { 168 int64_t d; 169 uint32_t val; 170 d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >> 171 s->count_shift; 172 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 173 /* periodic */ 174 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); 175 } else { 176 if (d >= s->initial_count) { 177 val = 0; 178 } else { 179 val = s->initial_count - d; 180 } 181 } 182 return val; 183 } 184 185 void apic_init_reset(DeviceState *dev) 186 { 187 APICCommonState *s; 188 APICCommonClass *info; 189 int i; 190 191 if (!dev) { 192 return; 193 } 194 s = APIC_COMMON(dev); 195 s->tpr = 0; 196 s->spurious_vec = 0xff; 197 s->log_dest = 0; 198 s->dest_mode = 0xf; 199 memset(s->isr, 0, sizeof(s->isr)); 200 memset(s->tmr, 0, sizeof(s->tmr)); 201 memset(s->irr, 0, sizeof(s->irr)); 202 for (i = 0; i < APIC_LVT_NB; i++) { 203 s->lvt[i] = APIC_LVT_MASKED; 204 } 205 s->esr = 0; 206 memset(s->icr, 0, sizeof(s->icr)); 207 s->divide_conf = 0; 208 s->count_shift = 0; 209 s->initial_count = 0; 210 s->initial_count_load_time = 0; 211 s->next_time = 0; 212 s->wait_for_sipi = !cpu_is_bsp(s->cpu); 213 214 if (s->timer) { 215 timer_del(s->timer); 216 } 217 s->timer_expiry = -1; 218 219 info = APIC_COMMON_GET_CLASS(s); 220 if (info->reset) { 221 info->reset(s); 222 } 223 } 224 225 void apic_designate_bsp(DeviceState *dev, bool bsp) 226 { 227 if (dev == NULL) { 228 return; 229 } 230 231 APICCommonState *s = APIC_COMMON(dev); 232 if (bsp) { 233 s->apicbase |= MSR_IA32_APICBASE_BSP; 234 } else { 235 s->apicbase &= ~MSR_IA32_APICBASE_BSP; 236 } 237 } 238 239 static void apic_reset_common(DeviceState *dev) 240 { 241 APICCommonState *s = APIC_COMMON(dev); 242 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 243 uint32_t bsp; 244 245 bsp = s->apicbase & MSR_IA32_APICBASE_BSP; 246 s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; 247 s->id = s->initial_apic_id; 248 249 kvm_reset_irq_delivered(); 250 251 s->vapic_paddr = 0; 252 info->vapic_base_update(s); 253 254 apic_init_reset(dev); 255 } 256 257 static const VMStateDescription vmstate_apic_common; 258 259 static void apic_common_realize(DeviceState *dev, Error **errp) 260 { 261 APICCommonState *s = APIC_COMMON(dev); 262 APICCommonClass *info; 263 static DeviceState *vapic; 264 uint32_t instance_id = s->initial_apic_id; 265 266 /* Normally initial APIC ID should be no more than hundreds */ 267 assert(instance_id != VMSTATE_INSTANCE_ID_ANY); 268 269 info = APIC_COMMON_GET_CLASS(s); 270 info->realize(dev, errp); 271 272 /* Note: We need at least 1M to map the VAPIC option ROM */ 273 if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && 274 !hax_enabled() && current_machine->ram_size >= 1024 * 1024) { 275 vapic = sysbus_create_simple("kvmvapic", -1, NULL); 276 } 277 s->vapic = vapic; 278 if (apic_report_tpr_access && info->enable_tpr_reporting) { 279 info->enable_tpr_reporting(s, true); 280 } 281 282 if (s->legacy_instance_id) { 283 instance_id = VMSTATE_INSTANCE_ID_ANY; 284 } 285 vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common, 286 s, -1, 0, NULL); 287 } 288 289 static void apic_common_unrealize(DeviceState *dev) 290 { 291 APICCommonState *s = APIC_COMMON(dev); 292 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 293 294 vmstate_unregister(NULL, &vmstate_apic_common, s); 295 info->unrealize(dev); 296 297 if (apic_report_tpr_access && info->enable_tpr_reporting) { 298 info->enable_tpr_reporting(s, false); 299 } 300 } 301 302 static int apic_pre_load(void *opaque) 303 { 304 APICCommonState *s = APIC_COMMON(opaque); 305 306 /* The default is !cpu_is_bsp(s->cpu), but the common value is 0 307 * so that's what apic_common_sipi_needed checks for. Reset to 308 * the value that is assumed when the apic_sipi subsection is 309 * absent. 310 */ 311 s->wait_for_sipi = 0; 312 return 0; 313 } 314 315 static int apic_dispatch_pre_save(void *opaque) 316 { 317 APICCommonState *s = APIC_COMMON(opaque); 318 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 319 320 if (info->pre_save) { 321 info->pre_save(s); 322 } 323 324 return 0; 325 } 326 327 static int apic_dispatch_post_load(void *opaque, int version_id) 328 { 329 APICCommonState *s = APIC_COMMON(opaque); 330 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 331 332 if (info->post_load) { 333 info->post_load(s); 334 } 335 return 0; 336 } 337 338 static bool apic_common_sipi_needed(void *opaque) 339 { 340 APICCommonState *s = APIC_COMMON(opaque); 341 return s->wait_for_sipi != 0; 342 } 343 344 static const VMStateDescription vmstate_apic_common_sipi = { 345 .name = "apic_sipi", 346 .version_id = 1, 347 .minimum_version_id = 1, 348 .needed = apic_common_sipi_needed, 349 .fields = (VMStateField[]) { 350 VMSTATE_INT32(sipi_vector, APICCommonState), 351 VMSTATE_INT32(wait_for_sipi, APICCommonState), 352 VMSTATE_END_OF_LIST() 353 } 354 }; 355 356 static const VMStateDescription vmstate_apic_common = { 357 .name = "apic", 358 .version_id = 3, 359 .minimum_version_id = 3, 360 .pre_load = apic_pre_load, 361 .pre_save = apic_dispatch_pre_save, 362 .post_load = apic_dispatch_post_load, 363 .fields = (VMStateField[]) { 364 VMSTATE_UINT32(apicbase, APICCommonState), 365 VMSTATE_UINT8(id, APICCommonState), 366 VMSTATE_UINT8(arb_id, APICCommonState), 367 VMSTATE_UINT8(tpr, APICCommonState), 368 VMSTATE_UINT32(spurious_vec, APICCommonState), 369 VMSTATE_UINT8(log_dest, APICCommonState), 370 VMSTATE_UINT8(dest_mode, APICCommonState), 371 VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), 372 VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), 373 VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), 374 VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), 375 VMSTATE_UINT32(esr, APICCommonState), 376 VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), 377 VMSTATE_UINT32(divide_conf, APICCommonState), 378 VMSTATE_INT32(count_shift, APICCommonState), 379 VMSTATE_UINT32(initial_count, APICCommonState), 380 VMSTATE_INT64(initial_count_load_time, APICCommonState), 381 VMSTATE_INT64(next_time, APICCommonState), 382 VMSTATE_INT64(timer_expiry, 383 APICCommonState), /* open-coded timer state */ 384 VMSTATE_END_OF_LIST() 385 }, 386 .subsections = (const VMStateDescription*[]) { 387 &vmstate_apic_common_sipi, 388 NULL 389 } 390 }; 391 392 static Property apic_properties_common[] = { 393 DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14), 394 DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, 395 true), 396 DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id, 397 false), 398 DEFINE_PROP_END_OF_LIST(), 399 }; 400 401 static void apic_common_get_id(Object *obj, Visitor *v, const char *name, 402 void *opaque, Error **errp) 403 { 404 APICCommonState *s = APIC_COMMON(obj); 405 uint32_t value; 406 407 value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id; 408 visit_type_uint32(v, name, &value, errp); 409 } 410 411 static void apic_common_set_id(Object *obj, Visitor *v, const char *name, 412 void *opaque, Error **errp) 413 { 414 APICCommonState *s = APIC_COMMON(obj); 415 DeviceState *dev = DEVICE(obj); 416 uint32_t value; 417 418 if (dev->realized) { 419 qdev_prop_set_after_realize(dev, name, errp); 420 return; 421 } 422 423 if (!visit_type_uint32(v, name, &value, errp)) { 424 return; 425 } 426 427 s->initial_apic_id = value; 428 s->id = (uint8_t)value; 429 } 430 431 static void apic_common_initfn(Object *obj) 432 { 433 APICCommonState *s = APIC_COMMON(obj); 434 435 s->id = s->initial_apic_id = -1; 436 object_property_add(obj, "id", "uint32", 437 apic_common_get_id, 438 apic_common_set_id, NULL, NULL); 439 } 440 441 static void apic_common_class_init(ObjectClass *klass, void *data) 442 { 443 DeviceClass *dc = DEVICE_CLASS(klass); 444 445 dc->reset = apic_reset_common; 446 device_class_set_props(dc, apic_properties_common); 447 dc->realize = apic_common_realize; 448 dc->unrealize = apic_common_unrealize; 449 /* 450 * Reason: APIC and CPU need to be wired up by 451 * x86_cpu_apic_create() 452 */ 453 dc->user_creatable = false; 454 } 455 456 static const TypeInfo apic_common_type = { 457 .name = TYPE_APIC_COMMON, 458 .parent = TYPE_DEVICE, 459 .instance_size = sizeof(APICCommonState), 460 .instance_init = apic_common_initfn, 461 .class_size = sizeof(APICCommonClass), 462 .class_init = apic_common_class_init, 463 .abstract = true, 464 }; 465 466 static void apic_common_register_types(void) 467 { 468 type_register_static(&apic_common_type); 469 } 470 471 type_init(apic_common_register_types) 472