1 /* 2 * APIC support - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * Copyright (c) 2011 Jan Kiszka, Siemens AG 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/> 19 */ 20 #include "hw/i386/apic.h" 21 #include "hw/i386/apic_internal.h" 22 #include "trace.h" 23 #include "sysemu/kvm.h" 24 #include "hw/qdev.h" 25 #include "hw/sysbus.h" 26 27 static int apic_irq_delivered; 28 bool apic_report_tpr_access; 29 30 void cpu_set_apic_base(DeviceState *dev, uint64_t val) 31 { 32 trace_cpu_set_apic_base(val); 33 34 if (dev) { 35 APICCommonState *s = APIC_COMMON(dev); 36 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 37 info->set_base(s, val); 38 } 39 } 40 41 uint64_t cpu_get_apic_base(DeviceState *dev) 42 { 43 if (dev) { 44 APICCommonState *s = APIC_COMMON(dev); 45 trace_cpu_get_apic_base((uint64_t)s->apicbase); 46 return s->apicbase; 47 } else { 48 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); 49 return MSR_IA32_APICBASE_BSP; 50 } 51 } 52 53 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val) 54 { 55 APICCommonState *s; 56 APICCommonClass *info; 57 58 if (!dev) { 59 return; 60 } 61 62 s = APIC_COMMON(dev); 63 info = APIC_COMMON_GET_CLASS(s); 64 65 info->set_tpr(s, val); 66 } 67 68 uint8_t cpu_get_apic_tpr(DeviceState *dev) 69 { 70 APICCommonState *s; 71 APICCommonClass *info; 72 73 if (!dev) { 74 return 0; 75 } 76 77 s = APIC_COMMON(dev); 78 info = APIC_COMMON_GET_CLASS(s); 79 80 return info->get_tpr(s); 81 } 82 83 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable) 84 { 85 APICCommonState *s = APIC_COMMON(dev); 86 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 87 88 apic_report_tpr_access = enable; 89 if (info->enable_tpr_reporting) { 90 info->enable_tpr_reporting(s, enable); 91 } 92 } 93 94 void apic_enable_vapic(DeviceState *dev, hwaddr paddr) 95 { 96 APICCommonState *s = APIC_COMMON(dev); 97 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 98 99 s->vapic_paddr = paddr; 100 info->vapic_base_update(s); 101 } 102 103 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip, 104 TPRAccess access) 105 { 106 APICCommonState *s = APIC_COMMON(dev); 107 108 vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access); 109 } 110 111 void apic_report_irq_delivered(int delivered) 112 { 113 apic_irq_delivered += delivered; 114 115 trace_apic_report_irq_delivered(apic_irq_delivered); 116 } 117 118 void apic_reset_irq_delivered(void) 119 { 120 /* Copy this into a local variable to encourage gcc to emit a plain 121 * register for a sys/sdt.h marker. For details on this workaround, see: 122 * https://sourceware.org/bugzilla/show_bug.cgi?id=13296 123 */ 124 volatile int a_i_d = apic_irq_delivered; 125 trace_apic_reset_irq_delivered(a_i_d); 126 127 apic_irq_delivered = 0; 128 } 129 130 int apic_get_irq_delivered(void) 131 { 132 trace_apic_get_irq_delivered(apic_irq_delivered); 133 134 return apic_irq_delivered; 135 } 136 137 void apic_deliver_nmi(DeviceState *dev) 138 { 139 APICCommonState *s = APIC_COMMON(dev); 140 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 141 142 info->external_nmi(s); 143 } 144 145 bool apic_next_timer(APICCommonState *s, int64_t current_time) 146 { 147 int64_t d; 148 149 /* We need to store the timer state separately to support APIC 150 * implementations that maintain a non-QEMU timer, e.g. inside the 151 * host kernel. This open-coded state allows us to migrate between 152 * both models. */ 153 s->timer_expiry = -1; 154 155 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) { 156 return false; 157 } 158 159 d = (current_time - s->initial_count_load_time) >> s->count_shift; 160 161 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 162 if (!s->initial_count) { 163 return false; 164 } 165 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * 166 ((uint64_t)s->initial_count + 1); 167 } else { 168 if (d >= s->initial_count) { 169 return false; 170 } 171 d = (uint64_t)s->initial_count + 1; 172 } 173 s->next_time = s->initial_count_load_time + (d << s->count_shift); 174 s->timer_expiry = s->next_time; 175 return true; 176 } 177 178 void apic_init_reset(DeviceState *dev) 179 { 180 APICCommonState *s = APIC_COMMON(dev); 181 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 182 int i; 183 184 if (!s) { 185 return; 186 } 187 s->tpr = 0; 188 s->spurious_vec = 0xff; 189 s->log_dest = 0; 190 s->dest_mode = 0xf; 191 memset(s->isr, 0, sizeof(s->isr)); 192 memset(s->tmr, 0, sizeof(s->tmr)); 193 memset(s->irr, 0, sizeof(s->irr)); 194 for (i = 0; i < APIC_LVT_NB; i++) { 195 s->lvt[i] = APIC_LVT_MASKED; 196 } 197 s->esr = 0; 198 memset(s->icr, 0, sizeof(s->icr)); 199 s->divide_conf = 0; 200 s->count_shift = 0; 201 s->initial_count = 0; 202 s->initial_count_load_time = 0; 203 s->next_time = 0; 204 s->wait_for_sipi = !cpu_is_bsp(s->cpu); 205 206 if (s->timer) { 207 timer_del(s->timer); 208 } 209 s->timer_expiry = -1; 210 211 if (info->reset) { 212 info->reset(s); 213 } 214 } 215 216 void apic_designate_bsp(DeviceState *dev) 217 { 218 if (dev == NULL) { 219 return; 220 } 221 222 APICCommonState *s = APIC_COMMON(dev); 223 s->apicbase |= MSR_IA32_APICBASE_BSP; 224 } 225 226 static void apic_reset_common(DeviceState *dev) 227 { 228 APICCommonState *s = APIC_COMMON(dev); 229 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 230 bool bsp; 231 232 bsp = cpu_is_bsp(s->cpu); 233 s->apicbase = APIC_DEFAULT_ADDRESS | 234 (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; 235 236 s->vapic_paddr = 0; 237 info->vapic_base_update(s); 238 239 apic_init_reset(dev); 240 241 if (bsp) { 242 /* 243 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization 244 * time typically by BIOS, so PIC interrupt can be delivered to the 245 * processor when local APIC is enabled. 246 */ 247 s->lvt[APIC_LVT_LINT0] = 0x700; 248 } 249 } 250 251 /* This function is only used for old state version 1 and 2 */ 252 static int apic_load_old(QEMUFile *f, void *opaque, int version_id) 253 { 254 APICCommonState *s = opaque; 255 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 256 int i; 257 258 if (version_id > 2) { 259 return -EINVAL; 260 } 261 262 /* XXX: what if the base changes? (registered memory regions) */ 263 qemu_get_be32s(f, &s->apicbase); 264 qemu_get_8s(f, &s->id); 265 qemu_get_8s(f, &s->arb_id); 266 qemu_get_8s(f, &s->tpr); 267 qemu_get_be32s(f, &s->spurious_vec); 268 qemu_get_8s(f, &s->log_dest); 269 qemu_get_8s(f, &s->dest_mode); 270 for (i = 0; i < 8; i++) { 271 qemu_get_be32s(f, &s->isr[i]); 272 qemu_get_be32s(f, &s->tmr[i]); 273 qemu_get_be32s(f, &s->irr[i]); 274 } 275 for (i = 0; i < APIC_LVT_NB; i++) { 276 qemu_get_be32s(f, &s->lvt[i]); 277 } 278 qemu_get_be32s(f, &s->esr); 279 qemu_get_be32s(f, &s->icr[0]); 280 qemu_get_be32s(f, &s->icr[1]); 281 qemu_get_be32s(f, &s->divide_conf); 282 s->count_shift = qemu_get_be32(f); 283 qemu_get_be32s(f, &s->initial_count); 284 s->initial_count_load_time = qemu_get_be64(f); 285 s->next_time = qemu_get_be64(f); 286 287 if (version_id >= 2) { 288 s->timer_expiry = qemu_get_be64(f); 289 } 290 291 if (info->post_load) { 292 info->post_load(s); 293 } 294 return 0; 295 } 296 297 static void apic_common_realize(DeviceState *dev, Error **errp) 298 { 299 APICCommonState *s = APIC_COMMON(dev); 300 APICCommonClass *info; 301 static DeviceState *vapic; 302 static int apic_no; 303 static bool mmio_registered; 304 305 if (apic_no >= MAX_APICS) { 306 error_setg(errp, "%s initialization failed.", 307 object_get_typename(OBJECT(dev))); 308 return; 309 } 310 s->idx = apic_no++; 311 312 info = APIC_COMMON_GET_CLASS(s); 313 info->realize(dev, errp); 314 if (!mmio_registered) { 315 ICCBus *b = ICC_BUS(qdev_get_parent_bus(dev)); 316 memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory); 317 mmio_registered = true; 318 } 319 320 /* Note: We need at least 1M to map the VAPIC option ROM */ 321 if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && 322 ram_size >= 1024 * 1024) { 323 vapic = sysbus_create_simple("kvmvapic", -1, NULL); 324 } 325 s->vapic = vapic; 326 if (apic_report_tpr_access && info->enable_tpr_reporting) { 327 info->enable_tpr_reporting(s, true); 328 } 329 330 } 331 332 static int apic_pre_load(void *opaque) 333 { 334 APICCommonState *s = APIC_COMMON(opaque); 335 336 /* The default is !cpu_is_bsp(s->cpu), but the common value is 0 337 * so that's what apic_common_sipi_needed checks for. Reset to 338 * the value that is assumed when the apic_sipi subsection is 339 * absent. 340 */ 341 s->wait_for_sipi = 0; 342 return 0; 343 } 344 345 static void apic_dispatch_pre_save(void *opaque) 346 { 347 APICCommonState *s = APIC_COMMON(opaque); 348 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 349 350 if (info->pre_save) { 351 info->pre_save(s); 352 } 353 } 354 355 static int apic_dispatch_post_load(void *opaque, int version_id) 356 { 357 APICCommonState *s = APIC_COMMON(opaque); 358 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 359 360 if (info->post_load) { 361 info->post_load(s); 362 } 363 return 0; 364 } 365 366 static bool apic_common_sipi_needed(void *opaque) 367 { 368 APICCommonState *s = APIC_COMMON(opaque); 369 return s->wait_for_sipi != 0; 370 } 371 372 static const VMStateDescription vmstate_apic_common_sipi = { 373 .name = "apic_sipi", 374 .version_id = 1, 375 .minimum_version_id = 1, 376 .fields = (VMStateField[]) { 377 VMSTATE_INT32(sipi_vector, APICCommonState), 378 VMSTATE_INT32(wait_for_sipi, APICCommonState), 379 VMSTATE_END_OF_LIST() 380 } 381 }; 382 383 static const VMStateDescription vmstate_apic_common = { 384 .name = "apic", 385 .version_id = 3, 386 .minimum_version_id = 3, 387 .minimum_version_id_old = 1, 388 .load_state_old = apic_load_old, 389 .pre_load = apic_pre_load, 390 .pre_save = apic_dispatch_pre_save, 391 .post_load = apic_dispatch_post_load, 392 .fields = (VMStateField[]) { 393 VMSTATE_UINT32(apicbase, APICCommonState), 394 VMSTATE_UINT8(id, APICCommonState), 395 VMSTATE_UINT8(arb_id, APICCommonState), 396 VMSTATE_UINT8(tpr, APICCommonState), 397 VMSTATE_UINT32(spurious_vec, APICCommonState), 398 VMSTATE_UINT8(log_dest, APICCommonState), 399 VMSTATE_UINT8(dest_mode, APICCommonState), 400 VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), 401 VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), 402 VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), 403 VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), 404 VMSTATE_UINT32(esr, APICCommonState), 405 VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), 406 VMSTATE_UINT32(divide_conf, APICCommonState), 407 VMSTATE_INT32(count_shift, APICCommonState), 408 VMSTATE_UINT32(initial_count, APICCommonState), 409 VMSTATE_INT64(initial_count_load_time, APICCommonState), 410 VMSTATE_INT64(next_time, APICCommonState), 411 VMSTATE_INT64(timer_expiry, 412 APICCommonState), /* open-coded timer state */ 413 VMSTATE_END_OF_LIST() 414 }, 415 .subsections = (VMStateSubsection[]) { 416 { 417 .vmsd = &vmstate_apic_common_sipi, 418 .needed = apic_common_sipi_needed, 419 }, 420 VMSTATE_END_OF_LIST() 421 } 422 }; 423 424 static Property apic_properties_common[] = { 425 DEFINE_PROP_UINT8("id", APICCommonState, id, -1), 426 DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14), 427 DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, 428 true), 429 DEFINE_PROP_END_OF_LIST(), 430 }; 431 432 static void apic_common_class_init(ObjectClass *klass, void *data) 433 { 434 ICCDeviceClass *idc = ICC_DEVICE_CLASS(klass); 435 DeviceClass *dc = DEVICE_CLASS(klass); 436 437 dc->vmsd = &vmstate_apic_common; 438 dc->reset = apic_reset_common; 439 dc->props = apic_properties_common; 440 idc->realize = apic_common_realize; 441 /* 442 * Reason: APIC and CPU need to be wired up by 443 * x86_cpu_apic_create() 444 */ 445 dc->cannot_instantiate_with_device_add_yet = true; 446 } 447 448 static const TypeInfo apic_common_type = { 449 .name = TYPE_APIC_COMMON, 450 .parent = TYPE_ICC_DEVICE, 451 .instance_size = sizeof(APICCommonState), 452 .class_size = sizeof(APICCommonClass), 453 .class_init = apic_common_class_init, 454 .abstract = true, 455 }; 456 457 static void apic_common_register_types(void) 458 { 459 type_register_static(&apic_common_type); 460 } 461 462 type_init(apic_common_register_types) 463