1 /* 2 * APIC support - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * Copyright (c) 2011 Jan Kiszka, Siemens AG 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/> 19 */ 20 #include "hw/i386/apic.h" 21 #include "hw/i386/apic_internal.h" 22 #include "trace.h" 23 #include "sysemu/kvm.h" 24 #include "hw/qdev.h" 25 #include "hw/sysbus.h" 26 27 static int apic_irq_delivered; 28 bool apic_report_tpr_access; 29 30 void cpu_set_apic_base(DeviceState *d, uint64_t val) 31 { 32 trace_cpu_set_apic_base(val); 33 34 if (d) { 35 APICCommonState *s = APIC_COMMON(d); 36 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 37 info->set_base(s, val); 38 } 39 } 40 41 uint64_t cpu_get_apic_base(DeviceState *d) 42 { 43 if (d) { 44 APICCommonState *s = APIC_COMMON(d); 45 trace_cpu_get_apic_base((uint64_t)s->apicbase); 46 return s->apicbase; 47 } else { 48 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); 49 return MSR_IA32_APICBASE_BSP; 50 } 51 } 52 53 void cpu_set_apic_tpr(DeviceState *d, uint8_t val) 54 { 55 APICCommonState *s; 56 APICCommonClass *info; 57 58 if (!d) { 59 return; 60 } 61 62 s = APIC_COMMON(d); 63 info = APIC_COMMON_GET_CLASS(s); 64 65 info->set_tpr(s, val); 66 } 67 68 uint8_t cpu_get_apic_tpr(DeviceState *d) 69 { 70 APICCommonState *s; 71 APICCommonClass *info; 72 73 if (!d) { 74 return 0; 75 } 76 77 s = APIC_COMMON(d); 78 info = APIC_COMMON_GET_CLASS(s); 79 80 return info->get_tpr(s); 81 } 82 83 void apic_enable_tpr_access_reporting(DeviceState *d, bool enable) 84 { 85 APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); 86 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 87 88 apic_report_tpr_access = enable; 89 if (info->enable_tpr_reporting) { 90 info->enable_tpr_reporting(s, enable); 91 } 92 } 93 94 void apic_enable_vapic(DeviceState *d, hwaddr paddr) 95 { 96 APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); 97 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 98 99 s->vapic_paddr = paddr; 100 info->vapic_base_update(s); 101 } 102 103 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, 104 TPRAccess access) 105 { 106 APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); 107 108 vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access); 109 } 110 111 void apic_report_irq_delivered(int delivered) 112 { 113 apic_irq_delivered += delivered; 114 115 trace_apic_report_irq_delivered(apic_irq_delivered); 116 } 117 118 void apic_reset_irq_delivered(void) 119 { 120 trace_apic_reset_irq_delivered(apic_irq_delivered); 121 122 apic_irq_delivered = 0; 123 } 124 125 int apic_get_irq_delivered(void) 126 { 127 trace_apic_get_irq_delivered(apic_irq_delivered); 128 129 return apic_irq_delivered; 130 } 131 132 void apic_deliver_nmi(DeviceState *d) 133 { 134 APICCommonState *s = APIC_COMMON(d); 135 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 136 137 info->external_nmi(s); 138 } 139 140 bool apic_next_timer(APICCommonState *s, int64_t current_time) 141 { 142 int64_t d; 143 144 /* We need to store the timer state separately to support APIC 145 * implementations that maintain a non-QEMU timer, e.g. inside the 146 * host kernel. This open-coded state allows us to migrate between 147 * both models. */ 148 s->timer_expiry = -1; 149 150 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) { 151 return false; 152 } 153 154 d = (current_time - s->initial_count_load_time) >> s->count_shift; 155 156 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 157 if (!s->initial_count) { 158 return false; 159 } 160 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * 161 ((uint64_t)s->initial_count + 1); 162 } else { 163 if (d >= s->initial_count) { 164 return false; 165 } 166 d = (uint64_t)s->initial_count + 1; 167 } 168 s->next_time = s->initial_count_load_time + (d << s->count_shift); 169 s->timer_expiry = s->next_time; 170 return true; 171 } 172 173 void apic_init_reset(DeviceState *d) 174 { 175 APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); 176 int i; 177 178 if (!s) { 179 return; 180 } 181 s->tpr = 0; 182 s->spurious_vec = 0xff; 183 s->log_dest = 0; 184 s->dest_mode = 0xf; 185 memset(s->isr, 0, sizeof(s->isr)); 186 memset(s->tmr, 0, sizeof(s->tmr)); 187 memset(s->irr, 0, sizeof(s->irr)); 188 for (i = 0; i < APIC_LVT_NB; i++) { 189 s->lvt[i] = APIC_LVT_MASKED; 190 } 191 s->esr = 0; 192 memset(s->icr, 0, sizeof(s->icr)); 193 s->divide_conf = 0; 194 s->count_shift = 0; 195 s->initial_count = 0; 196 s->initial_count_load_time = 0; 197 s->next_time = 0; 198 s->wait_for_sipi = 1; 199 200 if (s->timer) { 201 qemu_del_timer(s->timer); 202 } 203 s->timer_expiry = -1; 204 } 205 206 void apic_designate_bsp(DeviceState *d) 207 { 208 if (d == NULL) { 209 return; 210 } 211 212 APICCommonState *s = APIC_COMMON(d); 213 s->apicbase |= MSR_IA32_APICBASE_BSP; 214 } 215 216 static void apic_reset_common(DeviceState *d) 217 { 218 APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); 219 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 220 bool bsp; 221 222 bsp = cpu_is_bsp(s->cpu); 223 s->apicbase = APIC_DEFAULT_ADDRESS | 224 (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; 225 226 s->vapic_paddr = 0; 227 info->vapic_base_update(s); 228 229 apic_init_reset(d); 230 231 if (bsp) { 232 /* 233 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization 234 * time typically by BIOS, so PIC interrupt can be delivered to the 235 * processor when local APIC is enabled. 236 */ 237 s->lvt[APIC_LVT_LINT0] = 0x700; 238 } 239 } 240 241 /* This function is only used for old state version 1 and 2 */ 242 static int apic_load_old(QEMUFile *f, void *opaque, int version_id) 243 { 244 APICCommonState *s = opaque; 245 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 246 int i; 247 248 if (version_id > 2) { 249 return -EINVAL; 250 } 251 252 /* XXX: what if the base changes? (registered memory regions) */ 253 qemu_get_be32s(f, &s->apicbase); 254 qemu_get_8s(f, &s->id); 255 qemu_get_8s(f, &s->arb_id); 256 qemu_get_8s(f, &s->tpr); 257 qemu_get_be32s(f, &s->spurious_vec); 258 qemu_get_8s(f, &s->log_dest); 259 qemu_get_8s(f, &s->dest_mode); 260 for (i = 0; i < 8; i++) { 261 qemu_get_be32s(f, &s->isr[i]); 262 qemu_get_be32s(f, &s->tmr[i]); 263 qemu_get_be32s(f, &s->irr[i]); 264 } 265 for (i = 0; i < APIC_LVT_NB; i++) { 266 qemu_get_be32s(f, &s->lvt[i]); 267 } 268 qemu_get_be32s(f, &s->esr); 269 qemu_get_be32s(f, &s->icr[0]); 270 qemu_get_be32s(f, &s->icr[1]); 271 qemu_get_be32s(f, &s->divide_conf); 272 s->count_shift = qemu_get_be32(f); 273 qemu_get_be32s(f, &s->initial_count); 274 s->initial_count_load_time = qemu_get_be64(f); 275 s->next_time = qemu_get_be64(f); 276 277 if (version_id >= 2) { 278 s->timer_expiry = qemu_get_be64(f); 279 } 280 281 if (info->post_load) { 282 info->post_load(s); 283 } 284 return 0; 285 } 286 287 static int apic_init_common(ICCDevice *dev) 288 { 289 APICCommonState *s = APIC_COMMON(dev); 290 APICCommonClass *info; 291 static DeviceState *vapic; 292 static int apic_no; 293 static bool mmio_registered; 294 295 if (apic_no >= MAX_APICS) { 296 return -1; 297 } 298 s->idx = apic_no++; 299 300 info = APIC_COMMON_GET_CLASS(s); 301 info->init(s); 302 if (!mmio_registered) { 303 ICCBus *b = ICC_BUS(qdev_get_parent_bus(DEVICE(dev))); 304 memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory); 305 mmio_registered = true; 306 } 307 308 /* Note: We need at least 1M to map the VAPIC option ROM */ 309 if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && 310 ram_size >= 1024 * 1024) { 311 vapic = sysbus_create_simple("kvmvapic", -1, NULL); 312 } 313 s->vapic = vapic; 314 if (apic_report_tpr_access && info->enable_tpr_reporting) { 315 info->enable_tpr_reporting(s, true); 316 } 317 318 return 0; 319 } 320 321 static void apic_dispatch_pre_save(void *opaque) 322 { 323 APICCommonState *s = APIC_COMMON(opaque); 324 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 325 326 if (info->pre_save) { 327 info->pre_save(s); 328 } 329 } 330 331 static int apic_dispatch_post_load(void *opaque, int version_id) 332 { 333 APICCommonState *s = APIC_COMMON(opaque); 334 APICCommonClass *info = APIC_COMMON_GET_CLASS(s); 335 336 if (info->post_load) { 337 info->post_load(s); 338 } 339 return 0; 340 } 341 342 static const VMStateDescription vmstate_apic_common = { 343 .name = "apic", 344 .version_id = 3, 345 .minimum_version_id = 3, 346 .minimum_version_id_old = 1, 347 .load_state_old = apic_load_old, 348 .pre_save = apic_dispatch_pre_save, 349 .post_load = apic_dispatch_post_load, 350 .fields = (VMStateField[]) { 351 VMSTATE_UINT32(apicbase, APICCommonState), 352 VMSTATE_UINT8(id, APICCommonState), 353 VMSTATE_UINT8(arb_id, APICCommonState), 354 VMSTATE_UINT8(tpr, APICCommonState), 355 VMSTATE_UINT32(spurious_vec, APICCommonState), 356 VMSTATE_UINT8(log_dest, APICCommonState), 357 VMSTATE_UINT8(dest_mode, APICCommonState), 358 VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), 359 VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), 360 VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), 361 VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), 362 VMSTATE_UINT32(esr, APICCommonState), 363 VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), 364 VMSTATE_UINT32(divide_conf, APICCommonState), 365 VMSTATE_INT32(count_shift, APICCommonState), 366 VMSTATE_UINT32(initial_count, APICCommonState), 367 VMSTATE_INT64(initial_count_load_time, APICCommonState), 368 VMSTATE_INT64(next_time, APICCommonState), 369 VMSTATE_INT64(timer_expiry, 370 APICCommonState), /* open-coded timer state */ 371 VMSTATE_END_OF_LIST() 372 } 373 }; 374 375 static Property apic_properties_common[] = { 376 DEFINE_PROP_UINT8("id", APICCommonState, id, -1), 377 DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, 378 true), 379 DEFINE_PROP_END_OF_LIST(), 380 }; 381 382 static void apic_common_class_init(ObjectClass *klass, void *data) 383 { 384 ICCDeviceClass *idc = ICC_DEVICE_CLASS(klass); 385 DeviceClass *dc = DEVICE_CLASS(klass); 386 387 dc->vmsd = &vmstate_apic_common; 388 dc->reset = apic_reset_common; 389 dc->no_user = 1; 390 dc->props = apic_properties_common; 391 idc->init = apic_init_common; 392 } 393 394 static const TypeInfo apic_common_type = { 395 .name = TYPE_APIC_COMMON, 396 .parent = TYPE_ICC_DEVICE, 397 .instance_size = sizeof(APICCommonState), 398 .class_size = sizeof(APICCommonClass), 399 .class_init = apic_common_class_init, 400 .abstract = true, 401 }; 402 403 static void register_types(void) 404 { 405 type_register_static(&apic_common_type); 406 } 407 408 type_init(register_types) 409