1 /*
2 * APIC support - common bits of emulated and KVM kernel model
3 *
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qemu/module.h"
24 #include "qapi/error.h"
25 #include "qapi/visitor.h"
26 #include "hw/i386/apic.h"
27 #include "hw/i386/apic_internal.h"
28 #include "hw/intc/kvm_irqcount.h"
29 #include "trace.h"
30 #include "hw/boards.h"
31 #include "sysemu/kvm.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/sysbus.h"
34 #include "migration/vmstate.h"
35
36 bool apic_report_tpr_access;
37
cpu_set_apic_base(DeviceState * dev,uint64_t val)38 void cpu_set_apic_base(DeviceState *dev, uint64_t val)
39 {
40 trace_cpu_set_apic_base(val);
41
42 if (dev) {
43 APICCommonState *s = APIC_COMMON(dev);
44 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
45 /* switching to x2APIC, reset possibly modified xAPIC ID */
46 if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) &&
47 (val & MSR_IA32_APICBASE_EXTD)) {
48 s->id = s->initial_apic_id;
49 }
50 info->set_base(s, val);
51 }
52 }
53
cpu_get_apic_base(DeviceState * dev)54 uint64_t cpu_get_apic_base(DeviceState *dev)
55 {
56 if (dev) {
57 APICCommonState *s = APIC_COMMON(dev);
58 trace_cpu_get_apic_base((uint64_t)s->apicbase);
59 return s->apicbase;
60 } else {
61 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
62 return MSR_IA32_APICBASE_BSP;
63 }
64 }
65
cpu_set_apic_tpr(DeviceState * dev,uint8_t val)66 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
67 {
68 APICCommonState *s;
69 APICCommonClass *info;
70
71 if (!dev) {
72 return;
73 }
74
75 s = APIC_COMMON(dev);
76 info = APIC_COMMON_GET_CLASS(s);
77
78 info->set_tpr(s, val);
79 }
80
cpu_get_apic_tpr(DeviceState * dev)81 uint8_t cpu_get_apic_tpr(DeviceState *dev)
82 {
83 APICCommonState *s;
84 APICCommonClass *info;
85
86 if (!dev) {
87 return 0;
88 }
89
90 s = APIC_COMMON(dev);
91 info = APIC_COMMON_GET_CLASS(s);
92
93 return info->get_tpr(s);
94 }
95
apic_enable_tpr_access_reporting(DeviceState * dev,bool enable)96 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
97 {
98 APICCommonState *s = APIC_COMMON(dev);
99 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
100
101 apic_report_tpr_access = enable;
102 if (info->enable_tpr_reporting) {
103 info->enable_tpr_reporting(s, enable);
104 }
105 }
106
apic_enable_vapic(DeviceState * dev,hwaddr paddr)107 void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
108 {
109 APICCommonState *s = APIC_COMMON(dev);
110 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
111
112 s->vapic_paddr = paddr;
113 info->vapic_base_update(s);
114 }
115
apic_handle_tpr_access_report(DeviceState * dev,target_ulong ip,TPRAccess access)116 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
117 TPRAccess access)
118 {
119 APICCommonState *s = APIC_COMMON(dev);
120
121 vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
122 }
123
apic_deliver_nmi(DeviceState * dev)124 void apic_deliver_nmi(DeviceState *dev)
125 {
126 APICCommonState *s = APIC_COMMON(dev);
127 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
128
129 info->external_nmi(s);
130 }
131
apic_next_timer(APICCommonState * s,int64_t current_time)132 bool apic_next_timer(APICCommonState *s, int64_t current_time)
133 {
134 int64_t d;
135
136 /* We need to store the timer state separately to support APIC
137 * implementations that maintain a non-QEMU timer, e.g. inside the
138 * host kernel. This open-coded state allows us to migrate between
139 * both models. */
140 s->timer_expiry = -1;
141
142 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
143 return false;
144 }
145
146 d = (current_time - s->initial_count_load_time) >> s->count_shift;
147
148 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
149 if (!s->initial_count) {
150 return false;
151 }
152 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
153 ((uint64_t)s->initial_count + 1);
154 } else {
155 if (d >= s->initial_count) {
156 return false;
157 }
158 d = (uint64_t)s->initial_count + 1;
159 }
160 s->next_time = s->initial_count_load_time + (d << s->count_shift);
161 s->timer_expiry = s->next_time;
162 return true;
163 }
164
apic_get_current_count(APICCommonState * s)165 uint32_t apic_get_current_count(APICCommonState *s)
166 {
167 int64_t d;
168 uint32_t val;
169 d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >>
170 s->count_shift;
171 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
172 /* periodic */
173 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
174 } else {
175 if (d >= s->initial_count) {
176 val = 0;
177 } else {
178 val = s->initial_count - d;
179 }
180 }
181 return val;
182 }
183
apic_init_reset(DeviceState * dev)184 void apic_init_reset(DeviceState *dev)
185 {
186 APICCommonState *s;
187 APICCommonClass *info;
188 int i;
189
190 if (!dev) {
191 return;
192 }
193 s = APIC_COMMON(dev);
194 s->tpr = 0;
195 s->spurious_vec = 0xff;
196 s->log_dest = 0;
197 s->dest_mode = 0xf;
198 memset(s->isr, 0, sizeof(s->isr));
199 memset(s->tmr, 0, sizeof(s->tmr));
200 memset(s->irr, 0, sizeof(s->irr));
201 for (i = 0; i < APIC_LVT_NB; i++) {
202 s->lvt[i] = APIC_LVT_MASKED;
203 }
204 s->esr = 0;
205 memset(s->icr, 0, sizeof(s->icr));
206 s->divide_conf = 0;
207 s->count_shift = 0;
208 s->initial_count = 0;
209 s->initial_count_load_time = 0;
210 s->next_time = 0;
211 s->wait_for_sipi = !cpu_is_bsp(s->cpu);
212
213 if (s->timer) {
214 timer_del(s->timer);
215 }
216 s->timer_expiry = -1;
217
218 info = APIC_COMMON_GET_CLASS(s);
219 if (info->reset) {
220 info->reset(s);
221 }
222 }
223
apic_designate_bsp(DeviceState * dev,bool bsp)224 void apic_designate_bsp(DeviceState *dev, bool bsp)
225 {
226 if (dev == NULL) {
227 return;
228 }
229
230 APICCommonState *s = APIC_COMMON(dev);
231 if (bsp) {
232 s->apicbase |= MSR_IA32_APICBASE_BSP;
233 } else {
234 s->apicbase &= ~MSR_IA32_APICBASE_BSP;
235 }
236 }
237
apic_reset_common(DeviceState * dev)238 static void apic_reset_common(DeviceState *dev)
239 {
240 APICCommonState *s = APIC_COMMON(dev);
241 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
242 uint32_t bsp;
243
244 bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
245 s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
246 s->id = s->initial_apic_id;
247
248 kvm_reset_irq_delivered();
249
250 s->vapic_paddr = 0;
251 info->vapic_base_update(s);
252
253 apic_init_reset(dev);
254 }
255
256 static const VMStateDescription vmstate_apic_common;
257
apic_common_realize(DeviceState * dev,Error ** errp)258 static void apic_common_realize(DeviceState *dev, Error **errp)
259 {
260 ERRP_GUARD();
261 APICCommonState *s = APIC_COMMON(dev);
262 APICCommonClass *info;
263 static DeviceState *vapic;
264 uint32_t instance_id = s->initial_apic_id;
265
266 /* Normally initial APIC ID should be no more than hundreds */
267 assert(instance_id != VMSTATE_INSTANCE_ID_ANY);
268
269 info = APIC_COMMON_GET_CLASS(s);
270 info->realize(dev, errp);
271 if (*errp) {
272 return;
273 }
274
275 /* Note: We need at least 1M to map the VAPIC option ROM */
276 if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
277 current_machine->ram_size >= 1024 * 1024) {
278 vapic = sysbus_create_simple("kvmvapic", -1, NULL);
279 }
280 s->vapic = vapic;
281 if (apic_report_tpr_access && info->enable_tpr_reporting) {
282 info->enable_tpr_reporting(s, true);
283 }
284
285 if (s->legacy_instance_id) {
286 instance_id = VMSTATE_INSTANCE_ID_ANY;
287 }
288 vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,
289 s, -1, 0, NULL);
290 }
291
apic_common_unrealize(DeviceState * dev)292 static void apic_common_unrealize(DeviceState *dev)
293 {
294 APICCommonState *s = APIC_COMMON(dev);
295 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
296
297 vmstate_unregister(NULL, &vmstate_apic_common, s);
298 info->unrealize(dev);
299
300 if (apic_report_tpr_access && info->enable_tpr_reporting) {
301 info->enable_tpr_reporting(s, false);
302 }
303 }
304
apic_pre_load(void * opaque)305 static int apic_pre_load(void *opaque)
306 {
307 APICCommonState *s = APIC_COMMON(opaque);
308
309 /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
310 * so that's what apic_common_sipi_needed checks for. Reset to
311 * the value that is assumed when the apic_sipi subsection is
312 * absent.
313 */
314 s->wait_for_sipi = 0;
315 return 0;
316 }
317
apic_dispatch_pre_save(void * opaque)318 static int apic_dispatch_pre_save(void *opaque)
319 {
320 APICCommonState *s = APIC_COMMON(opaque);
321 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
322
323 if (info->pre_save) {
324 info->pre_save(s);
325 }
326
327 return 0;
328 }
329
apic_dispatch_post_load(void * opaque,int version_id)330 static int apic_dispatch_post_load(void *opaque, int version_id)
331 {
332 APICCommonState *s = APIC_COMMON(opaque);
333 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
334
335 if (info->post_load) {
336 info->post_load(s);
337 }
338 return 0;
339 }
340
apic_common_sipi_needed(void * opaque)341 static bool apic_common_sipi_needed(void *opaque)
342 {
343 APICCommonState *s = APIC_COMMON(opaque);
344 return s->wait_for_sipi != 0;
345 }
346
347 static const VMStateDescription vmstate_apic_common_sipi = {
348 .name = "apic_sipi",
349 .version_id = 1,
350 .minimum_version_id = 1,
351 .needed = apic_common_sipi_needed,
352 .fields = (VMStateField[]) {
353 VMSTATE_INT32(sipi_vector, APICCommonState),
354 VMSTATE_INT32(wait_for_sipi, APICCommonState),
355 VMSTATE_END_OF_LIST()
356 }
357 };
358
359 static const VMStateDescription vmstate_apic_common = {
360 .name = "apic",
361 .version_id = 3,
362 .minimum_version_id = 3,
363 .pre_load = apic_pre_load,
364 .pre_save = apic_dispatch_pre_save,
365 .post_load = apic_dispatch_post_load,
366 .fields = (VMStateField[]) {
367 VMSTATE_UINT32(apicbase, APICCommonState),
368 VMSTATE_UINT8(id, APICCommonState),
369 VMSTATE_UINT8(arb_id, APICCommonState),
370 VMSTATE_UINT8(tpr, APICCommonState),
371 VMSTATE_UINT32(spurious_vec, APICCommonState),
372 VMSTATE_UINT8(log_dest, APICCommonState),
373 VMSTATE_UINT8(dest_mode, APICCommonState),
374 VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
375 VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
376 VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
377 VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
378 VMSTATE_UINT32(esr, APICCommonState),
379 VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
380 VMSTATE_UINT32(divide_conf, APICCommonState),
381 VMSTATE_INT32(count_shift, APICCommonState),
382 VMSTATE_UINT32(initial_count, APICCommonState),
383 VMSTATE_INT64(initial_count_load_time, APICCommonState),
384 VMSTATE_INT64(next_time, APICCommonState),
385 VMSTATE_INT64(timer_expiry,
386 APICCommonState), /* open-coded timer state */
387 VMSTATE_END_OF_LIST()
388 },
389 .subsections = (const VMStateDescription*[]) {
390 &vmstate_apic_common_sipi,
391 NULL
392 }
393 };
394
395 static Property apic_properties_common[] = {
396 DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
397 DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
398 true),
399 DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
400 false),
401 DEFINE_PROP_END_OF_LIST(),
402 };
403
apic_common_get_id(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)404 static void apic_common_get_id(Object *obj, Visitor *v, const char *name,
405 void *opaque, Error **errp)
406 {
407 APICCommonState *s = APIC_COMMON(obj);
408 uint32_t value;
409
410 value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id;
411 visit_type_uint32(v, name, &value, errp);
412 }
413
apic_common_set_id(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)414 static void apic_common_set_id(Object *obj, Visitor *v, const char *name,
415 void *opaque, Error **errp)
416 {
417 APICCommonState *s = APIC_COMMON(obj);
418 DeviceState *dev = DEVICE(obj);
419 uint32_t value;
420
421 if (dev->realized) {
422 qdev_prop_set_after_realize(dev, name, errp);
423 return;
424 }
425
426 if (!visit_type_uint32(v, name, &value, errp)) {
427 return;
428 }
429
430 s->initial_apic_id = value;
431 s->id = (uint8_t)value;
432 }
433
apic_common_initfn(Object * obj)434 static void apic_common_initfn(Object *obj)
435 {
436 APICCommonState *s = APIC_COMMON(obj);
437
438 s->id = s->initial_apic_id = -1;
439 object_property_add(obj, "id", "uint32",
440 apic_common_get_id,
441 apic_common_set_id, NULL, NULL);
442 }
443
apic_common_class_init(ObjectClass * klass,void * data)444 static void apic_common_class_init(ObjectClass *klass, void *data)
445 {
446 DeviceClass *dc = DEVICE_CLASS(klass);
447
448 dc->reset = apic_reset_common;
449 device_class_set_props(dc, apic_properties_common);
450 dc->realize = apic_common_realize;
451 dc->unrealize = apic_common_unrealize;
452 /*
453 * Reason: APIC and CPU need to be wired up by
454 * x86_cpu_apic_create()
455 */
456 dc->user_creatable = false;
457 }
458
459 static const TypeInfo apic_common_type = {
460 .name = TYPE_APIC_COMMON,
461 .parent = TYPE_DEVICE,
462 .instance_size = sizeof(APICCommonState),
463 .instance_init = apic_common_initfn,
464 .class_size = sizeof(APICCommonClass),
465 .class_init = apic_common_class_init,
466 .abstract = true,
467 };
468
apic_common_register_types(void)469 static void apic_common_register_types(void)
470 {
471 type_register_static(&apic_common_type);
472 }
473
474 type_init(apic_common_register_types)
475