1 /* 2 * APIC support 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/> 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu/thread.h" 21 #include "qemu/error-report.h" 22 #include "hw/i386/apic_internal.h" 23 #include "hw/i386/apic.h" 24 #include "hw/intc/ioapic.h" 25 #include "hw/intc/i8259.h" 26 #include "hw/intc/kvm_irqcount.h" 27 #include "hw/pci/msi.h" 28 #include "qemu/host-utils.h" 29 #include "system/kvm.h" 30 #include "trace.h" 31 #include "hw/i386/apic-msidef.h" 32 #include "qapi/error.h" 33 #include "qom/object.h" 34 35 #define SYNC_FROM_VAPIC 0x1 36 #define SYNC_TO_VAPIC 0x2 37 #define SYNC_ISR_IRR_TO_VAPIC 0x4 38 39 static APICCommonState **local_apics; 40 static uint32_t max_apics; 41 static uint32_t max_apic_words; 42 43 #define TYPE_APIC "apic" 44 /*This is reusing the APICCommonState typedef from APIC_COMMON */ 45 DECLARE_INSTANCE_CHECKER(APICCommonState, APIC, 46 TYPE_APIC) 47 48 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); 49 static void apic_update_irq(APICCommonState *s); 50 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 51 uint32_t dest, uint8_t dest_mode); 52 53 void apic_set_max_apic_id(uint32_t max_apic_id) 54 { 55 int word_size = 32; 56 57 /* round up the max apic id to next multiple of words */ 58 max_apics = (max_apic_id + word_size - 1) & ~(word_size - 1); 59 60 local_apics = g_malloc0(sizeof(*local_apics) * max_apics); 61 max_apic_words = max_apics >> 5; 62 } 63 64 65 /* Find first bit starting from msb */ 66 static int apic_fls_bit(uint32_t value) 67 { 68 return 31 - clz32(value); 69 } 70 71 /* Find first bit starting from lsb */ 72 static int apic_ffs_bit(uint32_t value) 73 { 74 return ctz32(value); 75 } 76 77 static inline void apic_reset_bit(uint32_t *tab, int index) 78 { 79 int i, mask; 80 i = index >> 5; 81 mask = 1 << (index & 0x1f); 82 tab[i] &= ~mask; 83 } 84 85 /* return -1 if no bit is set */ 86 static int get_highest_priority_int(uint32_t *tab) 87 { 88 int i; 89 for (i = 7; i >= 0; i--) { 90 if (tab[i] != 0) { 91 return i * 32 + apic_fls_bit(tab[i]); 92 } 93 } 94 return -1; 95 } 96 97 static void apic_sync_vapic(APICCommonState *s, int sync_type) 98 { 99 VAPICState vapic_state; 100 size_t length; 101 off_t start; 102 int vector; 103 104 if (!s->vapic_paddr) { 105 return; 106 } 107 if (sync_type & SYNC_FROM_VAPIC) { 108 cpu_physical_memory_read(s->vapic_paddr, &vapic_state, 109 sizeof(vapic_state)); 110 s->tpr = vapic_state.tpr; 111 } 112 if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) { 113 start = offsetof(VAPICState, isr); 114 length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); 115 116 if (sync_type & SYNC_TO_VAPIC) { 117 assert(qemu_cpu_is_self(CPU(s->cpu))); 118 119 vapic_state.tpr = s->tpr; 120 vapic_state.enabled = 1; 121 start = 0; 122 length = sizeof(VAPICState); 123 } 124 125 vector = get_highest_priority_int(s->isr); 126 if (vector < 0) { 127 vector = 0; 128 } 129 vapic_state.isr = vector & 0xf0; 130 131 vapic_state.zero = 0; 132 133 vector = get_highest_priority_int(s->irr); 134 if (vector < 0) { 135 vector = 0; 136 } 137 vapic_state.irr = vector & 0xff; 138 139 address_space_write_rom(&address_space_memory, 140 s->vapic_paddr + start, 141 MEMTXATTRS_UNSPECIFIED, 142 ((void *)&vapic_state) + start, length); 143 } 144 } 145 146 static void apic_vapic_base_update(APICCommonState *s) 147 { 148 apic_sync_vapic(s, SYNC_TO_VAPIC); 149 } 150 151 static void apic_local_deliver(APICCommonState *s, int vector) 152 { 153 uint32_t lvt = s->lvt[vector]; 154 int trigger_mode; 155 156 trace_apic_local_deliver(vector, (lvt >> 8) & 7); 157 158 if (lvt & APIC_LVT_MASKED) 159 return; 160 161 switch ((lvt >> 8) & 7) { 162 case APIC_DM_SMI: 163 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI); 164 break; 165 166 case APIC_DM_NMI: 167 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI); 168 break; 169 170 case APIC_DM_EXTINT: 171 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD); 172 break; 173 174 case APIC_DM_FIXED: 175 trigger_mode = APIC_TRIGGER_EDGE; 176 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && 177 (lvt & APIC_LVT_LEVEL_TRIGGER)) 178 trigger_mode = APIC_TRIGGER_LEVEL; 179 apic_set_irq(s, lvt & 0xff, trigger_mode); 180 } 181 } 182 183 void apic_deliver_pic_intr(DeviceState *dev, int level) 184 { 185 APICCommonState *s = APIC(dev); 186 187 if (level) { 188 apic_local_deliver(s, APIC_LVT_LINT0); 189 } else { 190 uint32_t lvt = s->lvt[APIC_LVT_LINT0]; 191 192 switch ((lvt >> 8) & 7) { 193 case APIC_DM_FIXED: 194 if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) 195 break; 196 apic_reset_bit(s->irr, lvt & 0xff); 197 /* fall through */ 198 case APIC_DM_EXTINT: 199 apic_update_irq(s); 200 break; 201 } 202 } 203 } 204 205 static void apic_external_nmi(APICCommonState *s) 206 { 207 apic_local_deliver(s, APIC_LVT_LINT1); 208 } 209 210 #define foreach_apic(apic, deliver_bitmask, code) \ 211 {\ 212 int __i, __j;\ 213 for (__i = 0; __i < max_apic_words; __i++) {\ 214 uint32_t __mask = deliver_bitmask[__i];\ 215 if (__mask) {\ 216 for (__j = 0; __j < 32; __j++) {\ 217 if (__mask & (1U << __j)) {\ 218 apic = local_apics[__i * 32 + __j];\ 219 if (apic) {\ 220 code;\ 221 }\ 222 }\ 223 }\ 224 }\ 225 }\ 226 } 227 228 static void apic_bus_deliver(const uint32_t *deliver_bitmask, 229 uint8_t delivery_mode, uint8_t vector_num, 230 uint8_t trigger_mode) 231 { 232 APICCommonState *apic_iter; 233 234 switch (delivery_mode) { 235 case APIC_DM_LOWPRI: 236 /* XXX: search for focus processor, arbitration */ 237 { 238 int i, d; 239 d = -1; 240 for (i = 0; i < max_apic_words; i++) { 241 if (deliver_bitmask[i]) { 242 d = i * 32 + apic_ffs_bit(deliver_bitmask[i]); 243 break; 244 } 245 } 246 if (d >= 0) { 247 apic_iter = local_apics[d]; 248 if (apic_iter) { 249 apic_set_irq(apic_iter, vector_num, trigger_mode); 250 } 251 } 252 } 253 return; 254 255 case APIC_DM_FIXED: 256 break; 257 258 case APIC_DM_SMI: 259 foreach_apic(apic_iter, deliver_bitmask, 260 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI) 261 ); 262 return; 263 264 case APIC_DM_NMI: 265 foreach_apic(apic_iter, deliver_bitmask, 266 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI) 267 ); 268 return; 269 270 case APIC_DM_INIT: 271 /* normal INIT IPI sent to processors */ 272 foreach_apic(apic_iter, deliver_bitmask, 273 cpu_interrupt(CPU(apic_iter->cpu), 274 CPU_INTERRUPT_INIT) 275 ); 276 return; 277 278 case APIC_DM_EXTINT: 279 /* handled in I/O APIC code */ 280 break; 281 282 default: 283 return; 284 } 285 286 foreach_apic(apic_iter, deliver_bitmask, 287 apic_set_irq(apic_iter, vector_num, trigger_mode) ); 288 } 289 290 static void apic_deliver_irq(uint32_t dest, uint8_t dest_mode, 291 uint8_t delivery_mode, uint8_t vector_num, 292 uint8_t trigger_mode) 293 { 294 g_autofree uint32_t *deliver_bitmask = g_new(uint32_t, max_apic_words); 295 296 trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, 297 trigger_mode); 298 299 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 300 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 301 } 302 303 bool is_x2apic_mode(DeviceState *dev) 304 { 305 APICCommonState *s = APIC(dev); 306 307 return s->apicbase & MSR_IA32_APICBASE_EXTD; 308 } 309 310 static int apic_set_base_check(APICCommonState *s, uint64_t val) 311 { 312 /* Enable x2apic when x2apic is not supported by CPU */ 313 if (!cpu_has_x2apic_feature(&s->cpu->env) && 314 val & MSR_IA32_APICBASE_EXTD) { 315 return -1; 316 } 317 318 /* 319 * Transition into invalid state 320 * (s->apicbase & MSR_IA32_APICBASE_ENABLE == 0) && 321 * (s->apicbase & MSR_IA32_APICBASE_EXTD) == 1 322 */ 323 if (!(val & MSR_IA32_APICBASE_ENABLE) && 324 (val & MSR_IA32_APICBASE_EXTD)) { 325 return -1; 326 } 327 328 /* Invalid transition from disabled mode to x2APIC */ 329 if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) && 330 !(s->apicbase & MSR_IA32_APICBASE_EXTD) && 331 (val & MSR_IA32_APICBASE_ENABLE) && 332 (val & MSR_IA32_APICBASE_EXTD)) { 333 return -1; 334 } 335 336 /* Invalid transition from x2APIC to xAPIC */ 337 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) && 338 (s->apicbase & MSR_IA32_APICBASE_EXTD) && 339 (val & MSR_IA32_APICBASE_ENABLE) && 340 !(val & MSR_IA32_APICBASE_EXTD)) { 341 return -1; 342 } 343 344 return 0; 345 } 346 347 static int apic_set_base(APICCommonState *s, uint64_t val) 348 { 349 if (apic_set_base_check(s, val) < 0) { 350 return -1; 351 } 352 353 s->apicbase = (val & MSR_IA32_APICBASE_BASE) | 354 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); 355 if (!(val & MSR_IA32_APICBASE_ENABLE)) { 356 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; 357 cpu_clear_apic_feature(&s->cpu->env); 358 s->spurious_vec &= ~APIC_SV_ENABLE; 359 } 360 361 /* Transition from disabled mode to xAPIC */ 362 if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) && 363 (val & MSR_IA32_APICBASE_ENABLE)) { 364 s->apicbase |= MSR_IA32_APICBASE_ENABLE; 365 cpu_set_apic_feature(&s->cpu->env); 366 } 367 368 /* Transition from xAPIC to x2APIC */ 369 if (cpu_has_x2apic_feature(&s->cpu->env) && 370 !(s->apicbase & MSR_IA32_APICBASE_EXTD) && 371 (val & MSR_IA32_APICBASE_EXTD)) { 372 s->apicbase |= MSR_IA32_APICBASE_EXTD; 373 374 s->log_dest = ((s->initial_apic_id & 0xffff0) << 16) | 375 (1 << (s->initial_apic_id & 0xf)); 376 } 377 378 return 0; 379 } 380 381 static void apic_set_tpr(APICCommonState *s, uint8_t val) 382 { 383 /* Updates from cr8 are ignored while the VAPIC is active */ 384 if (!s->vapic_paddr) { 385 s->tpr = val << 4; 386 apic_update_irq(s); 387 } 388 } 389 390 int apic_get_highest_priority_irr(DeviceState *dev) 391 { 392 APICCommonState *s; 393 394 if (!dev) { 395 /* no interrupts */ 396 return -1; 397 } 398 s = APIC_COMMON(dev); 399 return get_highest_priority_int(s->irr); 400 } 401 402 static uint8_t apic_get_tpr(APICCommonState *s) 403 { 404 apic_sync_vapic(s, SYNC_FROM_VAPIC); 405 return s->tpr >> 4; 406 } 407 408 int apic_get_ppr(APICCommonState *s) 409 { 410 int tpr, isrv, ppr; 411 412 tpr = (s->tpr >> 4); 413 isrv = get_highest_priority_int(s->isr); 414 if (isrv < 0) 415 isrv = 0; 416 isrv >>= 4; 417 if (tpr >= isrv) 418 ppr = s->tpr; 419 else 420 ppr = isrv << 4; 421 return ppr; 422 } 423 424 static int apic_get_arb_pri(APICCommonState *s) 425 { 426 /* XXX: arbitration */ 427 return 0; 428 } 429 430 431 /* 432 * <0 - low prio interrupt, 433 * 0 - no interrupt, 434 * >0 - interrupt number 435 */ 436 static int apic_irq_pending(APICCommonState *s) 437 { 438 int irrv, ppr; 439 440 if (!(s->spurious_vec & APIC_SV_ENABLE)) { 441 return 0; 442 } 443 444 irrv = get_highest_priority_int(s->irr); 445 if (irrv < 0) { 446 return 0; 447 } 448 ppr = apic_get_ppr(s); 449 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { 450 return -1; 451 } 452 453 return irrv; 454 } 455 456 /* signal the CPU if an irq is pending */ 457 static void apic_update_irq(APICCommonState *s) 458 { 459 CPUState *cpu; 460 DeviceState *dev = (DeviceState *)s; 461 462 cpu = CPU(s->cpu); 463 if (!qemu_cpu_is_self(cpu)) { 464 cpu_interrupt(cpu, CPU_INTERRUPT_POLL); 465 } else if (apic_irq_pending(s) > 0) { 466 cpu_interrupt(cpu, CPU_INTERRUPT_HARD); 467 } else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { 468 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); 469 } 470 } 471 472 void apic_poll_irq(DeviceState *dev) 473 { 474 APICCommonState *s = APIC(dev); 475 476 apic_sync_vapic(s, SYNC_FROM_VAPIC); 477 apic_update_irq(s); 478 } 479 480 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode) 481 { 482 kvm_report_irq_delivered(!apic_get_bit(s->irr, vector_num)); 483 484 apic_set_bit(s->irr, vector_num); 485 if (trigger_mode) 486 apic_set_bit(s->tmr, vector_num); 487 else 488 apic_reset_bit(s->tmr, vector_num); 489 if (s->vapic_paddr) { 490 apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC); 491 /* 492 * The vcpu thread needs to see the new IRR before we pull its current 493 * TPR value. That way, if we miss a lowering of the TRP, the guest 494 * has the chance to notice the new IRR and poll for IRQs on its own. 495 */ 496 smp_wmb(); 497 apic_sync_vapic(s, SYNC_FROM_VAPIC); 498 } 499 apic_update_irq(s); 500 } 501 502 static void apic_eoi(APICCommonState *s) 503 { 504 int isrv; 505 isrv = get_highest_priority_int(s->isr); 506 if (isrv < 0) 507 return; 508 apic_reset_bit(s->isr, isrv); 509 if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) { 510 ioapic_eoi_broadcast(isrv); 511 } 512 apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC); 513 apic_update_irq(s); 514 } 515 516 static bool apic_match_dest(APICCommonState *apic, uint32_t dest) 517 { 518 if (is_x2apic_mode(&apic->parent_obj)) { 519 return apic->initial_apic_id == dest; 520 } else { 521 return apic->id == (uint8_t)dest; 522 } 523 } 524 525 static void apic_find_dest(uint32_t *deliver_bitmask, uint32_t dest) 526 { 527 APICCommonState *apic = NULL; 528 int i; 529 530 for (i = 0; i < max_apics; i++) { 531 apic = local_apics[i]; 532 if (apic && apic_match_dest(apic, dest)) { 533 apic_set_bit(deliver_bitmask, i); 534 } 535 } 536 } 537 538 /* 539 * Deliver interrupt to x2APIC CPUs if it is x2APIC broadcast. 540 * Otherwise, deliver interrupt to xAPIC CPUs if it is xAPIC 541 * broadcast. 542 */ 543 static void apic_get_broadcast_bitmask(uint32_t *deliver_bitmask, 544 bool is_x2apic_broadcast) 545 { 546 int i; 547 APICCommonState *apic_iter; 548 549 for (i = 0; i < max_apics; i++) { 550 apic_iter = local_apics[i]; 551 if (apic_iter) { 552 bool apic_in_x2apic = is_x2apic_mode(&apic_iter->parent_obj); 553 554 if (is_x2apic_broadcast && apic_in_x2apic) { 555 apic_set_bit(deliver_bitmask, i); 556 } else if (!is_x2apic_broadcast && !apic_in_x2apic) { 557 apic_set_bit(deliver_bitmask, i); 558 } 559 } 560 } 561 } 562 563 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 564 uint32_t dest, uint8_t dest_mode) 565 { 566 APICCommonState *apic; 567 int i; 568 569 memset(deliver_bitmask, 0x00, max_apic_words * sizeof(uint32_t)); 570 571 /* 572 * x2APIC broadcast is delivered to all x2APIC CPUs regardless of 573 * destination mode. In case the destination mode is physical, it is 574 * broadcasted to all xAPIC CPUs too. Otherwise, if the destination 575 * mode is logical, we need to continue checking if xAPIC CPUs accepts 576 * the interrupt. 577 */ 578 if (dest == 0xffffffff) { 579 if (dest_mode == APIC_DESTMODE_PHYSICAL) { 580 memset(deliver_bitmask, 0xff, max_apic_words * sizeof(uint32_t)); 581 return; 582 } else { 583 apic_get_broadcast_bitmask(deliver_bitmask, true); 584 } 585 } 586 587 if (dest_mode == APIC_DESTMODE_PHYSICAL) { 588 apic_find_dest(deliver_bitmask, dest); 589 /* Any APIC in xAPIC mode will interpret 0xFF as broadcast */ 590 if (dest == 0xff) { 591 apic_get_broadcast_bitmask(deliver_bitmask, false); 592 } 593 } else { 594 /* XXX: logical mode */ 595 for (i = 0; i < max_apics; i++) { 596 apic = local_apics[i]; 597 if (apic) { 598 /* x2APIC logical mode */ 599 if (apic->apicbase & MSR_IA32_APICBASE_EXTD) { 600 if ((dest >> 16) == (apic->extended_log_dest >> 16) && 601 (dest & apic->extended_log_dest & 0xffff)) { 602 apic_set_bit(deliver_bitmask, i); 603 } 604 continue; 605 } 606 607 /* xAPIC logical mode */ 608 dest = (uint8_t)dest; 609 if (apic->dest_mode == APIC_DESTMODE_LOGICAL_FLAT) { 610 if (dest & apic->log_dest) { 611 apic_set_bit(deliver_bitmask, i); 612 } 613 } else if (apic->dest_mode == APIC_DESTMODE_LOGICAL_CLUSTER) { 614 /* 615 * In cluster model of xAPIC logical mode IPI, 4 higher 616 * bits are used as cluster address, 4 lower bits are 617 * the bitmask for local APICs in the cluster. The IPI 618 * is delivered to an APIC if the cluster address 619 * matches and the APIC's address bit in the cluster is 620 * set in bitmask of destination ID in IPI. 621 * 622 * The cluster address ranges from 0 - 14, the cluster 623 * address 15 (0xf) is the broadcast address to all 624 * clusters. 625 */ 626 if ((dest & 0xf0) == 0xf0 || 627 (dest & 0xf0) == (apic->log_dest & 0xf0)) { 628 if (dest & apic->log_dest & 0x0f) { 629 apic_set_bit(deliver_bitmask, i); 630 } 631 } 632 } 633 } 634 } 635 } 636 } 637 638 static void apic_startup(APICCommonState *s, int vector_num) 639 { 640 s->sipi_vector = vector_num; 641 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); 642 } 643 644 void apic_sipi(DeviceState *dev) 645 { 646 APICCommonState *s = APIC(dev); 647 648 if (!s->wait_for_sipi) 649 return; 650 cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector); 651 s->wait_for_sipi = 0; 652 } 653 654 static void apic_deliver(DeviceState *dev, uint32_t dest, uint8_t dest_mode, 655 uint8_t delivery_mode, uint8_t vector_num, 656 uint8_t trigger_mode, uint8_t dest_shorthand) 657 { 658 APICCommonState *s = APIC(dev); 659 APICCommonState *apic_iter; 660 uint32_t deliver_bitmask_size = max_apic_words * sizeof(uint32_t); 661 g_autofree uint32_t *deliver_bitmask = g_new(uint32_t, max_apic_words); 662 uint32_t current_apic_id; 663 664 if (is_x2apic_mode(dev)) { 665 current_apic_id = s->initial_apic_id; 666 } else { 667 current_apic_id = s->id; 668 } 669 670 switch (dest_shorthand) { 671 case 0: 672 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 673 break; 674 case 1: 675 memset(deliver_bitmask, 0x00, deliver_bitmask_size); 676 apic_set_bit(deliver_bitmask, current_apic_id); 677 break; 678 case 2: 679 memset(deliver_bitmask, 0xff, deliver_bitmask_size); 680 break; 681 case 3: 682 memset(deliver_bitmask, 0xff, deliver_bitmask_size); 683 apic_reset_bit(deliver_bitmask, current_apic_id); 684 break; 685 } 686 687 switch (delivery_mode) { 688 case APIC_DM_INIT: 689 { 690 int trig_mode = (s->icr[0] >> 15) & 1; 691 int level = (s->icr[0] >> 14) & 1; 692 if (level == 0 && trig_mode == 1) { 693 foreach_apic(apic_iter, deliver_bitmask, 694 apic_iter->arb_id = apic_iter->id ); 695 return; 696 } 697 } 698 break; 699 700 case APIC_DM_SIPI: 701 foreach_apic(apic_iter, deliver_bitmask, 702 apic_startup(apic_iter, vector_num) ); 703 return; 704 } 705 706 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 707 } 708 709 static bool apic_check_pic(APICCommonState *s) 710 { 711 DeviceState *dev = (DeviceState *)s; 712 713 if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { 714 return false; 715 } 716 apic_deliver_pic_intr(dev, 1); 717 return true; 718 } 719 720 int apic_get_interrupt(DeviceState *dev) 721 { 722 APICCommonState *s = APIC(dev); 723 int intno; 724 725 /* if the APIC is installed or enabled, we let the 8259 handle the 726 IRQs */ 727 if (!s) 728 return -1; 729 if (!(s->spurious_vec & APIC_SV_ENABLE)) 730 return -1; 731 732 apic_sync_vapic(s, SYNC_FROM_VAPIC); 733 intno = apic_irq_pending(s); 734 735 /* if there is an interrupt from the 8259, let the caller handle 736 * that first since ExtINT interrupts ignore the priority. 737 */ 738 if (intno == 0 || apic_check_pic(s)) { 739 apic_sync_vapic(s, SYNC_TO_VAPIC); 740 return -1; 741 } else if (intno < 0) { 742 apic_sync_vapic(s, SYNC_TO_VAPIC); 743 return s->spurious_vec & 0xff; 744 } 745 apic_reset_bit(s->irr, intno); 746 apic_set_bit(s->isr, intno); 747 apic_sync_vapic(s, SYNC_TO_VAPIC); 748 749 apic_update_irq(s); 750 751 return intno; 752 } 753 754 int apic_accept_pic_intr(DeviceState *dev) 755 { 756 APICCommonState *s = APIC(dev); 757 uint32_t lvt0; 758 759 if (!s) 760 return -1; 761 762 lvt0 = s->lvt[APIC_LVT_LINT0]; 763 764 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || 765 (lvt0 & APIC_LVT_MASKED) == 0) 766 return isa_pic != NULL; 767 768 return 0; 769 } 770 771 static void apic_timer_update(APICCommonState *s, int64_t current_time) 772 { 773 if (apic_next_timer(s, current_time)) { 774 timer_mod(s->timer, s->next_time); 775 } else { 776 timer_del(s->timer); 777 } 778 } 779 780 static void apic_timer(void *opaque) 781 { 782 APICCommonState *s = opaque; 783 784 apic_local_deliver(s, APIC_LVT_TIMER); 785 apic_timer_update(s, s->next_time); 786 } 787 788 static int apic_register_read(int index, uint64_t *value) 789 { 790 DeviceState *dev; 791 APICCommonState *s; 792 uint32_t val; 793 int ret = 0; 794 795 dev = cpu_get_current_apic(); 796 if (!dev) { 797 return -1; 798 } 799 s = APIC(dev); 800 801 switch(index) { 802 case 0x02: /* id */ 803 if (is_x2apic_mode(dev)) { 804 val = s->initial_apic_id; 805 } else { 806 val = s->id << 24; 807 } 808 break; 809 case 0x03: /* version */ 810 val = s->version | ((APIC_LVT_NB - 1) << 16); 811 break; 812 case 0x08: 813 apic_sync_vapic(s, SYNC_FROM_VAPIC); 814 if (apic_report_tpr_access) { 815 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ); 816 } 817 val = s->tpr; 818 break; 819 case 0x09: 820 val = apic_get_arb_pri(s); 821 break; 822 case 0x0a: 823 /* ppr */ 824 val = apic_get_ppr(s); 825 break; 826 case 0x0b: 827 val = 0; 828 break; 829 case 0x0d: 830 if (is_x2apic_mode(dev)) { 831 val = s->extended_log_dest; 832 } else { 833 val = s->log_dest << 24; 834 } 835 break; 836 case 0x0e: 837 if (is_x2apic_mode(dev)) { 838 val = 0; 839 ret = -1; 840 } else { 841 val = (s->dest_mode << 28) | 0xfffffff; 842 } 843 break; 844 case 0x0f: 845 val = s->spurious_vec; 846 break; 847 case 0x10 ... 0x17: 848 val = s->isr[index & 7]; 849 break; 850 case 0x18 ... 0x1f: 851 val = s->tmr[index & 7]; 852 break; 853 case 0x20 ... 0x27: 854 val = s->irr[index & 7]; 855 break; 856 case 0x28: 857 val = s->esr; 858 break; 859 case 0x30: 860 case 0x31: 861 val = s->icr[index & 1]; 862 break; 863 case 0x32 ... 0x37: 864 val = s->lvt[index - 0x32]; 865 break; 866 case 0x38: 867 val = s->initial_count; 868 break; 869 case 0x39: 870 val = apic_get_current_count(s); 871 break; 872 case 0x3e: 873 val = s->divide_conf; 874 break; 875 default: 876 s->esr |= APIC_ESR_ILLEGAL_ADDRESS; 877 val = 0; 878 ret = -1; 879 break; 880 } 881 882 trace_apic_register_read(index, val); 883 *value = val; 884 return ret; 885 } 886 887 static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) 888 { 889 uint64_t val; 890 int index; 891 892 if (size < 4) { 893 return 0; 894 } 895 896 index = (addr >> 4) & 0xff; 897 apic_register_read(index, &val); 898 899 return val; 900 } 901 902 int apic_msr_read(int index, uint64_t *val) 903 { 904 DeviceState *dev; 905 906 dev = cpu_get_current_apic(); 907 if (!dev) { 908 return -1; 909 } 910 911 if (!is_x2apic_mode(dev)) { 912 return -1; 913 } 914 915 return apic_register_read(index, val); 916 } 917 918 static void apic_send_msi(MSIMessage *msi) 919 { 920 uint64_t addr = msi->address; 921 uint32_t data = msi->data; 922 uint32_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; 923 /* 924 * The higher 3 bytes of destination id is stored in higher word of 925 * msi address. See x86_iommu_irq_to_msi_message() 926 */ 927 dest = dest | (addr >> 32); 928 uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; 929 uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; 930 uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; 931 uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; 932 /* XXX: Ignore redirection hint. */ 933 apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); 934 } 935 936 static int apic_register_write(int index, uint64_t val) 937 { 938 DeviceState *dev; 939 APICCommonState *s; 940 941 dev = cpu_get_current_apic(); 942 if (!dev) { 943 return -1; 944 } 945 s = APIC(dev); 946 947 trace_apic_register_write(index, val); 948 949 switch(index) { 950 case 0x02: 951 if (is_x2apic_mode(dev)) { 952 return -1; 953 } 954 955 s->id = (val >> 24); 956 break; 957 case 0x03: 958 break; 959 case 0x08: 960 if (apic_report_tpr_access) { 961 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE); 962 } 963 s->tpr = val; 964 apic_sync_vapic(s, SYNC_TO_VAPIC); 965 apic_update_irq(s); 966 break; 967 case 0x09: 968 case 0x0a: 969 break; 970 case 0x0b: /* EOI */ 971 apic_eoi(s); 972 break; 973 case 0x0d: 974 if (is_x2apic_mode(dev)) { 975 return -1; 976 } 977 978 s->log_dest = val >> 24; 979 break; 980 case 0x0e: 981 if (is_x2apic_mode(dev)) { 982 return -1; 983 } 984 985 s->dest_mode = val >> 28; 986 break; 987 case 0x0f: 988 s->spurious_vec = val & 0x1ff; 989 apic_update_irq(s); 990 break; 991 case 0x10 ... 0x17: 992 case 0x18 ... 0x1f: 993 case 0x20 ... 0x27: 994 case 0x28: 995 break; 996 case 0x30: { 997 uint32_t dest; 998 999 s->icr[0] = val; 1000 if (is_x2apic_mode(dev)) { 1001 s->icr[1] = val >> 32; 1002 dest = s->icr[1]; 1003 } else { 1004 dest = (s->icr[1] >> 24) & 0xff; 1005 } 1006 1007 apic_deliver(dev, dest, (s->icr[0] >> 11) & 1, 1008 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), 1009 (s->icr[0] >> 15) & 1, (s->icr[0] >> 18) & 3); 1010 break; 1011 } 1012 case 0x31: 1013 if (is_x2apic_mode(dev)) { 1014 return -1; 1015 } 1016 1017 s->icr[1] = val; 1018 break; 1019 case 0x32 ... 0x37: 1020 { 1021 int n = index - 0x32; 1022 s->lvt[n] = val; 1023 if (n == APIC_LVT_TIMER) { 1024 apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 1025 } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) { 1026 apic_update_irq(s); 1027 } 1028 } 1029 break; 1030 case 0x38: 1031 s->initial_count = val; 1032 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1033 apic_timer_update(s, s->initial_count_load_time); 1034 break; 1035 case 0x39: 1036 break; 1037 case 0x3e: 1038 { 1039 int v; 1040 s->divide_conf = val & 0xb; 1041 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); 1042 s->count_shift = (v + 1) & 7; 1043 } 1044 break; 1045 case 0x3f: { 1046 int vector = val & 0xff; 1047 1048 if (!is_x2apic_mode(dev)) { 1049 return -1; 1050 } 1051 1052 /* 1053 * Self IPI is identical to IPI with 1054 * - Destination shorthand: 1 (Self) 1055 * - Trigger mode: 0 (Edge) 1056 * - Delivery mode: 0 (Fixed) 1057 */ 1058 apic_deliver(dev, 0, 0, APIC_DM_FIXED, vector, 0, 1); 1059 1060 break; 1061 } 1062 default: 1063 s->esr |= APIC_ESR_ILLEGAL_ADDRESS; 1064 return -1; 1065 } 1066 1067 return 0; 1068 } 1069 1070 static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, 1071 unsigned size) 1072 { 1073 int index = (addr >> 4) & 0xff; 1074 1075 if (size < 4) { 1076 return; 1077 } 1078 1079 if (addr > 0xfff || !index) { 1080 /* 1081 * MSI and MMIO APIC are at the same memory location, 1082 * but actually not on the global bus: MSI is on PCI bus 1083 * APIC is connected directly to the CPU. 1084 * Mapping them on the global bus happens to work because 1085 * MSI registers are reserved in APIC MMIO and vice versa. 1086 */ 1087 MSIMessage msi = { .address = addr, .data = val }; 1088 apic_send_msi(&msi); 1089 return; 1090 } 1091 1092 apic_register_write(index, val); 1093 } 1094 1095 int apic_msr_write(int index, uint64_t val) 1096 { 1097 DeviceState *dev; 1098 1099 dev = cpu_get_current_apic(); 1100 if (!dev) { 1101 return -1; 1102 } 1103 1104 if (!is_x2apic_mode(dev)) { 1105 return -1; 1106 } 1107 1108 return apic_register_write(index, val); 1109 } 1110 1111 static void apic_pre_save(APICCommonState *s) 1112 { 1113 apic_sync_vapic(s, SYNC_FROM_VAPIC); 1114 } 1115 1116 static void apic_post_load(APICCommonState *s) 1117 { 1118 if (s->timer_expiry != -1) { 1119 timer_mod(s->timer, s->timer_expiry); 1120 } else { 1121 timer_del(s->timer); 1122 } 1123 } 1124 1125 static const MemoryRegionOps apic_io_ops = { 1126 .read = apic_mem_read, 1127 .write = apic_mem_write, 1128 .impl.min_access_size = 1, 1129 .impl.max_access_size = 4, 1130 .valid.min_access_size = 1, 1131 .valid.max_access_size = 4, 1132 .endianness = DEVICE_NATIVE_ENDIAN, 1133 }; 1134 1135 static void apic_realize(DeviceState *dev, Error **errp) 1136 { 1137 APICCommonState *s = APIC(dev); 1138 1139 if (kvm_enabled()) { 1140 warn_report("Userspace local APIC is deprecated for KVM."); 1141 warn_report("Do not use kernel-irqchip except for the -M isapc machine type."); 1142 } 1143 1144 memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi", 1145 APIC_SPACE_SIZE); 1146 1147 /* 1148 * apic-msi's apic_mem_write can call into ioapic_eoi_broadcast, which can 1149 * write back to apic-msi. As such mark the apic-msi region re-entrancy 1150 * safe. 1151 */ 1152 s->io_memory.disable_reentrancy_guard = true; 1153 1154 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s); 1155 1156 /* 1157 * The --machine none does not call apic_set_max_apic_id before creating 1158 * apic, so we need to call it here and set it to 1 which is the max cpus 1159 * in machine none. 1160 */ 1161 if (!local_apics) { 1162 apic_set_max_apic_id(1); 1163 } 1164 local_apics[s->initial_apic_id] = s; 1165 1166 msi_nonbroken = true; 1167 } 1168 1169 static void apic_unrealize(DeviceState *dev) 1170 { 1171 APICCommonState *s = APIC(dev); 1172 1173 timer_free(s->timer); 1174 local_apics[s->initial_apic_id] = NULL; 1175 } 1176 1177 static void apic_class_init(ObjectClass *klass, const void *data) 1178 { 1179 APICCommonClass *k = APIC_COMMON_CLASS(klass); 1180 1181 k->realize = apic_realize; 1182 k->unrealize = apic_unrealize; 1183 k->set_base = apic_set_base; 1184 k->set_tpr = apic_set_tpr; 1185 k->get_tpr = apic_get_tpr; 1186 k->vapic_base_update = apic_vapic_base_update; 1187 k->external_nmi = apic_external_nmi; 1188 k->pre_save = apic_pre_save; 1189 k->post_load = apic_post_load; 1190 k->send_msi = apic_send_msi; 1191 } 1192 1193 static const TypeInfo apic_info = { 1194 .name = TYPE_APIC, 1195 .instance_size = sizeof(APICCommonState), 1196 .parent = TYPE_APIC_COMMON, 1197 .class_init = apic_class_init, 1198 }; 1199 1200 static void apic_register_types(void) 1201 { 1202 type_register_static(&apic_info); 1203 } 1204 1205 type_init(apic_register_types) 1206