1 /* 2 * APIC support 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/> 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "qemu/thread.h" 23 #include "hw/i386/apic_internal.h" 24 #include "hw/i386/apic.h" 25 #include "hw/i386/ioapic.h" 26 #include "hw/pci/msi.h" 27 #include "qemu/host-utils.h" 28 #include "trace.h" 29 #include "hw/i386/pc.h" 30 #include "hw/i386/apic-msidef.h" 31 32 #define MAX_APIC_WORDS 8 33 34 #define SYNC_FROM_VAPIC 0x1 35 #define SYNC_TO_VAPIC 0x2 36 #define SYNC_ISR_IRR_TO_VAPIC 0x4 37 38 static APICCommonState *local_apics[MAX_APICS + 1]; 39 40 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); 41 static void apic_update_irq(APICCommonState *s); 42 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 43 uint8_t dest, uint8_t dest_mode); 44 45 /* Find first bit starting from msb */ 46 static int apic_fls_bit(uint32_t value) 47 { 48 return 31 - clz32(value); 49 } 50 51 /* Find first bit starting from lsb */ 52 static int apic_ffs_bit(uint32_t value) 53 { 54 return ctz32(value); 55 } 56 57 static inline void apic_reset_bit(uint32_t *tab, int index) 58 { 59 int i, mask; 60 i = index >> 5; 61 mask = 1 << (index & 0x1f); 62 tab[i] &= ~mask; 63 } 64 65 /* return -1 if no bit is set */ 66 static int get_highest_priority_int(uint32_t *tab) 67 { 68 int i; 69 for (i = 7; i >= 0; i--) { 70 if (tab[i] != 0) { 71 return i * 32 + apic_fls_bit(tab[i]); 72 } 73 } 74 return -1; 75 } 76 77 static void apic_sync_vapic(APICCommonState *s, int sync_type) 78 { 79 VAPICState vapic_state; 80 size_t length; 81 off_t start; 82 int vector; 83 84 if (!s->vapic_paddr) { 85 return; 86 } 87 if (sync_type & SYNC_FROM_VAPIC) { 88 cpu_physical_memory_read(s->vapic_paddr, &vapic_state, 89 sizeof(vapic_state)); 90 s->tpr = vapic_state.tpr; 91 } 92 if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) { 93 start = offsetof(VAPICState, isr); 94 length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); 95 96 if (sync_type & SYNC_TO_VAPIC) { 97 assert(qemu_cpu_is_self(CPU(s->cpu))); 98 99 vapic_state.tpr = s->tpr; 100 vapic_state.enabled = 1; 101 start = 0; 102 length = sizeof(VAPICState); 103 } 104 105 vector = get_highest_priority_int(s->isr); 106 if (vector < 0) { 107 vector = 0; 108 } 109 vapic_state.isr = vector & 0xf0; 110 111 vapic_state.zero = 0; 112 113 vector = get_highest_priority_int(s->irr); 114 if (vector < 0) { 115 vector = 0; 116 } 117 vapic_state.irr = vector & 0xff; 118 119 cpu_physical_memory_write_rom(&address_space_memory, 120 s->vapic_paddr + start, 121 ((void *)&vapic_state) + start, length); 122 } 123 } 124 125 static void apic_vapic_base_update(APICCommonState *s) 126 { 127 apic_sync_vapic(s, SYNC_TO_VAPIC); 128 } 129 130 static void apic_local_deliver(APICCommonState *s, int vector) 131 { 132 uint32_t lvt = s->lvt[vector]; 133 int trigger_mode; 134 135 trace_apic_local_deliver(vector, (lvt >> 8) & 7); 136 137 if (lvt & APIC_LVT_MASKED) 138 return; 139 140 switch ((lvt >> 8) & 7) { 141 case APIC_DM_SMI: 142 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI); 143 break; 144 145 case APIC_DM_NMI: 146 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI); 147 break; 148 149 case APIC_DM_EXTINT: 150 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD); 151 break; 152 153 case APIC_DM_FIXED: 154 trigger_mode = APIC_TRIGGER_EDGE; 155 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && 156 (lvt & APIC_LVT_LEVEL_TRIGGER)) 157 trigger_mode = APIC_TRIGGER_LEVEL; 158 apic_set_irq(s, lvt & 0xff, trigger_mode); 159 } 160 } 161 162 void apic_deliver_pic_intr(DeviceState *dev, int level) 163 { 164 APICCommonState *s = APIC_COMMON(dev); 165 166 if (level) { 167 apic_local_deliver(s, APIC_LVT_LINT0); 168 } else { 169 uint32_t lvt = s->lvt[APIC_LVT_LINT0]; 170 171 switch ((lvt >> 8) & 7) { 172 case APIC_DM_FIXED: 173 if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) 174 break; 175 apic_reset_bit(s->irr, lvt & 0xff); 176 /* fall through */ 177 case APIC_DM_EXTINT: 178 apic_update_irq(s); 179 break; 180 } 181 } 182 } 183 184 static void apic_external_nmi(APICCommonState *s) 185 { 186 apic_local_deliver(s, APIC_LVT_LINT1); 187 } 188 189 #define foreach_apic(apic, deliver_bitmask, code) \ 190 {\ 191 int __i, __j;\ 192 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ 193 uint32_t __mask = deliver_bitmask[__i];\ 194 if (__mask) {\ 195 for(__j = 0; __j < 32; __j++) {\ 196 if (__mask & (1U << __j)) {\ 197 apic = local_apics[__i * 32 + __j];\ 198 if (apic) {\ 199 code;\ 200 }\ 201 }\ 202 }\ 203 }\ 204 }\ 205 } 206 207 static void apic_bus_deliver(const uint32_t *deliver_bitmask, 208 uint8_t delivery_mode, uint8_t vector_num, 209 uint8_t trigger_mode) 210 { 211 APICCommonState *apic_iter; 212 213 switch (delivery_mode) { 214 case APIC_DM_LOWPRI: 215 /* XXX: search for focus processor, arbitration */ 216 { 217 int i, d; 218 d = -1; 219 for(i = 0; i < MAX_APIC_WORDS; i++) { 220 if (deliver_bitmask[i]) { 221 d = i * 32 + apic_ffs_bit(deliver_bitmask[i]); 222 break; 223 } 224 } 225 if (d >= 0) { 226 apic_iter = local_apics[d]; 227 if (apic_iter) { 228 apic_set_irq(apic_iter, vector_num, trigger_mode); 229 } 230 } 231 } 232 return; 233 234 case APIC_DM_FIXED: 235 break; 236 237 case APIC_DM_SMI: 238 foreach_apic(apic_iter, deliver_bitmask, 239 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI) 240 ); 241 return; 242 243 case APIC_DM_NMI: 244 foreach_apic(apic_iter, deliver_bitmask, 245 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI) 246 ); 247 return; 248 249 case APIC_DM_INIT: 250 /* normal INIT IPI sent to processors */ 251 foreach_apic(apic_iter, deliver_bitmask, 252 cpu_interrupt(CPU(apic_iter->cpu), 253 CPU_INTERRUPT_INIT) 254 ); 255 return; 256 257 case APIC_DM_EXTINT: 258 /* handled in I/O APIC code */ 259 break; 260 261 default: 262 return; 263 } 264 265 foreach_apic(apic_iter, deliver_bitmask, 266 apic_set_irq(apic_iter, vector_num, trigger_mode) ); 267 } 268 269 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, 270 uint8_t vector_num, uint8_t trigger_mode) 271 { 272 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 273 274 trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, 275 trigger_mode); 276 277 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 278 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 279 } 280 281 static void apic_set_base(APICCommonState *s, uint64_t val) 282 { 283 s->apicbase = (val & 0xfffff000) | 284 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); 285 /* if disabled, cannot be enabled again */ 286 if (!(val & MSR_IA32_APICBASE_ENABLE)) { 287 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; 288 cpu_clear_apic_feature(&s->cpu->env); 289 s->spurious_vec &= ~APIC_SV_ENABLE; 290 } 291 } 292 293 static void apic_set_tpr(APICCommonState *s, uint8_t val) 294 { 295 /* Updates from cr8 are ignored while the VAPIC is active */ 296 if (!s->vapic_paddr) { 297 s->tpr = val << 4; 298 apic_update_irq(s); 299 } 300 } 301 302 static uint8_t apic_get_tpr(APICCommonState *s) 303 { 304 apic_sync_vapic(s, SYNC_FROM_VAPIC); 305 return s->tpr >> 4; 306 } 307 308 int apic_get_ppr(APICCommonState *s) 309 { 310 int tpr, isrv, ppr; 311 312 tpr = (s->tpr >> 4); 313 isrv = get_highest_priority_int(s->isr); 314 if (isrv < 0) 315 isrv = 0; 316 isrv >>= 4; 317 if (tpr >= isrv) 318 ppr = s->tpr; 319 else 320 ppr = isrv << 4; 321 return ppr; 322 } 323 324 static int apic_get_arb_pri(APICCommonState *s) 325 { 326 /* XXX: arbitration */ 327 return 0; 328 } 329 330 331 /* 332 * <0 - low prio interrupt, 333 * 0 - no interrupt, 334 * >0 - interrupt number 335 */ 336 static int apic_irq_pending(APICCommonState *s) 337 { 338 int irrv, ppr; 339 340 if (!(s->spurious_vec & APIC_SV_ENABLE)) { 341 return 0; 342 } 343 344 irrv = get_highest_priority_int(s->irr); 345 if (irrv < 0) { 346 return 0; 347 } 348 ppr = apic_get_ppr(s); 349 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { 350 return -1; 351 } 352 353 return irrv; 354 } 355 356 /* signal the CPU if an irq is pending */ 357 static void apic_update_irq(APICCommonState *s) 358 { 359 CPUState *cpu; 360 DeviceState *dev = (DeviceState *)s; 361 362 cpu = CPU(s->cpu); 363 if (!qemu_cpu_is_self(cpu)) { 364 cpu_interrupt(cpu, CPU_INTERRUPT_POLL); 365 } else if (apic_irq_pending(s) > 0) { 366 cpu_interrupt(cpu, CPU_INTERRUPT_HARD); 367 } else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { 368 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); 369 } 370 } 371 372 void apic_poll_irq(DeviceState *dev) 373 { 374 APICCommonState *s = APIC_COMMON(dev); 375 376 apic_sync_vapic(s, SYNC_FROM_VAPIC); 377 apic_update_irq(s); 378 } 379 380 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode) 381 { 382 apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num)); 383 384 apic_set_bit(s->irr, vector_num); 385 if (trigger_mode) 386 apic_set_bit(s->tmr, vector_num); 387 else 388 apic_reset_bit(s->tmr, vector_num); 389 if (s->vapic_paddr) { 390 apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC); 391 /* 392 * The vcpu thread needs to see the new IRR before we pull its current 393 * TPR value. That way, if we miss a lowering of the TRP, the guest 394 * has the chance to notice the new IRR and poll for IRQs on its own. 395 */ 396 smp_wmb(); 397 apic_sync_vapic(s, SYNC_FROM_VAPIC); 398 } 399 apic_update_irq(s); 400 } 401 402 static void apic_eoi(APICCommonState *s) 403 { 404 int isrv; 405 isrv = get_highest_priority_int(s->isr); 406 if (isrv < 0) 407 return; 408 apic_reset_bit(s->isr, isrv); 409 if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) { 410 ioapic_eoi_broadcast(isrv); 411 } 412 apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC); 413 apic_update_irq(s); 414 } 415 416 static int apic_find_dest(uint8_t dest) 417 { 418 APICCommonState *apic = local_apics[dest]; 419 int i; 420 421 if (apic && apic->id == dest) 422 return dest; /* shortcut in case apic->id == apic->idx */ 423 424 for (i = 0; i < MAX_APICS; i++) { 425 apic = local_apics[i]; 426 if (apic && apic->id == dest) 427 return i; 428 if (!apic) 429 break; 430 } 431 432 return -1; 433 } 434 435 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 436 uint8_t dest, uint8_t dest_mode) 437 { 438 APICCommonState *apic_iter; 439 int i; 440 441 if (dest_mode == 0) { 442 if (dest == 0xff) { 443 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); 444 } else { 445 int idx = apic_find_dest(dest); 446 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 447 if (idx >= 0) 448 apic_set_bit(deliver_bitmask, idx); 449 } 450 } else { 451 /* XXX: cluster mode */ 452 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 453 for(i = 0; i < MAX_APICS; i++) { 454 apic_iter = local_apics[i]; 455 if (apic_iter) { 456 if (apic_iter->dest_mode == 0xf) { 457 if (dest & apic_iter->log_dest) 458 apic_set_bit(deliver_bitmask, i); 459 } else if (apic_iter->dest_mode == 0x0) { 460 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && 461 (dest & apic_iter->log_dest & 0x0f)) { 462 apic_set_bit(deliver_bitmask, i); 463 } 464 } 465 } else { 466 break; 467 } 468 } 469 } 470 } 471 472 static void apic_startup(APICCommonState *s, int vector_num) 473 { 474 s->sipi_vector = vector_num; 475 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); 476 } 477 478 void apic_sipi(DeviceState *dev) 479 { 480 APICCommonState *s = APIC_COMMON(dev); 481 482 cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); 483 484 if (!s->wait_for_sipi) 485 return; 486 cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector); 487 s->wait_for_sipi = 0; 488 } 489 490 static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode, 491 uint8_t delivery_mode, uint8_t vector_num, 492 uint8_t trigger_mode) 493 { 494 APICCommonState *s = APIC_COMMON(dev); 495 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 496 int dest_shorthand = (s->icr[0] >> 18) & 3; 497 APICCommonState *apic_iter; 498 499 switch (dest_shorthand) { 500 case 0: 501 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 502 break; 503 case 1: 504 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); 505 apic_set_bit(deliver_bitmask, s->idx); 506 break; 507 case 2: 508 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 509 break; 510 case 3: 511 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 512 apic_reset_bit(deliver_bitmask, s->idx); 513 break; 514 } 515 516 switch (delivery_mode) { 517 case APIC_DM_INIT: 518 { 519 int trig_mode = (s->icr[0] >> 15) & 1; 520 int level = (s->icr[0] >> 14) & 1; 521 if (level == 0 && trig_mode == 1) { 522 foreach_apic(apic_iter, deliver_bitmask, 523 apic_iter->arb_id = apic_iter->id ); 524 return; 525 } 526 } 527 break; 528 529 case APIC_DM_SIPI: 530 foreach_apic(apic_iter, deliver_bitmask, 531 apic_startup(apic_iter, vector_num) ); 532 return; 533 } 534 535 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 536 } 537 538 static bool apic_check_pic(APICCommonState *s) 539 { 540 DeviceState *dev = (DeviceState *)s; 541 542 if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { 543 return false; 544 } 545 apic_deliver_pic_intr(dev, 1); 546 return true; 547 } 548 549 int apic_get_interrupt(DeviceState *dev) 550 { 551 APICCommonState *s = APIC_COMMON(dev); 552 int intno; 553 554 /* if the APIC is installed or enabled, we let the 8259 handle the 555 IRQs */ 556 if (!s) 557 return -1; 558 if (!(s->spurious_vec & APIC_SV_ENABLE)) 559 return -1; 560 561 apic_sync_vapic(s, SYNC_FROM_VAPIC); 562 intno = apic_irq_pending(s); 563 564 /* if there is an interrupt from the 8259, let the caller handle 565 * that first since ExtINT interrupts ignore the priority. 566 */ 567 if (intno == 0 || apic_check_pic(s)) { 568 apic_sync_vapic(s, SYNC_TO_VAPIC); 569 return -1; 570 } else if (intno < 0) { 571 apic_sync_vapic(s, SYNC_TO_VAPIC); 572 return s->spurious_vec & 0xff; 573 } 574 apic_reset_bit(s->irr, intno); 575 apic_set_bit(s->isr, intno); 576 apic_sync_vapic(s, SYNC_TO_VAPIC); 577 578 apic_update_irq(s); 579 580 return intno; 581 } 582 583 int apic_accept_pic_intr(DeviceState *dev) 584 { 585 APICCommonState *s = APIC_COMMON(dev); 586 uint32_t lvt0; 587 588 if (!s) 589 return -1; 590 591 lvt0 = s->lvt[APIC_LVT_LINT0]; 592 593 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || 594 (lvt0 & APIC_LVT_MASKED) == 0) 595 return 1; 596 597 return 0; 598 } 599 600 static uint32_t apic_get_current_count(APICCommonState *s) 601 { 602 int64_t d; 603 uint32_t val; 604 d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >> 605 s->count_shift; 606 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 607 /* periodic */ 608 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); 609 } else { 610 if (d >= s->initial_count) 611 val = 0; 612 else 613 val = s->initial_count - d; 614 } 615 return val; 616 } 617 618 static void apic_timer_update(APICCommonState *s, int64_t current_time) 619 { 620 if (apic_next_timer(s, current_time)) { 621 timer_mod(s->timer, s->next_time); 622 } else { 623 timer_del(s->timer); 624 } 625 } 626 627 static void apic_timer(void *opaque) 628 { 629 APICCommonState *s = opaque; 630 631 apic_local_deliver(s, APIC_LVT_TIMER); 632 apic_timer_update(s, s->next_time); 633 } 634 635 static uint32_t apic_mem_readb(void *opaque, hwaddr addr) 636 { 637 return 0; 638 } 639 640 static uint32_t apic_mem_readw(void *opaque, hwaddr addr) 641 { 642 return 0; 643 } 644 645 static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val) 646 { 647 } 648 649 static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val) 650 { 651 } 652 653 static uint32_t apic_mem_readl(void *opaque, hwaddr addr) 654 { 655 DeviceState *dev; 656 APICCommonState *s; 657 uint32_t val; 658 int index; 659 660 dev = cpu_get_current_apic(); 661 if (!dev) { 662 return 0; 663 } 664 s = APIC_COMMON(dev); 665 666 index = (addr >> 4) & 0xff; 667 switch(index) { 668 case 0x02: /* id */ 669 val = s->id << 24; 670 break; 671 case 0x03: /* version */ 672 val = s->version | ((APIC_LVT_NB - 1) << 16); 673 break; 674 case 0x08: 675 apic_sync_vapic(s, SYNC_FROM_VAPIC); 676 if (apic_report_tpr_access) { 677 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ); 678 } 679 val = s->tpr; 680 break; 681 case 0x09: 682 val = apic_get_arb_pri(s); 683 break; 684 case 0x0a: 685 /* ppr */ 686 val = apic_get_ppr(s); 687 break; 688 case 0x0b: 689 val = 0; 690 break; 691 case 0x0d: 692 val = s->log_dest << 24; 693 break; 694 case 0x0e: 695 val = (s->dest_mode << 28) | 0xfffffff; 696 break; 697 case 0x0f: 698 val = s->spurious_vec; 699 break; 700 case 0x10 ... 0x17: 701 val = s->isr[index & 7]; 702 break; 703 case 0x18 ... 0x1f: 704 val = s->tmr[index & 7]; 705 break; 706 case 0x20 ... 0x27: 707 val = s->irr[index & 7]; 708 break; 709 case 0x28: 710 val = s->esr; 711 break; 712 case 0x30: 713 case 0x31: 714 val = s->icr[index & 1]; 715 break; 716 case 0x32 ... 0x37: 717 val = s->lvt[index - 0x32]; 718 break; 719 case 0x38: 720 val = s->initial_count; 721 break; 722 case 0x39: 723 val = apic_get_current_count(s); 724 break; 725 case 0x3e: 726 val = s->divide_conf; 727 break; 728 default: 729 s->esr |= APIC_ESR_ILLEGAL_ADDRESS; 730 val = 0; 731 break; 732 } 733 trace_apic_mem_readl(addr, val); 734 return val; 735 } 736 737 static void apic_send_msi(hwaddr addr, uint32_t data) 738 { 739 uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; 740 uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; 741 uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; 742 uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; 743 uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; 744 /* XXX: Ignore redirection hint. */ 745 apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); 746 } 747 748 static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val) 749 { 750 DeviceState *dev; 751 APICCommonState *s; 752 int index = (addr >> 4) & 0xff; 753 if (addr > 0xfff || !index) { 754 /* MSI and MMIO APIC are at the same memory location, 755 * but actually not on the global bus: MSI is on PCI bus 756 * APIC is connected directly to the CPU. 757 * Mapping them on the global bus happens to work because 758 * MSI registers are reserved in APIC MMIO and vice versa. */ 759 apic_send_msi(addr, val); 760 return; 761 } 762 763 dev = cpu_get_current_apic(); 764 if (!dev) { 765 return; 766 } 767 s = APIC_COMMON(dev); 768 769 trace_apic_mem_writel(addr, val); 770 771 switch(index) { 772 case 0x02: 773 s->id = (val >> 24); 774 break; 775 case 0x03: 776 break; 777 case 0x08: 778 if (apic_report_tpr_access) { 779 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE); 780 } 781 s->tpr = val; 782 apic_sync_vapic(s, SYNC_TO_VAPIC); 783 apic_update_irq(s); 784 break; 785 case 0x09: 786 case 0x0a: 787 break; 788 case 0x0b: /* EOI */ 789 apic_eoi(s); 790 break; 791 case 0x0d: 792 s->log_dest = val >> 24; 793 break; 794 case 0x0e: 795 s->dest_mode = val >> 28; 796 break; 797 case 0x0f: 798 s->spurious_vec = val & 0x1ff; 799 apic_update_irq(s); 800 break; 801 case 0x10 ... 0x17: 802 case 0x18 ... 0x1f: 803 case 0x20 ... 0x27: 804 case 0x28: 805 break; 806 case 0x30: 807 s->icr[0] = val; 808 apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, 809 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), 810 (s->icr[0] >> 15) & 1); 811 break; 812 case 0x31: 813 s->icr[1] = val; 814 break; 815 case 0x32 ... 0x37: 816 { 817 int n = index - 0x32; 818 s->lvt[n] = val; 819 if (n == APIC_LVT_TIMER) { 820 apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 821 } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) { 822 apic_update_irq(s); 823 } 824 } 825 break; 826 case 0x38: 827 s->initial_count = val; 828 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 829 apic_timer_update(s, s->initial_count_load_time); 830 break; 831 case 0x39: 832 break; 833 case 0x3e: 834 { 835 int v; 836 s->divide_conf = val & 0xb; 837 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); 838 s->count_shift = (v + 1) & 7; 839 } 840 break; 841 default: 842 s->esr |= APIC_ESR_ILLEGAL_ADDRESS; 843 break; 844 } 845 } 846 847 static void apic_pre_save(APICCommonState *s) 848 { 849 apic_sync_vapic(s, SYNC_FROM_VAPIC); 850 } 851 852 static void apic_post_load(APICCommonState *s) 853 { 854 if (s->timer_expiry != -1) { 855 timer_mod(s->timer, s->timer_expiry); 856 } else { 857 timer_del(s->timer); 858 } 859 } 860 861 static const MemoryRegionOps apic_io_ops = { 862 .old_mmio = { 863 .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, 864 .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, 865 }, 866 .endianness = DEVICE_NATIVE_ENDIAN, 867 }; 868 869 static void apic_realize(DeviceState *dev, Error **errp) 870 { 871 APICCommonState *s = APIC_COMMON(dev); 872 873 memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi", 874 APIC_SPACE_SIZE); 875 876 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s); 877 local_apics[s->idx] = s; 878 879 msi_nonbroken = true; 880 } 881 882 static void apic_class_init(ObjectClass *klass, void *data) 883 { 884 APICCommonClass *k = APIC_COMMON_CLASS(klass); 885 886 k->realize = apic_realize; 887 k->set_base = apic_set_base; 888 k->set_tpr = apic_set_tpr; 889 k->get_tpr = apic_get_tpr; 890 k->vapic_base_update = apic_vapic_base_update; 891 k->external_nmi = apic_external_nmi; 892 k->pre_save = apic_pre_save; 893 k->post_load = apic_post_load; 894 } 895 896 static const TypeInfo apic_info = { 897 .name = "apic", 898 .instance_size = sizeof(APICCommonState), 899 .parent = TYPE_APIC_COMMON, 900 .class_init = apic_class_init, 901 }; 902 903 static void apic_register_types(void) 904 { 905 type_register_static(&apic_info); 906 } 907 908 type_init(apic_register_types) 909