1 /* 2 * APIC support 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/> 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "qemu/thread.h" 23 #include "hw/i386/apic_internal.h" 24 #include "hw/i386/apic.h" 25 #include "hw/i386/ioapic.h" 26 #include "hw/pci/msi.h" 27 #include "qemu/host-utils.h" 28 #include "trace.h" 29 #include "hw/i386/pc.h" 30 #include "hw/i386/apic-msidef.h" 31 #include "qapi/error.h" 32 33 #define MAX_APICS 255 34 #define MAX_APIC_WORDS 8 35 36 #define SYNC_FROM_VAPIC 0x1 37 #define SYNC_TO_VAPIC 0x2 38 #define SYNC_ISR_IRR_TO_VAPIC 0x4 39 40 static APICCommonState *local_apics[MAX_APICS + 1]; 41 42 #define TYPE_APIC "apic" 43 #define APIC(obj) \ 44 OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC) 45 46 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); 47 static void apic_update_irq(APICCommonState *s); 48 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 49 uint8_t dest, uint8_t dest_mode); 50 51 /* Find first bit starting from msb */ 52 static int apic_fls_bit(uint32_t value) 53 { 54 return 31 - clz32(value); 55 } 56 57 /* Find first bit starting from lsb */ 58 static int apic_ffs_bit(uint32_t value) 59 { 60 return ctz32(value); 61 } 62 63 static inline void apic_reset_bit(uint32_t *tab, int index) 64 { 65 int i, mask; 66 i = index >> 5; 67 mask = 1 << (index & 0x1f); 68 tab[i] &= ~mask; 69 } 70 71 /* return -1 if no bit is set */ 72 static int get_highest_priority_int(uint32_t *tab) 73 { 74 int i; 75 for (i = 7; i >= 0; i--) { 76 if (tab[i] != 0) { 77 return i * 32 + apic_fls_bit(tab[i]); 78 } 79 } 80 return -1; 81 } 82 83 static void apic_sync_vapic(APICCommonState *s, int sync_type) 84 { 85 VAPICState vapic_state; 86 size_t length; 87 off_t start; 88 int vector; 89 90 if (!s->vapic_paddr) { 91 return; 92 } 93 if (sync_type & SYNC_FROM_VAPIC) { 94 cpu_physical_memory_read(s->vapic_paddr, &vapic_state, 95 sizeof(vapic_state)); 96 s->tpr = vapic_state.tpr; 97 } 98 if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) { 99 start = offsetof(VAPICState, isr); 100 length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); 101 102 if (sync_type & SYNC_TO_VAPIC) { 103 assert(qemu_cpu_is_self(CPU(s->cpu))); 104 105 vapic_state.tpr = s->tpr; 106 vapic_state.enabled = 1; 107 start = 0; 108 length = sizeof(VAPICState); 109 } 110 111 vector = get_highest_priority_int(s->isr); 112 if (vector < 0) { 113 vector = 0; 114 } 115 vapic_state.isr = vector & 0xf0; 116 117 vapic_state.zero = 0; 118 119 vector = get_highest_priority_int(s->irr); 120 if (vector < 0) { 121 vector = 0; 122 } 123 vapic_state.irr = vector & 0xff; 124 125 cpu_physical_memory_write_rom(&address_space_memory, 126 s->vapic_paddr + start, 127 ((void *)&vapic_state) + start, length); 128 } 129 } 130 131 static void apic_vapic_base_update(APICCommonState *s) 132 { 133 apic_sync_vapic(s, SYNC_TO_VAPIC); 134 } 135 136 static void apic_local_deliver(APICCommonState *s, int vector) 137 { 138 uint32_t lvt = s->lvt[vector]; 139 int trigger_mode; 140 141 trace_apic_local_deliver(vector, (lvt >> 8) & 7); 142 143 if (lvt & APIC_LVT_MASKED) 144 return; 145 146 switch ((lvt >> 8) & 7) { 147 case APIC_DM_SMI: 148 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI); 149 break; 150 151 case APIC_DM_NMI: 152 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI); 153 break; 154 155 case APIC_DM_EXTINT: 156 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD); 157 break; 158 159 case APIC_DM_FIXED: 160 trigger_mode = APIC_TRIGGER_EDGE; 161 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && 162 (lvt & APIC_LVT_LEVEL_TRIGGER)) 163 trigger_mode = APIC_TRIGGER_LEVEL; 164 apic_set_irq(s, lvt & 0xff, trigger_mode); 165 } 166 } 167 168 void apic_deliver_pic_intr(DeviceState *dev, int level) 169 { 170 APICCommonState *s = APIC(dev); 171 172 if (level) { 173 apic_local_deliver(s, APIC_LVT_LINT0); 174 } else { 175 uint32_t lvt = s->lvt[APIC_LVT_LINT0]; 176 177 switch ((lvt >> 8) & 7) { 178 case APIC_DM_FIXED: 179 if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) 180 break; 181 apic_reset_bit(s->irr, lvt & 0xff); 182 /* fall through */ 183 case APIC_DM_EXTINT: 184 apic_update_irq(s); 185 break; 186 } 187 } 188 } 189 190 static void apic_external_nmi(APICCommonState *s) 191 { 192 apic_local_deliver(s, APIC_LVT_LINT1); 193 } 194 195 #define foreach_apic(apic, deliver_bitmask, code) \ 196 {\ 197 int __i, __j;\ 198 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ 199 uint32_t __mask = deliver_bitmask[__i];\ 200 if (__mask) {\ 201 for(__j = 0; __j < 32; __j++) {\ 202 if (__mask & (1U << __j)) {\ 203 apic = local_apics[__i * 32 + __j];\ 204 if (apic) {\ 205 code;\ 206 }\ 207 }\ 208 }\ 209 }\ 210 }\ 211 } 212 213 static void apic_bus_deliver(const uint32_t *deliver_bitmask, 214 uint8_t delivery_mode, uint8_t vector_num, 215 uint8_t trigger_mode) 216 { 217 APICCommonState *apic_iter; 218 219 switch (delivery_mode) { 220 case APIC_DM_LOWPRI: 221 /* XXX: search for focus processor, arbitration */ 222 { 223 int i, d; 224 d = -1; 225 for(i = 0; i < MAX_APIC_WORDS; i++) { 226 if (deliver_bitmask[i]) { 227 d = i * 32 + apic_ffs_bit(deliver_bitmask[i]); 228 break; 229 } 230 } 231 if (d >= 0) { 232 apic_iter = local_apics[d]; 233 if (apic_iter) { 234 apic_set_irq(apic_iter, vector_num, trigger_mode); 235 } 236 } 237 } 238 return; 239 240 case APIC_DM_FIXED: 241 break; 242 243 case APIC_DM_SMI: 244 foreach_apic(apic_iter, deliver_bitmask, 245 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI) 246 ); 247 return; 248 249 case APIC_DM_NMI: 250 foreach_apic(apic_iter, deliver_bitmask, 251 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI) 252 ); 253 return; 254 255 case APIC_DM_INIT: 256 /* normal INIT IPI sent to processors */ 257 foreach_apic(apic_iter, deliver_bitmask, 258 cpu_interrupt(CPU(apic_iter->cpu), 259 CPU_INTERRUPT_INIT) 260 ); 261 return; 262 263 case APIC_DM_EXTINT: 264 /* handled in I/O APIC code */ 265 break; 266 267 default: 268 return; 269 } 270 271 foreach_apic(apic_iter, deliver_bitmask, 272 apic_set_irq(apic_iter, vector_num, trigger_mode) ); 273 } 274 275 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, 276 uint8_t vector_num, uint8_t trigger_mode) 277 { 278 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 279 280 trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, 281 trigger_mode); 282 283 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 284 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 285 } 286 287 static void apic_set_base(APICCommonState *s, uint64_t val) 288 { 289 s->apicbase = (val & 0xfffff000) | 290 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); 291 /* if disabled, cannot be enabled again */ 292 if (!(val & MSR_IA32_APICBASE_ENABLE)) { 293 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; 294 cpu_clear_apic_feature(&s->cpu->env); 295 s->spurious_vec &= ~APIC_SV_ENABLE; 296 } 297 } 298 299 static void apic_set_tpr(APICCommonState *s, uint8_t val) 300 { 301 /* Updates from cr8 are ignored while the VAPIC is active */ 302 if (!s->vapic_paddr) { 303 s->tpr = val << 4; 304 apic_update_irq(s); 305 } 306 } 307 308 static uint8_t apic_get_tpr(APICCommonState *s) 309 { 310 apic_sync_vapic(s, SYNC_FROM_VAPIC); 311 return s->tpr >> 4; 312 } 313 314 int apic_get_ppr(APICCommonState *s) 315 { 316 int tpr, isrv, ppr; 317 318 tpr = (s->tpr >> 4); 319 isrv = get_highest_priority_int(s->isr); 320 if (isrv < 0) 321 isrv = 0; 322 isrv >>= 4; 323 if (tpr >= isrv) 324 ppr = s->tpr; 325 else 326 ppr = isrv << 4; 327 return ppr; 328 } 329 330 static int apic_get_arb_pri(APICCommonState *s) 331 { 332 /* XXX: arbitration */ 333 return 0; 334 } 335 336 337 /* 338 * <0 - low prio interrupt, 339 * 0 - no interrupt, 340 * >0 - interrupt number 341 */ 342 static int apic_irq_pending(APICCommonState *s) 343 { 344 int irrv, ppr; 345 346 if (!(s->spurious_vec & APIC_SV_ENABLE)) { 347 return 0; 348 } 349 350 irrv = get_highest_priority_int(s->irr); 351 if (irrv < 0) { 352 return 0; 353 } 354 ppr = apic_get_ppr(s); 355 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { 356 return -1; 357 } 358 359 return irrv; 360 } 361 362 /* signal the CPU if an irq is pending */ 363 static void apic_update_irq(APICCommonState *s) 364 { 365 CPUState *cpu; 366 DeviceState *dev = (DeviceState *)s; 367 368 cpu = CPU(s->cpu); 369 if (!qemu_cpu_is_self(cpu)) { 370 cpu_interrupt(cpu, CPU_INTERRUPT_POLL); 371 } else if (apic_irq_pending(s) > 0) { 372 cpu_interrupt(cpu, CPU_INTERRUPT_HARD); 373 } else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { 374 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); 375 } 376 } 377 378 void apic_poll_irq(DeviceState *dev) 379 { 380 APICCommonState *s = APIC(dev); 381 382 apic_sync_vapic(s, SYNC_FROM_VAPIC); 383 apic_update_irq(s); 384 } 385 386 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode) 387 { 388 apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num)); 389 390 apic_set_bit(s->irr, vector_num); 391 if (trigger_mode) 392 apic_set_bit(s->tmr, vector_num); 393 else 394 apic_reset_bit(s->tmr, vector_num); 395 if (s->vapic_paddr) { 396 apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC); 397 /* 398 * The vcpu thread needs to see the new IRR before we pull its current 399 * TPR value. That way, if we miss a lowering of the TRP, the guest 400 * has the chance to notice the new IRR and poll for IRQs on its own. 401 */ 402 smp_wmb(); 403 apic_sync_vapic(s, SYNC_FROM_VAPIC); 404 } 405 apic_update_irq(s); 406 } 407 408 static void apic_eoi(APICCommonState *s) 409 { 410 int isrv; 411 isrv = get_highest_priority_int(s->isr); 412 if (isrv < 0) 413 return; 414 apic_reset_bit(s->isr, isrv); 415 if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) { 416 ioapic_eoi_broadcast(isrv); 417 } 418 apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC); 419 apic_update_irq(s); 420 } 421 422 static int apic_find_dest(uint8_t dest) 423 { 424 APICCommonState *apic = local_apics[dest]; 425 int i; 426 427 if (apic && apic->id == dest) 428 return dest; /* shortcut in case apic->id == local_apics[dest]->id */ 429 430 for (i = 0; i < MAX_APICS; i++) { 431 apic = local_apics[i]; 432 if (apic && apic->id == dest) 433 return i; 434 if (!apic) 435 break; 436 } 437 438 return -1; 439 } 440 441 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 442 uint8_t dest, uint8_t dest_mode) 443 { 444 APICCommonState *apic_iter; 445 int i; 446 447 if (dest_mode == 0) { 448 if (dest == 0xff) { 449 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); 450 } else { 451 int idx = apic_find_dest(dest); 452 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 453 if (idx >= 0) 454 apic_set_bit(deliver_bitmask, idx); 455 } 456 } else { 457 /* XXX: cluster mode */ 458 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 459 for(i = 0; i < MAX_APICS; i++) { 460 apic_iter = local_apics[i]; 461 if (apic_iter) { 462 if (apic_iter->dest_mode == 0xf) { 463 if (dest & apic_iter->log_dest) 464 apic_set_bit(deliver_bitmask, i); 465 } else if (apic_iter->dest_mode == 0x0) { 466 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && 467 (dest & apic_iter->log_dest & 0x0f)) { 468 apic_set_bit(deliver_bitmask, i); 469 } 470 } 471 } else { 472 break; 473 } 474 } 475 } 476 } 477 478 static void apic_startup(APICCommonState *s, int vector_num) 479 { 480 s->sipi_vector = vector_num; 481 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); 482 } 483 484 void apic_sipi(DeviceState *dev) 485 { 486 APICCommonState *s = APIC(dev); 487 488 cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); 489 490 if (!s->wait_for_sipi) 491 return; 492 cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector); 493 s->wait_for_sipi = 0; 494 } 495 496 static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode, 497 uint8_t delivery_mode, uint8_t vector_num, 498 uint8_t trigger_mode) 499 { 500 APICCommonState *s = APIC(dev); 501 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 502 int dest_shorthand = (s->icr[0] >> 18) & 3; 503 APICCommonState *apic_iter; 504 505 switch (dest_shorthand) { 506 case 0: 507 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 508 break; 509 case 1: 510 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); 511 apic_set_bit(deliver_bitmask, s->id); 512 break; 513 case 2: 514 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 515 break; 516 case 3: 517 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 518 apic_reset_bit(deliver_bitmask, s->id); 519 break; 520 } 521 522 switch (delivery_mode) { 523 case APIC_DM_INIT: 524 { 525 int trig_mode = (s->icr[0] >> 15) & 1; 526 int level = (s->icr[0] >> 14) & 1; 527 if (level == 0 && trig_mode == 1) { 528 foreach_apic(apic_iter, deliver_bitmask, 529 apic_iter->arb_id = apic_iter->id ); 530 return; 531 } 532 } 533 break; 534 535 case APIC_DM_SIPI: 536 foreach_apic(apic_iter, deliver_bitmask, 537 apic_startup(apic_iter, vector_num) ); 538 return; 539 } 540 541 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 542 } 543 544 static bool apic_check_pic(APICCommonState *s) 545 { 546 DeviceState *dev = (DeviceState *)s; 547 548 if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { 549 return false; 550 } 551 apic_deliver_pic_intr(dev, 1); 552 return true; 553 } 554 555 int apic_get_interrupt(DeviceState *dev) 556 { 557 APICCommonState *s = APIC(dev); 558 int intno; 559 560 /* if the APIC is installed or enabled, we let the 8259 handle the 561 IRQs */ 562 if (!s) 563 return -1; 564 if (!(s->spurious_vec & APIC_SV_ENABLE)) 565 return -1; 566 567 apic_sync_vapic(s, SYNC_FROM_VAPIC); 568 intno = apic_irq_pending(s); 569 570 /* if there is an interrupt from the 8259, let the caller handle 571 * that first since ExtINT interrupts ignore the priority. 572 */ 573 if (intno == 0 || apic_check_pic(s)) { 574 apic_sync_vapic(s, SYNC_TO_VAPIC); 575 return -1; 576 } else if (intno < 0) { 577 apic_sync_vapic(s, SYNC_TO_VAPIC); 578 return s->spurious_vec & 0xff; 579 } 580 apic_reset_bit(s->irr, intno); 581 apic_set_bit(s->isr, intno); 582 apic_sync_vapic(s, SYNC_TO_VAPIC); 583 584 apic_update_irq(s); 585 586 return intno; 587 } 588 589 int apic_accept_pic_intr(DeviceState *dev) 590 { 591 APICCommonState *s = APIC(dev); 592 uint32_t lvt0; 593 594 if (!s) 595 return -1; 596 597 lvt0 = s->lvt[APIC_LVT_LINT0]; 598 599 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || 600 (lvt0 & APIC_LVT_MASKED) == 0) 601 return 1; 602 603 return 0; 604 } 605 606 static uint32_t apic_get_current_count(APICCommonState *s) 607 { 608 int64_t d; 609 uint32_t val; 610 d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >> 611 s->count_shift; 612 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { 613 /* periodic */ 614 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); 615 } else { 616 if (d >= s->initial_count) 617 val = 0; 618 else 619 val = s->initial_count - d; 620 } 621 return val; 622 } 623 624 static void apic_timer_update(APICCommonState *s, int64_t current_time) 625 { 626 if (apic_next_timer(s, current_time)) { 627 timer_mod(s->timer, s->next_time); 628 } else { 629 timer_del(s->timer); 630 } 631 } 632 633 static void apic_timer(void *opaque) 634 { 635 APICCommonState *s = opaque; 636 637 apic_local_deliver(s, APIC_LVT_TIMER); 638 apic_timer_update(s, s->next_time); 639 } 640 641 static uint32_t apic_mem_readb(void *opaque, hwaddr addr) 642 { 643 return 0; 644 } 645 646 static uint32_t apic_mem_readw(void *opaque, hwaddr addr) 647 { 648 return 0; 649 } 650 651 static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val) 652 { 653 } 654 655 static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val) 656 { 657 } 658 659 static uint32_t apic_mem_readl(void *opaque, hwaddr addr) 660 { 661 DeviceState *dev; 662 APICCommonState *s; 663 uint32_t val; 664 int index; 665 666 dev = cpu_get_current_apic(); 667 if (!dev) { 668 return 0; 669 } 670 s = APIC(dev); 671 672 index = (addr >> 4) & 0xff; 673 switch(index) { 674 case 0x02: /* id */ 675 val = s->id << 24; 676 break; 677 case 0x03: /* version */ 678 val = s->version | ((APIC_LVT_NB - 1) << 16); 679 break; 680 case 0x08: 681 apic_sync_vapic(s, SYNC_FROM_VAPIC); 682 if (apic_report_tpr_access) { 683 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ); 684 } 685 val = s->tpr; 686 break; 687 case 0x09: 688 val = apic_get_arb_pri(s); 689 break; 690 case 0x0a: 691 /* ppr */ 692 val = apic_get_ppr(s); 693 break; 694 case 0x0b: 695 val = 0; 696 break; 697 case 0x0d: 698 val = s->log_dest << 24; 699 break; 700 case 0x0e: 701 val = (s->dest_mode << 28) | 0xfffffff; 702 break; 703 case 0x0f: 704 val = s->spurious_vec; 705 break; 706 case 0x10 ... 0x17: 707 val = s->isr[index & 7]; 708 break; 709 case 0x18 ... 0x1f: 710 val = s->tmr[index & 7]; 711 break; 712 case 0x20 ... 0x27: 713 val = s->irr[index & 7]; 714 break; 715 case 0x28: 716 val = s->esr; 717 break; 718 case 0x30: 719 case 0x31: 720 val = s->icr[index & 1]; 721 break; 722 case 0x32 ... 0x37: 723 val = s->lvt[index - 0x32]; 724 break; 725 case 0x38: 726 val = s->initial_count; 727 break; 728 case 0x39: 729 val = apic_get_current_count(s); 730 break; 731 case 0x3e: 732 val = s->divide_conf; 733 break; 734 default: 735 s->esr |= APIC_ESR_ILLEGAL_ADDRESS; 736 val = 0; 737 break; 738 } 739 trace_apic_mem_readl(addr, val); 740 return val; 741 } 742 743 static void apic_send_msi(hwaddr addr, uint32_t data) 744 { 745 uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; 746 uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; 747 uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; 748 uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; 749 uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; 750 /* XXX: Ignore redirection hint. */ 751 apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); 752 } 753 754 static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val) 755 { 756 DeviceState *dev; 757 APICCommonState *s; 758 int index = (addr >> 4) & 0xff; 759 if (addr > 0xfff || !index) { 760 /* MSI and MMIO APIC are at the same memory location, 761 * but actually not on the global bus: MSI is on PCI bus 762 * APIC is connected directly to the CPU. 763 * Mapping them on the global bus happens to work because 764 * MSI registers are reserved in APIC MMIO and vice versa. */ 765 apic_send_msi(addr, val); 766 return; 767 } 768 769 dev = cpu_get_current_apic(); 770 if (!dev) { 771 return; 772 } 773 s = APIC(dev); 774 775 trace_apic_mem_writel(addr, val); 776 777 switch(index) { 778 case 0x02: 779 s->id = (val >> 24); 780 break; 781 case 0x03: 782 break; 783 case 0x08: 784 if (apic_report_tpr_access) { 785 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE); 786 } 787 s->tpr = val; 788 apic_sync_vapic(s, SYNC_TO_VAPIC); 789 apic_update_irq(s); 790 break; 791 case 0x09: 792 case 0x0a: 793 break; 794 case 0x0b: /* EOI */ 795 apic_eoi(s); 796 break; 797 case 0x0d: 798 s->log_dest = val >> 24; 799 break; 800 case 0x0e: 801 s->dest_mode = val >> 28; 802 break; 803 case 0x0f: 804 s->spurious_vec = val & 0x1ff; 805 apic_update_irq(s); 806 break; 807 case 0x10 ... 0x17: 808 case 0x18 ... 0x1f: 809 case 0x20 ... 0x27: 810 case 0x28: 811 break; 812 case 0x30: 813 s->icr[0] = val; 814 apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, 815 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), 816 (s->icr[0] >> 15) & 1); 817 break; 818 case 0x31: 819 s->icr[1] = val; 820 break; 821 case 0x32 ... 0x37: 822 { 823 int n = index - 0x32; 824 s->lvt[n] = val; 825 if (n == APIC_LVT_TIMER) { 826 apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 827 } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) { 828 apic_update_irq(s); 829 } 830 } 831 break; 832 case 0x38: 833 s->initial_count = val; 834 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 835 apic_timer_update(s, s->initial_count_load_time); 836 break; 837 case 0x39: 838 break; 839 case 0x3e: 840 { 841 int v; 842 s->divide_conf = val & 0xb; 843 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); 844 s->count_shift = (v + 1) & 7; 845 } 846 break; 847 default: 848 s->esr |= APIC_ESR_ILLEGAL_ADDRESS; 849 break; 850 } 851 } 852 853 static void apic_pre_save(APICCommonState *s) 854 { 855 apic_sync_vapic(s, SYNC_FROM_VAPIC); 856 } 857 858 static void apic_post_load(APICCommonState *s) 859 { 860 if (s->timer_expiry != -1) { 861 timer_mod(s->timer, s->timer_expiry); 862 } else { 863 timer_del(s->timer); 864 } 865 } 866 867 static const MemoryRegionOps apic_io_ops = { 868 .old_mmio = { 869 .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, 870 .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, 871 }, 872 .endianness = DEVICE_NATIVE_ENDIAN, 873 }; 874 875 static void apic_realize(DeviceState *dev, Error **errp) 876 { 877 APICCommonState *s = APIC(dev); 878 879 if (s->id >= MAX_APICS) { 880 error_setg(errp, "%s initialization failed. APIC ID %d is invalid", 881 object_get_typename(OBJECT(dev)), s->id); 882 return; 883 } 884 885 memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi", 886 APIC_SPACE_SIZE); 887 888 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s); 889 local_apics[s->id] = s; 890 891 msi_nonbroken = true; 892 } 893 894 static void apic_unrealize(DeviceState *dev, Error **errp) 895 { 896 APICCommonState *s = APIC(dev); 897 898 timer_del(s->timer); 899 timer_free(s->timer); 900 local_apics[s->id] = NULL; 901 } 902 903 static void apic_class_init(ObjectClass *klass, void *data) 904 { 905 APICCommonClass *k = APIC_COMMON_CLASS(klass); 906 907 k->realize = apic_realize; 908 k->unrealize = apic_unrealize; 909 k->set_base = apic_set_base; 910 k->set_tpr = apic_set_tpr; 911 k->get_tpr = apic_get_tpr; 912 k->vapic_base_update = apic_vapic_base_update; 913 k->external_nmi = apic_external_nmi; 914 k->pre_save = apic_pre_save; 915 k->post_load = apic_post_load; 916 } 917 918 static const TypeInfo apic_info = { 919 .name = TYPE_APIC, 920 .instance_size = sizeof(APICCommonState), 921 .parent = TYPE_APIC_COMMON, 922 .class_init = apic_class_init, 923 }; 924 925 static void apic_register_types(void) 926 { 927 type_register_static(&apic_info); 928 } 929 930 type_init(apic_register_types) 931