xref: /openbmc/qemu/hw/intc/allwinner-a10-pic.c (revision db725815985654007ade0fd53590d613fd657208)
1 /*
2  * Allwinner A10 interrupt controller device emulation
3  *
4  * Copyright (C) 2013 Li Guang
5  * Written by Li Guang <lig.fnst@cn.fujitsu.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  */
17 
18 #include "qemu/osdep.h"
19 #include "hw/sysbus.h"
20 #include "migration/vmstate.h"
21 #include "sysemu/sysemu.h"
22 #include "hw/intc/allwinner-a10-pic.h"
23 #include "hw/irq.h"
24 #include "qemu/log.h"
25 #include "qemu/module.h"
26 
27 static void aw_a10_pic_update(AwA10PICState *s)
28 {
29     uint8_t i;
30     int irq = 0, fiq = 0, zeroes;
31 
32     s->vector = 0;
33 
34     for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
35         irq |= s->irq_pending[i] & ~s->mask[i];
36         fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];
37 
38         if (!s->vector) {
39             zeroes = ctz32(s->irq_pending[i] & ~s->mask[i]);
40             if (zeroes != 32) {
41                 s->vector = (i * 32 + zeroes) * 4;
42             }
43         }
44     }
45 
46     qemu_set_irq(s->parent_irq, !!irq);
47     qemu_set_irq(s->parent_fiq, !!fiq);
48 }
49 
50 static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
51 {
52     AwA10PICState *s = opaque;
53 
54     if (level) {
55         set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
56     } else {
57         clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
58     }
59     aw_a10_pic_update(s);
60 }
61 
62 static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size)
63 {
64     AwA10PICState *s = opaque;
65     uint8_t index = (offset & 0xc) / 4;
66 
67     switch (offset) {
68     case AW_A10_PIC_VECTOR:
69         return s->vector;
70     case AW_A10_PIC_BASE_ADDR:
71         return s->base_addr;
72     case AW_A10_PIC_PROTECT:
73         return s->protect;
74     case AW_A10_PIC_NMI:
75         return s->nmi;
76     case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
77         return s->irq_pending[index];
78     case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
79         return s->fiq_pending[index];
80     case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
81         return s->select[index];
82     case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
83         return s->enable[index];
84     case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
85         return s->mask[index];
86     default:
87         qemu_log_mask(LOG_GUEST_ERROR,
88                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
89         break;
90     }
91 
92     return 0;
93 }
94 
95 static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
96                              unsigned size)
97 {
98     AwA10PICState *s = opaque;
99     uint8_t index = (offset & 0xc) / 4;
100 
101     switch (offset) {
102     case AW_A10_PIC_BASE_ADDR:
103         s->base_addr = value & ~0x3;
104         break;
105     case AW_A10_PIC_PROTECT:
106         s->protect = value;
107         break;
108     case AW_A10_PIC_NMI:
109         s->nmi = value;
110         break;
111     case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
112         /*
113          * The register is read-only; nevertheless, Linux (including
114          * the version originally shipped by Allwinner) pretends to
115          * write to the register. Just ignore it.
116          */
117         break;
118     case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
119         s->fiq_pending[index] &= ~value;
120         break;
121     case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
122         s->select[index] = value;
123         break;
124     case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
125         s->enable[index] = value;
126         break;
127     case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
128         s->mask[index] = value;
129         break;
130     default:
131         qemu_log_mask(LOG_GUEST_ERROR,
132                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
133         break;
134     }
135 
136     aw_a10_pic_update(s);
137 }
138 
139 static const MemoryRegionOps aw_a10_pic_ops = {
140     .read = aw_a10_pic_read,
141     .write = aw_a10_pic_write,
142     .endianness = DEVICE_NATIVE_ENDIAN,
143 };
144 
145 static const VMStateDescription vmstate_aw_a10_pic = {
146     .name = "a10.pic",
147     .version_id = 1,
148     .minimum_version_id = 1,
149     .fields = (VMStateField[]) {
150         VMSTATE_UINT32(vector, AwA10PICState),
151         VMSTATE_UINT32(base_addr, AwA10PICState),
152         VMSTATE_UINT32(protect, AwA10PICState),
153         VMSTATE_UINT32(nmi, AwA10PICState),
154         VMSTATE_UINT32_ARRAY(irq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
155         VMSTATE_UINT32_ARRAY(fiq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
156         VMSTATE_UINT32_ARRAY(enable, AwA10PICState, AW_A10_PIC_REG_NUM),
157         VMSTATE_UINT32_ARRAY(select, AwA10PICState, AW_A10_PIC_REG_NUM),
158         VMSTATE_UINT32_ARRAY(mask, AwA10PICState, AW_A10_PIC_REG_NUM),
159         VMSTATE_END_OF_LIST()
160     }
161 };
162 
163 static void aw_a10_pic_init(Object *obj)
164 {
165     AwA10PICState *s = AW_A10_PIC(obj);
166     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
167 
168      qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR);
169      sysbus_init_irq(dev, &s->parent_irq);
170      sysbus_init_irq(dev, &s->parent_fiq);
171      memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s,
172                            TYPE_AW_A10_PIC, 0x400);
173      sysbus_init_mmio(dev, &s->iomem);
174 }
175 
176 static void aw_a10_pic_reset(DeviceState *d)
177 {
178     AwA10PICState *s = AW_A10_PIC(d);
179     uint8_t i;
180 
181     s->base_addr = 0;
182     s->protect = 0;
183     s->nmi = 0;
184     s->vector = 0;
185     for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
186         s->irq_pending[i] = 0;
187         s->fiq_pending[i] = 0;
188         s->select[i] = 0;
189         s->enable[i] = 0;
190         s->mask[i] = 0;
191     }
192 }
193 
194 static void aw_a10_pic_class_init(ObjectClass *klass, void *data)
195 {
196     DeviceClass *dc = DEVICE_CLASS(klass);
197 
198     dc->reset = aw_a10_pic_reset;
199     dc->desc = "allwinner a10 pic";
200     dc->vmsd = &vmstate_aw_a10_pic;
201  }
202 
203 static const TypeInfo aw_a10_pic_info = {
204     .name = TYPE_AW_A10_PIC,
205     .parent = TYPE_SYS_BUS_DEVICE,
206     .instance_size = sizeof(AwA10PICState),
207     .instance_init = aw_a10_pic_init,
208     .class_init = aw_a10_pic_class_init,
209 };
210 
211 static void aw_a10_register_types(void)
212 {
213     type_register_static(&aw_a10_pic_info);
214 }
215 
216 type_init(aw_a10_register_types);
217