1 /* 2 * Allwinner A10 interrupt controller device emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/sysbus.h" 20 #include "hw/devices.h" 21 #include "sysemu/sysemu.h" 22 #include "hw/intc/allwinner-a10-pic.h" 23 #include "qemu/log.h" 24 25 static void aw_a10_pic_update(AwA10PICState *s) 26 { 27 uint8_t i; 28 int irq = 0, fiq = 0, zeroes; 29 30 s->vector = 0; 31 32 for (i = 0; i < AW_A10_PIC_REG_NUM; i++) { 33 irq |= s->irq_pending[i] & ~s->mask[i]; 34 fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i]; 35 36 if (!s->vector) { 37 zeroes = ctz32(s->irq_pending[i] & ~s->mask[i]); 38 if (zeroes != 32) { 39 s->vector = (i * 32 + zeroes) * 4; 40 } 41 } 42 } 43 44 qemu_set_irq(s->parent_irq, !!irq); 45 qemu_set_irq(s->parent_fiq, !!fiq); 46 } 47 48 static void aw_a10_pic_set_irq(void *opaque, int irq, int level) 49 { 50 AwA10PICState *s = opaque; 51 52 if (level) { 53 set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); 54 } else { 55 clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); 56 } 57 aw_a10_pic_update(s); 58 } 59 60 static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size) 61 { 62 AwA10PICState *s = opaque; 63 uint8_t index = (offset & 0xc) / 4; 64 65 switch (offset) { 66 case AW_A10_PIC_VECTOR: 67 return s->vector; 68 case AW_A10_PIC_BASE_ADDR: 69 return s->base_addr; 70 case AW_A10_PIC_PROTECT: 71 return s->protect; 72 case AW_A10_PIC_NMI: 73 return s->nmi; 74 case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8: 75 return s->irq_pending[index]; 76 case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8: 77 return s->fiq_pending[index]; 78 case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8: 79 return s->select[index]; 80 case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8: 81 return s->enable[index]; 82 case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8: 83 return s->mask[index]; 84 default: 85 qemu_log_mask(LOG_GUEST_ERROR, 86 "%s: Bad offset 0x%x\n", __func__, (int)offset); 87 break; 88 } 89 90 return 0; 91 } 92 93 static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value, 94 unsigned size) 95 { 96 AwA10PICState *s = opaque; 97 uint8_t index = (offset & 0xc) / 4; 98 99 switch (offset) { 100 case AW_A10_PIC_BASE_ADDR: 101 s->base_addr = value & ~0x3; 102 break; 103 case AW_A10_PIC_PROTECT: 104 s->protect = value; 105 break; 106 case AW_A10_PIC_NMI: 107 s->nmi = value; 108 break; 109 case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8: 110 /* 111 * The register is read-only; nevertheless, Linux (including 112 * the version originally shipped by Allwinner) pretends to 113 * write to the register. Just ignore it. 114 */ 115 break; 116 case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8: 117 s->fiq_pending[index] &= ~value; 118 break; 119 case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8: 120 s->select[index] = value; 121 break; 122 case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8: 123 s->enable[index] = value; 124 break; 125 case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8: 126 s->mask[index] = value; 127 break; 128 default: 129 qemu_log_mask(LOG_GUEST_ERROR, 130 "%s: Bad offset 0x%x\n", __func__, (int)offset); 131 break; 132 } 133 134 aw_a10_pic_update(s); 135 } 136 137 static const MemoryRegionOps aw_a10_pic_ops = { 138 .read = aw_a10_pic_read, 139 .write = aw_a10_pic_write, 140 .endianness = DEVICE_NATIVE_ENDIAN, 141 }; 142 143 static const VMStateDescription vmstate_aw_a10_pic = { 144 .name = "a10.pic", 145 .version_id = 1, 146 .minimum_version_id = 1, 147 .fields = (VMStateField[]) { 148 VMSTATE_UINT32(vector, AwA10PICState), 149 VMSTATE_UINT32(base_addr, AwA10PICState), 150 VMSTATE_UINT32(protect, AwA10PICState), 151 VMSTATE_UINT32(nmi, AwA10PICState), 152 VMSTATE_UINT32_ARRAY(irq_pending, AwA10PICState, AW_A10_PIC_REG_NUM), 153 VMSTATE_UINT32_ARRAY(fiq_pending, AwA10PICState, AW_A10_PIC_REG_NUM), 154 VMSTATE_UINT32_ARRAY(enable, AwA10PICState, AW_A10_PIC_REG_NUM), 155 VMSTATE_UINT32_ARRAY(select, AwA10PICState, AW_A10_PIC_REG_NUM), 156 VMSTATE_UINT32_ARRAY(mask, AwA10PICState, AW_A10_PIC_REG_NUM), 157 VMSTATE_END_OF_LIST() 158 } 159 }; 160 161 static void aw_a10_pic_init(Object *obj) 162 { 163 AwA10PICState *s = AW_A10_PIC(obj); 164 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 165 166 qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR); 167 sysbus_init_irq(dev, &s->parent_irq); 168 sysbus_init_irq(dev, &s->parent_fiq); 169 memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s, 170 TYPE_AW_A10_PIC, 0x400); 171 sysbus_init_mmio(dev, &s->iomem); 172 } 173 174 static void aw_a10_pic_reset(DeviceState *d) 175 { 176 AwA10PICState *s = AW_A10_PIC(d); 177 uint8_t i; 178 179 s->base_addr = 0; 180 s->protect = 0; 181 s->nmi = 0; 182 s->vector = 0; 183 for (i = 0; i < AW_A10_PIC_REG_NUM; i++) { 184 s->irq_pending[i] = 0; 185 s->fiq_pending[i] = 0; 186 s->select[i] = 0; 187 s->enable[i] = 0; 188 s->mask[i] = 0; 189 } 190 } 191 192 static void aw_a10_pic_class_init(ObjectClass *klass, void *data) 193 { 194 DeviceClass *dc = DEVICE_CLASS(klass); 195 196 dc->reset = aw_a10_pic_reset; 197 dc->desc = "allwinner a10 pic"; 198 dc->vmsd = &vmstate_aw_a10_pic; 199 } 200 201 static const TypeInfo aw_a10_pic_info = { 202 .name = TYPE_AW_A10_PIC, 203 .parent = TYPE_SYS_BUS_DEVICE, 204 .instance_size = sizeof(AwA10PICState), 205 .instance_init = aw_a10_pic_init, 206 .class_init = aw_a10_pic_class_init, 207 }; 208 209 static void aw_a10_register_types(void) 210 { 211 type_register_static(&aw_a10_pic_info); 212 } 213 214 type_init(aw_a10_register_types); 215