xref: /openbmc/qemu/hw/input/pl050.c (revision 6a0acfff)
1 /*
2  * Arm PrimeCell PL050 Keyboard / Mouse Interface
3  *
4  * Copyright (c) 2006-2007 CodeSourcery.
5  * Written by Paul Brook
6  *
7  * This code is licensed under the GPL.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "hw/sysbus.h"
12 #include "hw/input/ps2.h"
13 #include "hw/irq.h"
14 #include "qemu/log.h"
15 #include "qemu/module.h"
16 
17 #define TYPE_PL050 "pl050"
18 #define PL050(obj) OBJECT_CHECK(PL050State, (obj), TYPE_PL050)
19 
20 typedef struct PL050State {
21     SysBusDevice parent_obj;
22 
23     MemoryRegion iomem;
24     void *dev;
25     uint32_t cr;
26     uint32_t clk;
27     uint32_t last;
28     int pending;
29     qemu_irq irq;
30     bool is_mouse;
31 } PL050State;
32 
33 static const VMStateDescription vmstate_pl050 = {
34     .name = "pl050",
35     .version_id = 2,
36     .minimum_version_id = 2,
37     .fields = (VMStateField[]) {
38         VMSTATE_UINT32(cr, PL050State),
39         VMSTATE_UINT32(clk, PL050State),
40         VMSTATE_UINT32(last, PL050State),
41         VMSTATE_INT32(pending, PL050State),
42         VMSTATE_END_OF_LIST()
43     }
44 };
45 
46 #define PL050_TXEMPTY         (1 << 6)
47 #define PL050_TXBUSY          (1 << 5)
48 #define PL050_RXFULL          (1 << 4)
49 #define PL050_RXBUSY          (1 << 3)
50 #define PL050_RXPARITY        (1 << 2)
51 #define PL050_KMIC            (1 << 1)
52 #define PL050_KMID            (1 << 0)
53 
54 static const unsigned char pl050_id[] =
55 { 0x50, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
56 
57 static void pl050_update(void *opaque, int level)
58 {
59     PL050State *s = (PL050State *)opaque;
60     int raise;
61 
62     s->pending = level;
63     raise = (s->pending && (s->cr & 0x10) != 0)
64             || (s->cr & 0x08) != 0;
65     qemu_set_irq(s->irq, raise);
66 }
67 
68 static uint64_t pl050_read(void *opaque, hwaddr offset,
69                            unsigned size)
70 {
71     PL050State *s = (PL050State *)opaque;
72     if (offset >= 0xfe0 && offset < 0x1000)
73         return pl050_id[(offset - 0xfe0) >> 2];
74 
75     switch (offset >> 2) {
76     case 0: /* KMICR */
77         return s->cr;
78     case 1: /* KMISTAT */
79         {
80             uint8_t val;
81             uint32_t stat;
82 
83             val = s->last;
84             val = val ^ (val >> 4);
85             val = val ^ (val >> 2);
86             val = (val ^ (val >> 1)) & 1;
87 
88             stat = PL050_TXEMPTY;
89             if (val)
90                 stat |= PL050_RXPARITY;
91             if (s->pending)
92                 stat |= PL050_RXFULL;
93 
94             return stat;
95         }
96     case 2: /* KMIDATA */
97         if (s->pending)
98             s->last = ps2_read_data(s->dev);
99         return s->last;
100     case 3: /* KMICLKDIV */
101         return s->clk;
102     case 4: /* KMIIR */
103         return s->pending | 2;
104     default:
105         qemu_log_mask(LOG_GUEST_ERROR,
106                       "pl050_read: Bad offset %x\n", (int)offset);
107         return 0;
108     }
109 }
110 
111 static void pl050_write(void *opaque, hwaddr offset,
112                         uint64_t value, unsigned size)
113 {
114     PL050State *s = (PL050State *)opaque;
115     switch (offset >> 2) {
116     case 0: /* KMICR */
117         s->cr = value;
118         pl050_update(s, s->pending);
119         /* ??? Need to implement the enable/disable bit.  */
120         break;
121     case 2: /* KMIDATA */
122         /* ??? This should toggle the TX interrupt line.  */
123         /* ??? This means kbd/mouse can block each other.  */
124         if (s->is_mouse) {
125             ps2_write_mouse(s->dev, value);
126         } else {
127             ps2_write_keyboard(s->dev, value);
128         }
129         break;
130     case 3: /* KMICLKDIV */
131         s->clk = value;
132         return;
133     default:
134         qemu_log_mask(LOG_GUEST_ERROR,
135                       "pl050_write: Bad offset %x\n", (int)offset);
136     }
137 }
138 static const MemoryRegionOps pl050_ops = {
139     .read = pl050_read,
140     .write = pl050_write,
141     .endianness = DEVICE_NATIVE_ENDIAN,
142 };
143 
144 static void pl050_realize(DeviceState *dev, Error **errp)
145 {
146     PL050State *s = PL050(dev);
147     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
148 
149     memory_region_init_io(&s->iomem, OBJECT(s), &pl050_ops, s, "pl050", 0x1000);
150     sysbus_init_mmio(sbd, &s->iomem);
151     sysbus_init_irq(sbd, &s->irq);
152     if (s->is_mouse) {
153         s->dev = ps2_mouse_init(pl050_update, s);
154     } else {
155         s->dev = ps2_kbd_init(pl050_update, s);
156     }
157 }
158 
159 static void pl050_keyboard_init(Object *obj)
160 {
161     PL050State *s = PL050(obj);
162 
163     s->is_mouse = false;
164 }
165 
166 static void pl050_mouse_init(Object *obj)
167 {
168     PL050State *s = PL050(obj);
169 
170     s->is_mouse = true;
171 }
172 
173 static const TypeInfo pl050_kbd_info = {
174     .name          = "pl050_keyboard",
175     .parent        = TYPE_PL050,
176     .instance_init = pl050_keyboard_init,
177 };
178 
179 static const TypeInfo pl050_mouse_info = {
180     .name          = "pl050_mouse",
181     .parent        = TYPE_PL050,
182     .instance_init = pl050_mouse_init,
183 };
184 
185 static void pl050_class_init(ObjectClass *oc, void *data)
186 {
187     DeviceClass *dc = DEVICE_CLASS(oc);
188 
189     dc->realize = pl050_realize;
190     dc->vmsd = &vmstate_pl050;
191 }
192 
193 static const TypeInfo pl050_type_info = {
194     .name          = TYPE_PL050,
195     .parent        = TYPE_SYS_BUS_DEVICE,
196     .instance_size = sizeof(PL050State),
197     .abstract      = true,
198     .class_init    = pl050_class_init,
199 };
200 
201 static void pl050_register_types(void)
202 {
203     type_register_static(&pl050_type_info);
204     type_register_static(&pl050_kbd_info);
205     type_register_static(&pl050_mouse_info);
206 }
207 
208 type_init(pl050_register_types)
209