1 /* 2 * QEMU PC keyboard emulation 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/log.h" 27 #include "hw/isa/isa.h" 28 #include "migration/vmstate.h" 29 #include "hw/input/ps2.h" 30 #include "hw/irq.h" 31 #include "hw/input/i8042.h" 32 #include "sysemu/reset.h" 33 #include "sysemu/runstate.h" 34 35 #include "trace.h" 36 37 /* Keyboard Controller Commands */ 38 #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ 39 #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ 40 #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ 41 #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ 42 #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ 43 #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ 44 #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ 45 #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ 46 #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ 47 #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ 48 #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */ 49 #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */ 50 #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */ 51 #define KBD_CCMD_WRITE_OBUF 0xD2 52 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if 53 initiated by the auxiliary device */ 54 #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ 55 #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */ 56 #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */ 57 #define KBD_CCMD_PULSE_BITS_3_0 0xF0 /* Pulse bits 3-0 of the output port P2. */ 58 #define KBD_CCMD_RESET 0xFE /* Pulse bit 0 of the output port P2 = CPU reset. */ 59 #define KBD_CCMD_NO_OP 0xFF /* Pulse no bits of the output port P2. */ 60 61 /* Keyboard Commands */ 62 #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ 63 #define KBD_CMD_ECHO 0xEE 64 #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */ 65 #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ 66 #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ 67 #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */ 68 #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */ 69 #define KBD_CMD_RESET 0xFF /* Reset */ 70 71 /* Keyboard Replies */ 72 #define KBD_REPLY_POR 0xAA /* Power on reset */ 73 #define KBD_REPLY_ACK 0xFA /* Command ACK */ 74 #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ 75 76 /* Status Register Bits */ 77 #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ 78 #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ 79 #define KBD_STAT_SELFTEST 0x04 /* Self test successful */ 80 #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ 81 #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ 82 #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ 83 #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ 84 #define KBD_STAT_PERR 0x80 /* Parity error */ 85 86 /* Controller Mode Register Bits */ 87 #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ 88 #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ 89 #define KBD_MODE_SYS 0x04 /* The system flag (?) */ 90 #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ 91 #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ 92 #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ 93 #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ 94 #define KBD_MODE_RFU 0x80 95 96 /* Output Port Bits */ 97 #define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */ 98 #define KBD_OUT_A20 0x02 /* x86 only */ 99 #define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */ 100 #define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */ 101 102 /* OSes typically write 0xdd/0xdf to turn the A20 line off and on. 103 * We make the default value of the outport include these four bits, 104 * so that the subsection is rarely necessary. 105 */ 106 #define KBD_OUT_ONES 0xcc 107 108 /* Mouse Commands */ 109 #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */ 110 #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */ 111 #define AUX_SET_RES 0xE8 /* Set resolution */ 112 #define AUX_GET_SCALE 0xE9 /* Get scaling factor */ 113 #define AUX_SET_STREAM 0xEA /* Set stream mode */ 114 #define AUX_POLL 0xEB /* Poll */ 115 #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */ 116 #define AUX_SET_WRAP 0xEE /* Set wrap mode */ 117 #define AUX_SET_REMOTE 0xF0 /* Set remote mode */ 118 #define AUX_GET_TYPE 0xF2 /* Get type */ 119 #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */ 120 #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */ 121 #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */ 122 #define AUX_SET_DEFAULT 0xF6 123 #define AUX_RESET 0xFF /* Reset aux device */ 124 #define AUX_ACK 0xFA /* Command byte ACK. */ 125 126 #define MOUSE_STATUS_REMOTE 0x40 127 #define MOUSE_STATUS_ENABLED 0x20 128 #define MOUSE_STATUS_SCALE21 0x10 129 130 #define KBD_PENDING_KBD 1 131 #define KBD_PENDING_AUX 2 132 133 typedef struct KBDState { 134 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */ 135 uint8_t status; 136 uint8_t mode; 137 uint8_t outport; 138 bool outport_present; 139 /* Bitmask of devices with data available. */ 140 uint8_t pending; 141 void *kbd; 142 void *mouse; 143 144 qemu_irq irq_kbd; 145 qemu_irq irq_mouse; 146 qemu_irq a20_out; 147 hwaddr mask; 148 } KBDState; 149 150 /* update irq and KBD_STAT_[MOUSE_]OBF */ 151 /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be 152 incorrect, but it avoids having to simulate exact delays */ 153 static void kbd_update_irq(KBDState *s) 154 { 155 int irq_kbd_level, irq_mouse_level; 156 157 irq_kbd_level = 0; 158 irq_mouse_level = 0; 159 s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF); 160 s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF); 161 if (s->pending) { 162 s->status |= KBD_STAT_OBF; 163 s->outport |= KBD_OUT_OBF; 164 /* kbd data takes priority over aux data. */ 165 if (s->pending == KBD_PENDING_AUX) { 166 s->status |= KBD_STAT_MOUSE_OBF; 167 s->outport |= KBD_OUT_MOUSE_OBF; 168 if (s->mode & KBD_MODE_MOUSE_INT) 169 irq_mouse_level = 1; 170 } else { 171 if ((s->mode & KBD_MODE_KBD_INT) && 172 !(s->mode & KBD_MODE_DISABLE_KBD)) 173 irq_kbd_level = 1; 174 } 175 } 176 qemu_set_irq(s->irq_kbd, irq_kbd_level); 177 qemu_set_irq(s->irq_mouse, irq_mouse_level); 178 } 179 180 static void kbd_update_kbd_irq(void *opaque, int level) 181 { 182 KBDState *s = (KBDState *)opaque; 183 184 if (level) 185 s->pending |= KBD_PENDING_KBD; 186 else 187 s->pending &= ~KBD_PENDING_KBD; 188 kbd_update_irq(s); 189 } 190 191 static void kbd_update_aux_irq(void *opaque, int level) 192 { 193 KBDState *s = (KBDState *)opaque; 194 195 if (level) 196 s->pending |= KBD_PENDING_AUX; 197 else 198 s->pending &= ~KBD_PENDING_AUX; 199 kbd_update_irq(s); 200 } 201 202 static uint64_t kbd_read_status(void *opaque, hwaddr addr, 203 unsigned size) 204 { 205 KBDState *s = opaque; 206 int val; 207 val = s->status; 208 trace_pckbd_kbd_read_status(val); 209 return val; 210 } 211 212 static void kbd_queue(KBDState *s, int b, int aux) 213 { 214 if (aux) 215 ps2_queue(s->mouse, b); 216 else 217 ps2_queue(s->kbd, b); 218 } 219 220 static void outport_write(KBDState *s, uint32_t val) 221 { 222 trace_pckbd_outport_write(val); 223 s->outport = val; 224 qemu_set_irq(s->a20_out, (val >> 1) & 1); 225 if (!(val & 1)) { 226 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 227 } 228 } 229 230 static void kbd_write_command(void *opaque, hwaddr addr, 231 uint64_t val, unsigned size) 232 { 233 KBDState *s = opaque; 234 235 trace_pckbd_kbd_write_command(val); 236 237 /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed 238 * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE 239 * command specify the output port bits to be pulsed. 240 * 0: Bit should be pulsed. 1: Bit should not be modified. 241 * The only useful version of this command is pulsing bit 0, 242 * which does a CPU reset. 243 */ 244 if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) { 245 if(!(val & 1)) 246 val = KBD_CCMD_RESET; 247 else 248 val = KBD_CCMD_NO_OP; 249 } 250 251 switch(val) { 252 case KBD_CCMD_READ_MODE: 253 kbd_queue(s, s->mode, 0); 254 break; 255 case KBD_CCMD_WRITE_MODE: 256 case KBD_CCMD_WRITE_OBUF: 257 case KBD_CCMD_WRITE_AUX_OBUF: 258 case KBD_CCMD_WRITE_MOUSE: 259 case KBD_CCMD_WRITE_OUTPORT: 260 s->write_cmd = val; 261 break; 262 case KBD_CCMD_MOUSE_DISABLE: 263 s->mode |= KBD_MODE_DISABLE_MOUSE; 264 break; 265 case KBD_CCMD_MOUSE_ENABLE: 266 s->mode &= ~KBD_MODE_DISABLE_MOUSE; 267 break; 268 case KBD_CCMD_TEST_MOUSE: 269 kbd_queue(s, 0x00, 0); 270 break; 271 case KBD_CCMD_SELF_TEST: 272 s->status |= KBD_STAT_SELFTEST; 273 kbd_queue(s, 0x55, 0); 274 break; 275 case KBD_CCMD_KBD_TEST: 276 kbd_queue(s, 0x00, 0); 277 break; 278 case KBD_CCMD_KBD_DISABLE: 279 s->mode |= KBD_MODE_DISABLE_KBD; 280 kbd_update_irq(s); 281 break; 282 case KBD_CCMD_KBD_ENABLE: 283 s->mode &= ~KBD_MODE_DISABLE_KBD; 284 kbd_update_irq(s); 285 break; 286 case KBD_CCMD_READ_INPORT: 287 kbd_queue(s, 0x80, 0); 288 break; 289 case KBD_CCMD_READ_OUTPORT: 290 kbd_queue(s, s->outport, 0); 291 break; 292 case KBD_CCMD_ENABLE_A20: 293 qemu_irq_raise(s->a20_out); 294 s->outport |= KBD_OUT_A20; 295 break; 296 case KBD_CCMD_DISABLE_A20: 297 qemu_irq_lower(s->a20_out); 298 s->outport &= ~KBD_OUT_A20; 299 break; 300 case KBD_CCMD_RESET: 301 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 302 break; 303 case KBD_CCMD_NO_OP: 304 /* ignore that */ 305 break; 306 default: 307 qemu_log_mask(LOG_GUEST_ERROR, 308 "unsupported keyboard cmd=0x%02" PRIx64 "\n", val); 309 break; 310 } 311 } 312 313 static uint64_t kbd_read_data(void *opaque, hwaddr addr, 314 unsigned size) 315 { 316 KBDState *s = opaque; 317 uint32_t val; 318 319 if (s->pending == KBD_PENDING_AUX) 320 val = ps2_read_data(s->mouse); 321 else 322 val = ps2_read_data(s->kbd); 323 324 trace_pckbd_kbd_read_data(val); 325 return val; 326 } 327 328 static void kbd_write_data(void *opaque, hwaddr addr, 329 uint64_t val, unsigned size) 330 { 331 KBDState *s = opaque; 332 333 trace_pckbd_kbd_write_data(val); 334 335 switch(s->write_cmd) { 336 case 0: 337 ps2_write_keyboard(s->kbd, val); 338 break; 339 case KBD_CCMD_WRITE_MODE: 340 s->mode = val; 341 ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0); 342 /* ??? */ 343 kbd_update_irq(s); 344 break; 345 case KBD_CCMD_WRITE_OBUF: 346 kbd_queue(s, val, 0); 347 break; 348 case KBD_CCMD_WRITE_AUX_OBUF: 349 kbd_queue(s, val, 1); 350 break; 351 case KBD_CCMD_WRITE_OUTPORT: 352 outport_write(s, val); 353 break; 354 case KBD_CCMD_WRITE_MOUSE: 355 ps2_write_mouse(s->mouse, val); 356 break; 357 default: 358 break; 359 } 360 s->write_cmd = 0; 361 } 362 363 static void kbd_reset(void *opaque) 364 { 365 KBDState *s = opaque; 366 367 s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT; 368 s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED; 369 s->outport = KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES; 370 s->outport_present = false; 371 } 372 373 static uint8_t kbd_outport_default(KBDState *s) 374 { 375 return KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES 376 | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0) 377 | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0); 378 } 379 380 static int kbd_outport_post_load(void *opaque, int version_id) 381 { 382 KBDState *s = opaque; 383 s->outport_present = true; 384 return 0; 385 } 386 387 static bool kbd_outport_needed(void *opaque) 388 { 389 KBDState *s = opaque; 390 return s->outport != kbd_outport_default(s); 391 } 392 393 static const VMStateDescription vmstate_kbd_outport = { 394 .name = "pckbd_outport", 395 .version_id = 1, 396 .minimum_version_id = 1, 397 .post_load = kbd_outport_post_load, 398 .needed = kbd_outport_needed, 399 .fields = (VMStateField[]) { 400 VMSTATE_UINT8(outport, KBDState), 401 VMSTATE_END_OF_LIST() 402 } 403 }; 404 405 static int kbd_post_load(void *opaque, int version_id) 406 { 407 KBDState *s = opaque; 408 if (!s->outport_present) { 409 s->outport = kbd_outport_default(s); 410 } 411 s->outport_present = false; 412 return 0; 413 } 414 415 static const VMStateDescription vmstate_kbd = { 416 .name = "pckbd", 417 .version_id = 3, 418 .minimum_version_id = 3, 419 .post_load = kbd_post_load, 420 .fields = (VMStateField[]) { 421 VMSTATE_UINT8(write_cmd, KBDState), 422 VMSTATE_UINT8(status, KBDState), 423 VMSTATE_UINT8(mode, KBDState), 424 VMSTATE_UINT8(pending, KBDState), 425 VMSTATE_END_OF_LIST() 426 }, 427 .subsections = (const VMStateDescription*[]) { 428 &vmstate_kbd_outport, 429 NULL 430 } 431 }; 432 433 /* Memory mapped interface */ 434 static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size) 435 { 436 KBDState *s = opaque; 437 438 if (addr & s->mask) 439 return kbd_read_status(s, 0, 1) & 0xff; 440 else 441 return kbd_read_data(s, 0, 1) & 0xff; 442 } 443 444 static void kbd_mm_writefn(void *opaque, hwaddr addr, 445 uint64_t value, unsigned size) 446 { 447 KBDState *s = opaque; 448 449 if (addr & s->mask) 450 kbd_write_command(s, 0, value & 0xff, 1); 451 else 452 kbd_write_data(s, 0, value & 0xff, 1); 453 } 454 455 456 static const MemoryRegionOps i8042_mmio_ops = { 457 .read = kbd_mm_readfn, 458 .write = kbd_mm_writefn, 459 .valid.min_access_size = 1, 460 .valid.max_access_size = 4, 461 .endianness = DEVICE_NATIVE_ENDIAN, 462 }; 463 464 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, 465 MemoryRegion *region, ram_addr_t size, 466 hwaddr mask) 467 { 468 KBDState *s = g_malloc0(sizeof(KBDState)); 469 470 s->irq_kbd = kbd_irq; 471 s->irq_mouse = mouse_irq; 472 s->mask = mask; 473 474 vmstate_register(NULL, 0, &vmstate_kbd, s); 475 476 memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size); 477 478 s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); 479 s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); 480 qemu_register_reset(kbd_reset, s); 481 } 482 483 #define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042) 484 485 typedef struct ISAKBDState { 486 ISADevice parent_obj; 487 488 KBDState kbd; 489 MemoryRegion io[2]; 490 } ISAKBDState; 491 492 void i8042_isa_mouse_fake_event(void *opaque) 493 { 494 ISADevice *dev = opaque; 495 ISAKBDState *isa = I8042(dev); 496 KBDState *s = &isa->kbd; 497 498 ps2_mouse_fake_event(s->mouse); 499 } 500 501 void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out) 502 { 503 qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, a20_out); 504 } 505 506 static const VMStateDescription vmstate_kbd_isa = { 507 .name = "pckbd", 508 .version_id = 3, 509 .minimum_version_id = 3, 510 .fields = (VMStateField[]) { 511 VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState), 512 VMSTATE_END_OF_LIST() 513 } 514 }; 515 516 static const MemoryRegionOps i8042_data_ops = { 517 .read = kbd_read_data, 518 .write = kbd_write_data, 519 .impl = { 520 .min_access_size = 1, 521 .max_access_size = 1, 522 }, 523 .endianness = DEVICE_LITTLE_ENDIAN, 524 }; 525 526 static const MemoryRegionOps i8042_cmd_ops = { 527 .read = kbd_read_status, 528 .write = kbd_write_command, 529 .impl = { 530 .min_access_size = 1, 531 .max_access_size = 1, 532 }, 533 .endianness = DEVICE_LITTLE_ENDIAN, 534 }; 535 536 static void i8042_initfn(Object *obj) 537 { 538 ISAKBDState *isa_s = I8042(obj); 539 KBDState *s = &isa_s->kbd; 540 541 memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s, 542 "i8042-data", 1); 543 memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s, 544 "i8042-cmd", 1); 545 546 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1); 547 } 548 549 static void i8042_realizefn(DeviceState *dev, Error **errp) 550 { 551 ISADevice *isadev = ISA_DEVICE(dev); 552 ISAKBDState *isa_s = I8042(dev); 553 KBDState *s = &isa_s->kbd; 554 555 isa_init_irq(isadev, &s->irq_kbd, 1); 556 isa_init_irq(isadev, &s->irq_mouse, 12); 557 558 isa_register_ioport(isadev, isa_s->io + 0, 0x60); 559 isa_register_ioport(isadev, isa_s->io + 1, 0x64); 560 561 s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); 562 s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); 563 qemu_register_reset(kbd_reset, s); 564 } 565 566 static void i8042_class_initfn(ObjectClass *klass, void *data) 567 { 568 DeviceClass *dc = DEVICE_CLASS(klass); 569 570 dc->realize = i8042_realizefn; 571 dc->vmsd = &vmstate_kbd_isa; 572 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 573 } 574 575 static const TypeInfo i8042_info = { 576 .name = TYPE_I8042, 577 .parent = TYPE_ISA_DEVICE, 578 .instance_size = sizeof(ISAKBDState), 579 .instance_init = i8042_initfn, 580 .class_init = i8042_class_initfn, 581 }; 582 583 static void i8042_register_types(void) 584 { 585 type_register_static(&i8042_info); 586 } 587 588 type_init(i8042_register_types) 589