1 /* 2 * QEMU PC keyboard emulation 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/isa/isa.h" 26 #include "hw/i386/pc.h" 27 #include "hw/input/ps2.h" 28 #include "sysemu/sysemu.h" 29 30 /* debug PC keyboard */ 31 //#define DEBUG_KBD 32 #ifdef DEBUG_KBD 33 #define DPRINTF(fmt, ...) \ 34 do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0) 35 #else 36 #define DPRINTF(fmt, ...) 37 #endif 38 39 /* Keyboard Controller Commands */ 40 #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ 41 #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ 42 #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ 43 #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ 44 #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ 45 #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ 46 #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ 47 #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ 48 #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ 49 #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ 50 #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */ 51 #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */ 52 #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */ 53 #define KBD_CCMD_WRITE_OBUF 0xD2 54 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if 55 initiated by the auxiliary device */ 56 #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ 57 #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */ 58 #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */ 59 #define KBD_CCMD_PULSE_BITS_3_0 0xF0 /* Pulse bits 3-0 of the output port P2. */ 60 #define KBD_CCMD_RESET 0xFE /* Pulse bit 0 of the output port P2 = CPU reset. */ 61 #define KBD_CCMD_NO_OP 0xFF /* Pulse no bits of the output port P2. */ 62 63 /* Keyboard Commands */ 64 #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ 65 #define KBD_CMD_ECHO 0xEE 66 #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */ 67 #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ 68 #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ 69 #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */ 70 #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */ 71 #define KBD_CMD_RESET 0xFF /* Reset */ 72 73 /* Keyboard Replies */ 74 #define KBD_REPLY_POR 0xAA /* Power on reset */ 75 #define KBD_REPLY_ACK 0xFA /* Command ACK */ 76 #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ 77 78 /* Status Register Bits */ 79 #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ 80 #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ 81 #define KBD_STAT_SELFTEST 0x04 /* Self test successful */ 82 #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ 83 #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ 84 #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ 85 #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ 86 #define KBD_STAT_PERR 0x80 /* Parity error */ 87 88 /* Controller Mode Register Bits */ 89 #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ 90 #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ 91 #define KBD_MODE_SYS 0x04 /* The system flag (?) */ 92 #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ 93 #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ 94 #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ 95 #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ 96 #define KBD_MODE_RFU 0x80 97 98 /* Output Port Bits */ 99 #define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */ 100 #define KBD_OUT_A20 0x02 /* x86 only */ 101 #define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */ 102 #define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */ 103 104 /* Mouse Commands */ 105 #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */ 106 #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */ 107 #define AUX_SET_RES 0xE8 /* Set resolution */ 108 #define AUX_GET_SCALE 0xE9 /* Get scaling factor */ 109 #define AUX_SET_STREAM 0xEA /* Set stream mode */ 110 #define AUX_POLL 0xEB /* Poll */ 111 #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */ 112 #define AUX_SET_WRAP 0xEE /* Set wrap mode */ 113 #define AUX_SET_REMOTE 0xF0 /* Set remote mode */ 114 #define AUX_GET_TYPE 0xF2 /* Get type */ 115 #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */ 116 #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */ 117 #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */ 118 #define AUX_SET_DEFAULT 0xF6 119 #define AUX_RESET 0xFF /* Reset aux device */ 120 #define AUX_ACK 0xFA /* Command byte ACK. */ 121 122 #define MOUSE_STATUS_REMOTE 0x40 123 #define MOUSE_STATUS_ENABLED 0x20 124 #define MOUSE_STATUS_SCALE21 0x10 125 126 #define KBD_PENDING_KBD 1 127 #define KBD_PENDING_AUX 2 128 129 typedef struct KBDState { 130 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */ 131 uint8_t status; 132 uint8_t mode; 133 uint8_t outport; 134 bool outport_present; 135 /* Bitmask of devices with data available. */ 136 uint8_t pending; 137 void *kbd; 138 void *mouse; 139 140 qemu_irq irq_kbd; 141 qemu_irq irq_mouse; 142 qemu_irq *a20_out; 143 hwaddr mask; 144 } KBDState; 145 146 /* update irq and KBD_STAT_[MOUSE_]OBF */ 147 /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be 148 incorrect, but it avoids having to simulate exact delays */ 149 static void kbd_update_irq(KBDState *s) 150 { 151 int irq_kbd_level, irq_mouse_level; 152 153 irq_kbd_level = 0; 154 irq_mouse_level = 0; 155 s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF); 156 s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF); 157 if (s->pending) { 158 s->status |= KBD_STAT_OBF; 159 s->outport |= KBD_OUT_OBF; 160 /* kbd data takes priority over aux data. */ 161 if (s->pending == KBD_PENDING_AUX) { 162 s->status |= KBD_STAT_MOUSE_OBF; 163 s->outport |= KBD_OUT_MOUSE_OBF; 164 if (s->mode & KBD_MODE_MOUSE_INT) 165 irq_mouse_level = 1; 166 } else { 167 if ((s->mode & KBD_MODE_KBD_INT) && 168 !(s->mode & KBD_MODE_DISABLE_KBD)) 169 irq_kbd_level = 1; 170 } 171 } 172 qemu_set_irq(s->irq_kbd, irq_kbd_level); 173 qemu_set_irq(s->irq_mouse, irq_mouse_level); 174 } 175 176 static void kbd_update_kbd_irq(void *opaque, int level) 177 { 178 KBDState *s = (KBDState *)opaque; 179 180 if (level) 181 s->pending |= KBD_PENDING_KBD; 182 else 183 s->pending &= ~KBD_PENDING_KBD; 184 kbd_update_irq(s); 185 } 186 187 static void kbd_update_aux_irq(void *opaque, int level) 188 { 189 KBDState *s = (KBDState *)opaque; 190 191 if (level) 192 s->pending |= KBD_PENDING_AUX; 193 else 194 s->pending &= ~KBD_PENDING_AUX; 195 kbd_update_irq(s); 196 } 197 198 static uint64_t kbd_read_status(void *opaque, hwaddr addr, 199 unsigned size) 200 { 201 KBDState *s = opaque; 202 int val; 203 val = s->status; 204 DPRINTF("kbd: read status=0x%02x\n", val); 205 return val; 206 } 207 208 static void kbd_queue(KBDState *s, int b, int aux) 209 { 210 if (aux) 211 ps2_queue(s->mouse, b); 212 else 213 ps2_queue(s->kbd, b); 214 } 215 216 static void outport_write(KBDState *s, uint32_t val) 217 { 218 DPRINTF("kbd: write outport=0x%02x\n", val); 219 s->outport = val; 220 if (s->a20_out) { 221 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 222 } 223 if (!(val & 1)) { 224 qemu_system_reset_request(); 225 } 226 } 227 228 static void kbd_write_command(void *opaque, hwaddr addr, 229 uint64_t val, unsigned size) 230 { 231 KBDState *s = opaque; 232 233 DPRINTF("kbd: write cmd=0x%02" PRIx64 "\n", val); 234 235 /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed 236 * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE 237 * command specify the output port bits to be pulsed. 238 * 0: Bit should be pulsed. 1: Bit should not be modified. 239 * The only useful version of this command is pulsing bit 0, 240 * which does a CPU reset. 241 */ 242 if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) { 243 if(!(val & 1)) 244 val = KBD_CCMD_RESET; 245 else 246 val = KBD_CCMD_NO_OP; 247 } 248 249 switch(val) { 250 case KBD_CCMD_READ_MODE: 251 kbd_queue(s, s->mode, 0); 252 break; 253 case KBD_CCMD_WRITE_MODE: 254 case KBD_CCMD_WRITE_OBUF: 255 case KBD_CCMD_WRITE_AUX_OBUF: 256 case KBD_CCMD_WRITE_MOUSE: 257 case KBD_CCMD_WRITE_OUTPORT: 258 s->write_cmd = val; 259 break; 260 case KBD_CCMD_MOUSE_DISABLE: 261 s->mode |= KBD_MODE_DISABLE_MOUSE; 262 break; 263 case KBD_CCMD_MOUSE_ENABLE: 264 s->mode &= ~KBD_MODE_DISABLE_MOUSE; 265 break; 266 case KBD_CCMD_TEST_MOUSE: 267 kbd_queue(s, 0x00, 0); 268 break; 269 case KBD_CCMD_SELF_TEST: 270 s->status |= KBD_STAT_SELFTEST; 271 kbd_queue(s, 0x55, 0); 272 break; 273 case KBD_CCMD_KBD_TEST: 274 kbd_queue(s, 0x00, 0); 275 break; 276 case KBD_CCMD_KBD_DISABLE: 277 s->mode |= KBD_MODE_DISABLE_KBD; 278 kbd_update_irq(s); 279 break; 280 case KBD_CCMD_KBD_ENABLE: 281 s->mode &= ~KBD_MODE_DISABLE_KBD; 282 kbd_update_irq(s); 283 break; 284 case KBD_CCMD_READ_INPORT: 285 kbd_queue(s, 0x80, 0); 286 break; 287 case KBD_CCMD_READ_OUTPORT: 288 kbd_queue(s, s->outport, 0); 289 break; 290 case KBD_CCMD_ENABLE_A20: 291 if (s->a20_out) { 292 qemu_irq_raise(*s->a20_out); 293 } 294 s->outport |= KBD_OUT_A20; 295 break; 296 case KBD_CCMD_DISABLE_A20: 297 if (s->a20_out) { 298 qemu_irq_lower(*s->a20_out); 299 } 300 s->outport &= ~KBD_OUT_A20; 301 break; 302 case KBD_CCMD_RESET: 303 qemu_system_reset_request(); 304 break; 305 case KBD_CCMD_NO_OP: 306 /* ignore that */ 307 break; 308 default: 309 fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", (int)val); 310 break; 311 } 312 } 313 314 static uint64_t kbd_read_data(void *opaque, hwaddr addr, 315 unsigned size) 316 { 317 KBDState *s = opaque; 318 uint32_t val; 319 320 if (s->pending == KBD_PENDING_AUX) 321 val = ps2_read_data(s->mouse); 322 else 323 val = ps2_read_data(s->kbd); 324 325 DPRINTF("kbd: read data=0x%02x\n", val); 326 return val; 327 } 328 329 static void kbd_write_data(void *opaque, hwaddr addr, 330 uint64_t val, unsigned size) 331 { 332 KBDState *s = opaque; 333 334 DPRINTF("kbd: write data=0x%02" PRIx64 "\n", val); 335 336 switch(s->write_cmd) { 337 case 0: 338 ps2_write_keyboard(s->kbd, val); 339 break; 340 case KBD_CCMD_WRITE_MODE: 341 s->mode = val; 342 ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0); 343 /* ??? */ 344 kbd_update_irq(s); 345 break; 346 case KBD_CCMD_WRITE_OBUF: 347 kbd_queue(s, val, 0); 348 break; 349 case KBD_CCMD_WRITE_AUX_OBUF: 350 kbd_queue(s, val, 1); 351 break; 352 case KBD_CCMD_WRITE_OUTPORT: 353 outport_write(s, val); 354 break; 355 case KBD_CCMD_WRITE_MOUSE: 356 ps2_write_mouse(s->mouse, val); 357 break; 358 default: 359 break; 360 } 361 s->write_cmd = 0; 362 } 363 364 static void kbd_reset(void *opaque) 365 { 366 KBDState *s = opaque; 367 368 s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT; 369 s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED; 370 s->outport = KBD_OUT_RESET | KBD_OUT_A20; 371 s->outport_present = false; 372 } 373 374 static uint8_t kbd_outport_default(KBDState *s) 375 { 376 return KBD_OUT_RESET | KBD_OUT_A20 377 | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0) 378 | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0); 379 } 380 381 static int kbd_outport_post_load(void *opaque, int version_id) 382 { 383 KBDState *s = opaque; 384 s->outport_present = true; 385 return 0; 386 } 387 388 static const VMStateDescription vmstate_kbd_outport = { 389 .name = "pckbd_outport", 390 .version_id = 1, 391 .minimum_version_id = 1, 392 .post_load = kbd_outport_post_load, 393 .fields = (VMStateField[]) { 394 VMSTATE_UINT8(outport, KBDState), 395 VMSTATE_END_OF_LIST() 396 } 397 }; 398 399 static bool kbd_outport_needed(void *opaque) 400 { 401 KBDState *s = opaque; 402 return s->outport != kbd_outport_default(s); 403 } 404 405 static int kbd_post_load(void *opaque, int version_id) 406 { 407 KBDState *s = opaque; 408 if (!s->outport_present) { 409 s->outport = kbd_outport_default(s); 410 } 411 s->outport_present = false; 412 return 0; 413 } 414 415 static const VMStateDescription vmstate_kbd = { 416 .name = "pckbd", 417 .version_id = 3, 418 .minimum_version_id = 3, 419 .post_load = kbd_post_load, 420 .fields = (VMStateField[]) { 421 VMSTATE_UINT8(write_cmd, KBDState), 422 VMSTATE_UINT8(status, KBDState), 423 VMSTATE_UINT8(mode, KBDState), 424 VMSTATE_UINT8(pending, KBDState), 425 VMSTATE_END_OF_LIST() 426 }, 427 .subsections = (VMStateSubsection[]) { 428 { 429 .vmsd = &vmstate_kbd_outport, 430 .needed = kbd_outport_needed, 431 }, 432 VMSTATE_END_OF_LIST() 433 } 434 }; 435 436 /* Memory mapped interface */ 437 static uint32_t kbd_mm_readb (void *opaque, hwaddr addr) 438 { 439 KBDState *s = opaque; 440 441 if (addr & s->mask) 442 return kbd_read_status(s, 0, 1) & 0xff; 443 else 444 return kbd_read_data(s, 0, 1) & 0xff; 445 } 446 447 static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value) 448 { 449 KBDState *s = opaque; 450 451 if (addr & s->mask) 452 kbd_write_command(s, 0, value & 0xff, 1); 453 else 454 kbd_write_data(s, 0, value & 0xff, 1); 455 } 456 457 static const MemoryRegionOps i8042_mmio_ops = { 458 .endianness = DEVICE_NATIVE_ENDIAN, 459 .old_mmio = { 460 .read = { kbd_mm_readb, kbd_mm_readb, kbd_mm_readb }, 461 .write = { kbd_mm_writeb, kbd_mm_writeb, kbd_mm_writeb }, 462 }, 463 }; 464 465 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, 466 MemoryRegion *region, ram_addr_t size, 467 hwaddr mask) 468 { 469 KBDState *s = g_malloc0(sizeof(KBDState)); 470 471 s->irq_kbd = kbd_irq; 472 s->irq_mouse = mouse_irq; 473 s->mask = mask; 474 475 vmstate_register(NULL, 0, &vmstate_kbd, s); 476 477 memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size); 478 479 s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); 480 s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); 481 qemu_register_reset(kbd_reset, s); 482 } 483 484 #define TYPE_I8042 "i8042" 485 #define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042) 486 487 typedef struct ISAKBDState { 488 ISADevice parent_obj; 489 490 KBDState kbd; 491 MemoryRegion io[2]; 492 } ISAKBDState; 493 494 void i8042_isa_mouse_fake_event(void *opaque) 495 { 496 ISADevice *dev = opaque; 497 ISAKBDState *isa = I8042(dev); 498 KBDState *s = &isa->kbd; 499 500 ps2_mouse_fake_event(s->mouse); 501 } 502 503 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out) 504 { 505 ISAKBDState *isa = I8042(dev); 506 KBDState *s = &isa->kbd; 507 508 s->a20_out = a20_out; 509 } 510 511 static const VMStateDescription vmstate_kbd_isa = { 512 .name = "pckbd", 513 .version_id = 3, 514 .minimum_version_id = 3, 515 .fields = (VMStateField[]) { 516 VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState), 517 VMSTATE_END_OF_LIST() 518 } 519 }; 520 521 static const MemoryRegionOps i8042_data_ops = { 522 .read = kbd_read_data, 523 .write = kbd_write_data, 524 .impl = { 525 .min_access_size = 1, 526 .max_access_size = 1, 527 }, 528 .endianness = DEVICE_LITTLE_ENDIAN, 529 }; 530 531 static const MemoryRegionOps i8042_cmd_ops = { 532 .read = kbd_read_status, 533 .write = kbd_write_command, 534 .impl = { 535 .min_access_size = 1, 536 .max_access_size = 1, 537 }, 538 .endianness = DEVICE_LITTLE_ENDIAN, 539 }; 540 541 static void i8042_initfn(Object *obj) 542 { 543 ISAKBDState *isa_s = I8042(obj); 544 KBDState *s = &isa_s->kbd; 545 546 memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s, 547 "i8042-data", 1); 548 memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s, 549 "i8042-cmd", 1); 550 } 551 552 static void i8042_realizefn(DeviceState *dev, Error **errp) 553 { 554 ISADevice *isadev = ISA_DEVICE(dev); 555 ISAKBDState *isa_s = I8042(dev); 556 KBDState *s = &isa_s->kbd; 557 558 isa_init_irq(isadev, &s->irq_kbd, 1); 559 isa_init_irq(isadev, &s->irq_mouse, 12); 560 561 isa_register_ioport(isadev, isa_s->io + 0, 0x60); 562 isa_register_ioport(isadev, isa_s->io + 1, 0x64); 563 564 s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); 565 s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); 566 qemu_register_reset(kbd_reset, s); 567 } 568 569 static void i8042_class_initfn(ObjectClass *klass, void *data) 570 { 571 DeviceClass *dc = DEVICE_CLASS(klass); 572 573 dc->realize = i8042_realizefn; 574 dc->vmsd = &vmstate_kbd_isa; 575 } 576 577 static const TypeInfo i8042_info = { 578 .name = TYPE_I8042, 579 .parent = TYPE_ISA_DEVICE, 580 .instance_size = sizeof(ISAKBDState), 581 .instance_init = i8042_initfn, 582 .class_init = i8042_class_initfn, 583 }; 584 585 static void i8042_register_types(void) 586 { 587 type_register_static(&i8042_info); 588 } 589 590 type_init(i8042_register_types) 591