1 /* 2 * QEMU HP Lasi PS/2 interface emulation 3 * 4 * Copyright (c) 2019 Sven Schnelle 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qemu/log.h" 26 #include "hw/qdev-properties.h" 27 #include "hw/sysbus.h" 28 #include "hw/input/ps2.h" 29 #include "hw/input/lasips2.h" 30 #include "exec/hwaddr.h" 31 #include "trace.h" 32 #include "exec/address-spaces.h" 33 #include "migration/vmstate.h" 34 #include "hw/irq.h" 35 #include "qapi/error.h" 36 37 38 static const VMStateDescription vmstate_lasips2 = { 39 .name = "lasips2", 40 .version_id = 0, 41 .minimum_version_id = 0, 42 .fields = (VMStateField[]) { 43 VMSTATE_UINT8(kbd.control, LASIPS2State), 44 VMSTATE_UINT8(kbd.id, LASIPS2State), 45 VMSTATE_BOOL(kbd.irq, LASIPS2State), 46 VMSTATE_UINT8(mouse.control, LASIPS2State), 47 VMSTATE_UINT8(mouse.id, LASIPS2State), 48 VMSTATE_BOOL(mouse.irq, LASIPS2State), 49 VMSTATE_END_OF_LIST() 50 } 51 }; 52 53 typedef enum { 54 REG_PS2_ID = 0, 55 REG_PS2_RCVDATA = 4, 56 REG_PS2_CONTROL = 8, 57 REG_PS2_STATUS = 12, 58 } lasips2_read_reg_t; 59 60 typedef enum { 61 REG_PS2_RESET = 0, 62 REG_PS2_XMTDATA = 4, 63 } lasips2_write_reg_t; 64 65 typedef enum { 66 LASIPS2_CONTROL_ENABLE = 0x01, 67 LASIPS2_CONTROL_LOOPBACK = 0x02, 68 LASIPS2_CONTROL_DIAG = 0x20, 69 LASIPS2_CONTROL_DATDIR = 0x40, 70 LASIPS2_CONTROL_CLKDIR = 0x80, 71 } lasips2_control_reg_t; 72 73 typedef enum { 74 LASIPS2_STATUS_RBNE = 0x01, 75 LASIPS2_STATUS_TBNE = 0x02, 76 LASIPS2_STATUS_TERR = 0x04, 77 LASIPS2_STATUS_PERR = 0x08, 78 LASIPS2_STATUS_CMPINTR = 0x10, 79 LASIPS2_STATUS_DATSHD = 0x40, 80 LASIPS2_STATUS_CLKSHD = 0x80, 81 } lasips2_status_reg_t; 82 83 static const char *lasips2_read_reg_name(uint64_t addr) 84 { 85 switch (addr & 0xc) { 86 case REG_PS2_ID: 87 return " PS2_ID"; 88 89 case REG_PS2_RCVDATA: 90 return " PS2_RCVDATA"; 91 92 case REG_PS2_CONTROL: 93 return " PS2_CONTROL"; 94 95 case REG_PS2_STATUS: 96 return " PS2_STATUS"; 97 98 default: 99 return ""; 100 } 101 } 102 103 static const char *lasips2_write_reg_name(uint64_t addr) 104 { 105 switch (addr & 0x0c) { 106 case REG_PS2_RESET: 107 return " PS2_RESET"; 108 109 case REG_PS2_XMTDATA: 110 return " PS2_XMTDATA"; 111 112 case REG_PS2_CONTROL: 113 return " PS2_CONTROL"; 114 115 default: 116 return ""; 117 } 118 } 119 120 static void lasips2_update_irq(LASIPS2State *s) 121 { 122 trace_lasips2_intr(s->kbd.irq | s->mouse.irq); 123 qemu_set_irq(s->irq, s->kbd.irq | s->mouse.irq); 124 } 125 126 static void lasips2_reg_write(void *opaque, hwaddr addr, uint64_t val, 127 unsigned size) 128 { 129 LASIPS2Port *port = opaque; 130 131 trace_lasips2_reg_write(size, port->id, addr, 132 lasips2_write_reg_name(addr), val); 133 134 switch (addr & 0xc) { 135 case REG_PS2_CONTROL: 136 port->control = val; 137 break; 138 139 case REG_PS2_XMTDATA: 140 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 141 port->buf = val; 142 port->irq = true; 143 port->loopback_rbne = true; 144 lasips2_update_irq(port->parent); 145 break; 146 } 147 148 if (port->id) { 149 ps2_write_mouse(port->dev, val); 150 } else { 151 ps2_write_keyboard(port->dev, val); 152 } 153 break; 154 155 case REG_PS2_RESET: 156 break; 157 158 default: 159 qemu_log_mask(LOG_UNIMP, "%s: unknown register 0x%02" HWADDR_PRIx "\n", 160 __func__, addr); 161 break; 162 } 163 } 164 165 static uint64_t lasips2_reg_read(void *opaque, hwaddr addr, unsigned size) 166 { 167 LASIPS2Port *port = opaque; 168 uint64_t ret = 0; 169 170 switch (addr & 0xc) { 171 case REG_PS2_ID: 172 ret = port->id; 173 break; 174 175 case REG_PS2_RCVDATA: 176 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 177 port->irq = false; 178 port->loopback_rbne = false; 179 lasips2_update_irq(port->parent); 180 ret = port->buf; 181 break; 182 } 183 184 ret = ps2_read_data(port->dev); 185 break; 186 187 case REG_PS2_CONTROL: 188 ret = port->control; 189 break; 190 191 case REG_PS2_STATUS: 192 ret = LASIPS2_STATUS_DATSHD | LASIPS2_STATUS_CLKSHD; 193 194 if (port->control & LASIPS2_CONTROL_DIAG) { 195 if (!(port->control & LASIPS2_CONTROL_DATDIR)) { 196 ret &= ~LASIPS2_STATUS_DATSHD; 197 } 198 199 if (!(port->control & LASIPS2_CONTROL_CLKDIR)) { 200 ret &= ~LASIPS2_STATUS_CLKSHD; 201 } 202 } 203 204 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 205 if (port->loopback_rbne) { 206 ret |= LASIPS2_STATUS_RBNE; 207 } 208 } else { 209 if (!ps2_queue_empty(port->dev)) { 210 ret |= LASIPS2_STATUS_RBNE; 211 } 212 } 213 214 if (port->parent->kbd.irq || port->parent->mouse.irq) { 215 ret |= LASIPS2_STATUS_CMPINTR; 216 } 217 break; 218 219 default: 220 qemu_log_mask(LOG_UNIMP, "%s: unknown register 0x%02" HWADDR_PRIx "\n", 221 __func__, addr); 222 break; 223 } 224 225 trace_lasips2_reg_read(size, port->id, addr, 226 lasips2_read_reg_name(addr), ret); 227 return ret; 228 } 229 230 static const MemoryRegionOps lasips2_reg_ops = { 231 .read = lasips2_reg_read, 232 .write = lasips2_reg_write, 233 .impl = { 234 .min_access_size = 1, 235 .max_access_size = 4, 236 }, 237 .endianness = DEVICE_NATIVE_ENDIAN, 238 }; 239 240 static void lasips2_set_kbd_irq(void *opaque, int n, int level) 241 { 242 LASIPS2State *s = LASIPS2(opaque); 243 LASIPS2Port *port = &s->kbd; 244 245 port->irq = level; 246 lasips2_update_irq(port->parent); 247 } 248 249 static void lasips2_set_mouse_irq(void *opaque, int n, int level) 250 { 251 LASIPS2State *s = LASIPS2(opaque); 252 LASIPS2Port *port = &s->mouse; 253 254 port->irq = level; 255 lasips2_update_irq(port->parent); 256 } 257 258 LASIPS2State *lasips2_initfn(hwaddr base, qemu_irq irq) 259 { 260 DeviceState *dev; 261 262 dev = qdev_new(TYPE_LASIPS2); 263 qdev_prop_set_uint64(dev, "base", base); 264 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 265 266 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); 267 268 return LASIPS2(dev); 269 } 270 271 static void lasips2_realize(DeviceState *dev, Error **errp) 272 { 273 LASIPS2State *s = LASIPS2(dev); 274 275 vmstate_register(NULL, s->base, &vmstate_lasips2, s); 276 277 s->kbd.dev = ps2_kbd_init(); 278 qdev_connect_gpio_out(DEVICE(s->kbd.dev), PS2_DEVICE_IRQ, 279 qdev_get_gpio_in_named(dev, "ps2-kbd-input-irq", 280 0)); 281 s->mouse.dev = ps2_mouse_init(); 282 qdev_connect_gpio_out(DEVICE(s->mouse.dev), PS2_DEVICE_IRQ, 283 qdev_get_gpio_in_named(dev, "ps2-mouse-input-irq", 284 0)); 285 } 286 287 static void lasips2_init(Object *obj) 288 { 289 LASIPS2State *s = LASIPS2(obj); 290 291 s->kbd.id = 0; 292 s->mouse.id = 1; 293 s->kbd.parent = s; 294 s->mouse.parent = s; 295 296 memory_region_init_io(&s->kbd.reg, obj, &lasips2_reg_ops, &s->kbd, 297 "lasips2-kbd", 0x100); 298 memory_region_init_io(&s->mouse.reg, obj, &lasips2_reg_ops, &s->mouse, 299 "lasips2-mouse", 0x100); 300 301 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->kbd.reg); 302 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mouse.reg); 303 304 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 305 306 qdev_init_gpio_in_named(DEVICE(obj), lasips2_set_kbd_irq, 307 "ps2-kbd-input-irq", 1); 308 qdev_init_gpio_in_named(DEVICE(obj), lasips2_set_mouse_irq, 309 "ps2-mouse-input-irq", 1); 310 } 311 312 static Property lasips2_properties[] = { 313 DEFINE_PROP_UINT64("base", LASIPS2State, base, UINT64_MAX), 314 DEFINE_PROP_END_OF_LIST(), 315 }; 316 317 static void lasips2_class_init(ObjectClass *klass, void *data) 318 { 319 DeviceClass *dc = DEVICE_CLASS(klass); 320 321 dc->realize = lasips2_realize; 322 device_class_set_props(dc, lasips2_properties); 323 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 324 } 325 326 static const TypeInfo lasips2_info = { 327 .name = TYPE_LASIPS2, 328 .parent = TYPE_SYS_BUS_DEVICE, 329 .instance_init = lasips2_init, 330 .instance_size = sizeof(LASIPS2State), 331 .class_init = lasips2_class_init, 332 }; 333 334 static void lasips2_register_types(void) 335 { 336 type_register_static(&lasips2_info); 337 } 338 339 type_init(lasips2_register_types) 340