1 /* 2 * QEMU HP Lasi PS/2 interface emulation 3 * 4 * Copyright (c) 2019 Sven Schnelle 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qemu/log.h" 26 #include "hw/qdev-properties.h" 27 #include "hw/input/ps2.h" 28 #include "hw/input/lasips2.h" 29 #include "exec/hwaddr.h" 30 #include "sysemu/sysemu.h" 31 #include "trace.h" 32 #include "exec/address-spaces.h" 33 #include "migration/vmstate.h" 34 #include "hw/irq.h" 35 36 37 struct LASIPS2State; 38 typedef struct LASIPS2Port { 39 struct LASIPS2State *parent; 40 MemoryRegion reg; 41 void *dev; 42 uint8_t id; 43 uint8_t control; 44 uint8_t buf; 45 bool loopback_rbne; 46 bool irq; 47 } LASIPS2Port; 48 49 typedef struct LASIPS2State { 50 LASIPS2Port kbd; 51 LASIPS2Port mouse; 52 qemu_irq irq; 53 } LASIPS2State; 54 55 static const VMStateDescription vmstate_lasips2 = { 56 .name = "lasips2", 57 .version_id = 0, 58 .minimum_version_id = 0, 59 .fields = (VMStateField[]) { 60 VMSTATE_UINT8(kbd.control, LASIPS2State), 61 VMSTATE_UINT8(kbd.id, LASIPS2State), 62 VMSTATE_BOOL(kbd.irq, LASIPS2State), 63 VMSTATE_UINT8(mouse.control, LASIPS2State), 64 VMSTATE_UINT8(mouse.id, LASIPS2State), 65 VMSTATE_BOOL(mouse.irq, LASIPS2State), 66 VMSTATE_END_OF_LIST() 67 } 68 }; 69 70 typedef enum { 71 REG_PS2_ID = 0, 72 REG_PS2_RCVDATA = 4, 73 REG_PS2_CONTROL = 8, 74 REG_PS2_STATUS = 12, 75 } lasips2_read_reg_t; 76 77 typedef enum { 78 REG_PS2_RESET = 0, 79 REG_PS2_XMTDATA = 4, 80 } lasips2_write_reg_t; 81 82 typedef enum { 83 LASIPS2_CONTROL_ENABLE = 0x01, 84 LASIPS2_CONTROL_LOOPBACK = 0x02, 85 LASIPS2_CONTROL_DIAG = 0x20, 86 LASIPS2_CONTROL_DATDIR = 0x40, 87 LASIPS2_CONTROL_CLKDIR = 0x80, 88 } lasips2_control_reg_t; 89 90 typedef enum { 91 LASIPS2_STATUS_RBNE = 0x01, 92 LASIPS2_STATUS_TBNE = 0x02, 93 LASIPS2_STATUS_TERR = 0x04, 94 LASIPS2_STATUS_PERR = 0x08, 95 LASIPS2_STATUS_CMPINTR = 0x10, 96 LASIPS2_STATUS_DATSHD = 0x40, 97 LASIPS2_STATUS_CLKSHD = 0x80, 98 } lasips2_status_reg_t; 99 100 static const char *artist_read_reg_name(uint64_t addr) 101 { 102 switch (addr & 0xc) { 103 case REG_PS2_ID: 104 return " PS2_ID"; 105 106 case REG_PS2_RCVDATA: 107 return " PS2_RCVDATA"; 108 109 case REG_PS2_CONTROL: 110 return " PS2_CONTROL"; 111 112 case REG_PS2_STATUS: 113 return " PS2_STATUS"; 114 115 default: 116 return ""; 117 } 118 } 119 120 static const char *artist_write_reg_name(uint64_t addr) 121 { 122 switch (addr & 0x0c) { 123 case REG_PS2_RESET: 124 return " PS2_RESET"; 125 126 case REG_PS2_XMTDATA: 127 return " PS2_XMTDATA"; 128 129 case REG_PS2_CONTROL: 130 return " PS2_CONTROL"; 131 132 default: 133 return ""; 134 } 135 } 136 137 static void lasips2_update_irq(LASIPS2State *s) 138 { 139 trace_lasips2_intr(s->kbd.irq | s->mouse.irq); 140 qemu_set_irq(s->irq, s->kbd.irq | s->mouse.irq); 141 } 142 143 static void lasips2_reg_write(void *opaque, hwaddr addr, uint64_t val, 144 unsigned size) 145 { 146 LASIPS2Port *port = opaque; 147 148 trace_lasips2_reg_write(size, port->id, addr, 149 artist_write_reg_name(addr), val); 150 151 switch (addr & 0xc) { 152 case REG_PS2_CONTROL: 153 port->control = val; 154 break; 155 156 case REG_PS2_XMTDATA: 157 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 158 port->buf = val; 159 port->irq = true; 160 port->loopback_rbne = true; 161 lasips2_update_irq(port->parent); 162 break; 163 } 164 165 if (port->id) { 166 ps2_write_mouse(port->dev, val); 167 } else { 168 ps2_write_keyboard(port->dev, val); 169 } 170 break; 171 172 case REG_PS2_RESET: 173 break; 174 175 default: 176 qemu_log_mask(LOG_UNIMP, "%s: unknown register 0x%02" HWADDR_PRIx "\n", 177 __func__, addr); 178 break; 179 } 180 } 181 182 static uint64_t lasips2_reg_read(void *opaque, hwaddr addr, unsigned size) 183 { 184 LASIPS2Port *port = opaque; 185 uint64_t ret = 0; 186 187 switch (addr & 0xc) { 188 case REG_PS2_ID: 189 ret = port->id; 190 break; 191 192 case REG_PS2_RCVDATA: 193 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 194 port->irq = false; 195 port->loopback_rbne = false; 196 lasips2_update_irq(port->parent); 197 ret = port->buf; 198 break; 199 } 200 201 ret = ps2_read_data(port->dev); 202 break; 203 204 case REG_PS2_CONTROL: 205 ret = port->control; 206 break; 207 208 case REG_PS2_STATUS: 209 210 ret = LASIPS2_STATUS_DATSHD | LASIPS2_STATUS_CLKSHD; 211 212 if (port->control & LASIPS2_CONTROL_DIAG) { 213 if (!(port->control & LASIPS2_CONTROL_DATDIR)) { 214 ret &= ~LASIPS2_STATUS_DATSHD; 215 } 216 217 if (!(port->control & LASIPS2_CONTROL_CLKDIR)) { 218 ret &= ~LASIPS2_STATUS_CLKSHD; 219 } 220 } 221 222 if (port->control & LASIPS2_CONTROL_LOOPBACK) { 223 if (port->loopback_rbne) { 224 ret |= LASIPS2_STATUS_RBNE; 225 } 226 } else { 227 if (!ps2_queue_empty(port->dev)) { 228 ret |= LASIPS2_STATUS_RBNE; 229 } 230 } 231 232 if (port->parent->kbd.irq || port->parent->mouse.irq) { 233 ret |= LASIPS2_STATUS_CMPINTR; 234 } 235 break; 236 237 default: 238 qemu_log_mask(LOG_UNIMP, "%s: unknown register 0x%02" HWADDR_PRIx "\n", 239 __func__, addr); 240 break; 241 } 242 trace_lasips2_reg_read(size, port->id, addr, 243 artist_read_reg_name(addr), ret); 244 245 return ret; 246 } 247 248 static const MemoryRegionOps lasips2_reg_ops = { 249 .read = lasips2_reg_read, 250 .write = lasips2_reg_write, 251 .impl = { 252 .min_access_size = 1, 253 .max_access_size = 4, 254 }, 255 .endianness = DEVICE_NATIVE_ENDIAN, 256 }; 257 258 static void ps2dev_update_irq(void *opaque, int level) 259 { 260 LASIPS2Port *port = opaque; 261 port->irq = level; 262 lasips2_update_irq(port->parent); 263 } 264 265 void lasips2_init(MemoryRegion *address_space, 266 hwaddr base, qemu_irq irq) 267 { 268 LASIPS2State *s; 269 270 s = g_malloc0(sizeof(LASIPS2State)); 271 272 s->irq = irq; 273 s->mouse.id = 1; 274 s->kbd.parent = s; 275 s->mouse.parent = s; 276 277 vmstate_register(NULL, base, &vmstate_lasips2, s); 278 279 s->kbd.dev = ps2_kbd_init(ps2dev_update_irq, &s->kbd); 280 s->mouse.dev = ps2_mouse_init(ps2dev_update_irq, &s->mouse); 281 282 memory_region_init_io(&s->kbd.reg, NULL, &lasips2_reg_ops, &s->kbd, 283 "lasips2-kbd", 0x100); 284 memory_region_add_subregion(address_space, base, &s->kbd.reg); 285 286 memory_region_init_io(&s->mouse.reg, NULL, &lasips2_reg_ops, &s->mouse, 287 "lasips2-mouse", 0x100); 288 memory_region_add_subregion(address_space, base + 0x100, &s->mouse.reg); 289 } 290