1 /* 2 * QEMU IDE Emulation: PCI VIA82C686B support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "qemu/osdep.h" 27 #include "hw/hw.h" 28 #include "hw/i386/pc.h" 29 #include "hw/pci/pci.h" 30 #include "hw/isa/isa.h" 31 #include "sysemu/block-backend.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/dma.h" 34 35 #include "hw/ide/pci.h" 36 37 static uint64_t bmdma_read(void *opaque, hwaddr addr, 38 unsigned size) 39 { 40 BMDMAState *bm = opaque; 41 uint32_t val; 42 43 if (size != 1) { 44 return ((uint64_t)1 << (size * 8)) - 1; 45 } 46 47 switch (addr & 3) { 48 case 0: 49 val = bm->cmd; 50 break; 51 case 2: 52 val = bm->status; 53 break; 54 default: 55 val = 0xff; 56 break; 57 } 58 #ifdef DEBUG_IDE 59 printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val); 60 #endif 61 return val; 62 } 63 64 static void bmdma_write(void *opaque, hwaddr addr, 65 uint64_t val, unsigned size) 66 { 67 BMDMAState *bm = opaque; 68 69 if (size != 1) { 70 return; 71 } 72 73 #ifdef DEBUG_IDE 74 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val); 75 #endif 76 switch (addr & 3) { 77 case 0: 78 bmdma_cmd_writeb(bm, val); 79 break; 80 case 2: 81 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 82 break; 83 default:; 84 } 85 } 86 87 static const MemoryRegionOps via_bmdma_ops = { 88 .read = bmdma_read, 89 .write = bmdma_write, 90 }; 91 92 static void bmdma_setup_bar(PCIIDEState *d) 93 { 94 int i; 95 96 memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16); 97 for(i = 0;i < 2; i++) { 98 BMDMAState *bm = &d->bmdma[i]; 99 100 memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm, 101 "via-bmdma", 4); 102 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 103 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 104 &bmdma_addr_ioport_ops, bm, "bmdma", 4); 105 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 106 } 107 } 108 109 static void via_reset(void *opaque) 110 { 111 PCIIDEState *d = opaque; 112 PCIDevice *pd = PCI_DEVICE(d); 113 uint8_t *pci_conf = pd->config; 114 int i; 115 116 for (i = 0; i < 2; i++) { 117 ide_bus_reset(&d->bus[i]); 118 } 119 120 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT); 121 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 122 PCI_STATUS_DEVSEL_MEDIUM); 123 124 pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0); 125 pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4); 126 pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170); 127 pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374); 128 pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */ 129 pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e); 130 131 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ 132 pci_set_long(pci_conf + 0x40, 0x0a090600); 133 /* IDE misc configuration 1/2/3 */ 134 pci_set_long(pci_conf + 0x44, 0x00c00068); 135 /* IDE Timing control */ 136 pci_set_long(pci_conf + 0x48, 0xa8a8a8a8); 137 /* IDE Address Setup Time */ 138 pci_set_long(pci_conf + 0x4c, 0x000000ff); 139 /* UltraDMA Extended Timing Control*/ 140 pci_set_long(pci_conf + 0x50, 0x07070707); 141 /* UltraDMA FIFO Control */ 142 pci_set_long(pci_conf + 0x54, 0x00000004); 143 /* IDE primary sector size */ 144 pci_set_long(pci_conf + 0x60, 0x00000200); 145 /* IDE secondary sector size */ 146 pci_set_long(pci_conf + 0x68, 0x00000200); 147 /* PCI PM Block */ 148 pci_set_long(pci_conf + 0xc0, 0x00020001); 149 } 150 151 static void vt82c686b_init_ports(PCIIDEState *d) { 152 static const struct { 153 int iobase; 154 int iobase2; 155 int isairq; 156 } port_info[] = { 157 {0x1f0, 0x3f6, 14}, 158 {0x170, 0x376, 15}, 159 }; 160 int i; 161 162 for (i = 0; i < 2; i++) { 163 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); 164 ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, 165 port_info[i].iobase2); 166 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); 167 168 bmdma_init(&d->bus[i], &d->bmdma[i], d); 169 d->bmdma[i].bus = &d->bus[i]; 170 ide_register_restart_cb(&d->bus[i]); 171 } 172 } 173 174 /* via ide func */ 175 static void vt82c686b_ide_realize(PCIDevice *dev, Error **errp) 176 { 177 PCIIDEState *d = PCI_IDE(dev); 178 uint8_t *pci_conf = dev->config; 179 180 pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */ 181 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 182 183 qemu_register_reset(via_reset, d); 184 bmdma_setup_bar(d); 185 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 186 187 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); 188 189 vt82c686b_init_ports(d); 190 } 191 192 static void vt82c686b_ide_exitfn(PCIDevice *dev) 193 { 194 PCIIDEState *d = PCI_IDE(dev); 195 unsigned i; 196 197 for (i = 0; i < 2; ++i) { 198 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 199 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 200 } 201 } 202 203 void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 204 { 205 PCIDevice *dev; 206 207 dev = pci_create_simple(bus, devfn, "via-ide"); 208 pci_ide_create_devs(dev, hd_table); 209 } 210 211 static void via_ide_class_init(ObjectClass *klass, void *data) 212 { 213 DeviceClass *dc = DEVICE_CLASS(klass); 214 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 215 216 k->realize = vt82c686b_ide_realize; 217 k->exit = vt82c686b_ide_exitfn; 218 k->vendor_id = PCI_VENDOR_ID_VIA; 219 k->device_id = PCI_DEVICE_ID_VIA_IDE; 220 k->revision = 0x06; 221 k->class_id = PCI_CLASS_STORAGE_IDE; 222 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 223 } 224 225 static const TypeInfo via_ide_info = { 226 .name = "via-ide", 227 .parent = TYPE_PCI_IDE, 228 .class_init = via_ide_class_init, 229 }; 230 231 static void via_ide_register_types(void) 232 { 233 type_register_static(&via_ide_info); 234 } 235 236 type_init(via_ide_register_types) 237