1 /* 2 * QEMU IDE Emulation: PCI VIA82C686B support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include <hw/hw.h> 27 #include <hw/pc.h> 28 #include <hw/pci.h> 29 #include <hw/isa.h> 30 #include "block.h" 31 #include "sysemu.h" 32 #include "dma.h" 33 34 #include <hw/ide/pci.h> 35 36 static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, 37 unsigned size) 38 { 39 BMDMAState *bm = opaque; 40 uint32_t val; 41 42 if (size != 1) { 43 return ((uint64_t)1 << (size * 8)) - 1; 44 } 45 46 switch (addr & 3) { 47 case 0: 48 val = bm->cmd; 49 break; 50 case 2: 51 val = bm->status; 52 break; 53 default: 54 val = 0xff; 55 break; 56 } 57 #ifdef DEBUG_IDE 58 printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val); 59 #endif 60 return val; 61 } 62 63 static void bmdma_write(void *opaque, target_phys_addr_t addr, 64 uint64_t val, unsigned size) 65 { 66 BMDMAState *bm = opaque; 67 68 if (size != 1) { 69 return; 70 } 71 72 #ifdef DEBUG_IDE 73 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val); 74 #endif 75 switch (addr & 3) { 76 case 0: 77 return bmdma_cmd_writeb(bm, val); 78 case 2: 79 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 80 break; 81 default:; 82 } 83 } 84 85 static const MemoryRegionOps via_bmdma_ops = { 86 .read = bmdma_read, 87 .write = bmdma_write, 88 }; 89 90 static void bmdma_setup_bar(PCIIDEState *d) 91 { 92 int i; 93 94 memory_region_init(&d->bmdma_bar, "via-bmdma-container", 16); 95 for(i = 0;i < 2; i++) { 96 BMDMAState *bm = &d->bmdma[i]; 97 98 memory_region_init_io(&bm->extra_io, &via_bmdma_ops, bm, 99 "via-bmdma", 4); 100 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 101 memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm, 102 "bmdma", 4); 103 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 104 } 105 } 106 107 static void via_reset(void *opaque) 108 { 109 PCIIDEState *d = opaque; 110 uint8_t *pci_conf = d->dev.config; 111 int i; 112 113 for (i = 0; i < 2; i++) { 114 ide_bus_reset(&d->bus[i]); 115 } 116 117 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT); 118 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 119 PCI_STATUS_DEVSEL_MEDIUM); 120 121 pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0); 122 pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4); 123 pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170); 124 pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374); 125 pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */ 126 pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e); 127 128 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ 129 pci_set_long(pci_conf + 0x40, 0x0a090600); 130 /* IDE misc configuration 1/2/3 */ 131 pci_set_long(pci_conf + 0x44, 0x00c00068); 132 /* IDE Timing control */ 133 pci_set_long(pci_conf + 0x48, 0xa8a8a8a8); 134 /* IDE Address Setup Time */ 135 pci_set_long(pci_conf + 0x4c, 0x000000ff); 136 /* UltraDMA Extended Timing Control*/ 137 pci_set_long(pci_conf + 0x50, 0x07070707); 138 /* UltraDMA FIFO Control */ 139 pci_set_long(pci_conf + 0x54, 0x00000004); 140 /* IDE primary sector size */ 141 pci_set_long(pci_conf + 0x60, 0x00000200); 142 /* IDE secondary sector size */ 143 pci_set_long(pci_conf + 0x68, 0x00000200); 144 /* PCI PM Block */ 145 pci_set_long(pci_conf + 0xc0, 0x00020001); 146 } 147 148 static void vt82c686b_init_ports(PCIIDEState *d) { 149 static const struct { 150 int iobase; 151 int iobase2; 152 int isairq; 153 } port_info[] = { 154 {0x1f0, 0x3f6, 14}, 155 {0x170, 0x376, 15}, 156 }; 157 int i; 158 159 for (i = 0; i < 2; i++) { 160 ide_bus_new(&d->bus[i], &d->dev.qdev, i); 161 ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, 162 port_info[i].iobase2); 163 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); 164 165 bmdma_init(&d->bus[i], &d->bmdma[i], d); 166 d->bmdma[i].bus = &d->bus[i]; 167 qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb, 168 &d->bmdma[i].dma); 169 } 170 } 171 172 /* via ide func */ 173 static int vt82c686b_ide_initfn(PCIDevice *dev) 174 { 175 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); 176 uint8_t *pci_conf = d->dev.config; 177 178 pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */ 179 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 180 181 qemu_register_reset(via_reset, d); 182 bmdma_setup_bar(d); 183 pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 184 185 vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d); 186 187 vt82c686b_init_ports(d); 188 189 return 0; 190 } 191 192 static int vt82c686b_ide_exitfn(PCIDevice *dev) 193 { 194 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); 195 unsigned i; 196 197 for (i = 0; i < 2; ++i) { 198 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 199 memory_region_destroy(&d->bmdma[i].extra_io); 200 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 201 memory_region_destroy(&d->bmdma[i].addr_ioport); 202 } 203 memory_region_destroy(&d->bmdma_bar); 204 205 return 0; 206 } 207 208 void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 209 { 210 PCIDevice *dev; 211 212 dev = pci_create_simple(bus, devfn, "via-ide"); 213 pci_ide_create_devs(dev, hd_table); 214 } 215 216 static void via_ide_class_init(ObjectClass *klass, void *data) 217 { 218 DeviceClass *dc = DEVICE_CLASS(klass); 219 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 220 221 k->init = vt82c686b_ide_initfn; 222 k->exit = vt82c686b_ide_exitfn; 223 k->vendor_id = PCI_VENDOR_ID_VIA; 224 k->device_id = PCI_DEVICE_ID_VIA_IDE; 225 k->revision = 0x06; 226 k->class_id = PCI_CLASS_STORAGE_IDE; 227 dc->no_user = 1; 228 } 229 230 static TypeInfo via_ide_info = { 231 .name = "via-ide", 232 .parent = TYPE_PCI_DEVICE, 233 .instance_size = sizeof(PCIIDEState), 234 .class_init = via_ide_class_init, 235 }; 236 237 static void via_ide_register_types(void) 238 { 239 type_register_static(&via_ide_info); 240 } 241 242 type_init(via_ide_register_types) 243