1 /* 2 * QEMU IDE Emulation: PCI VIA82C686B support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "qemu/osdep.h" 27 #include "hw/hw.h" 28 #include "hw/i386/pc.h" 29 #include "hw/pci/pci.h" 30 #include "hw/isa/isa.h" 31 #include "sysemu/block-backend.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/dma.h" 34 35 #include "hw/ide/pci.h" 36 #include "trace.h" 37 38 static uint64_t bmdma_read(void *opaque, hwaddr addr, 39 unsigned size) 40 { 41 BMDMAState *bm = opaque; 42 uint32_t val; 43 44 if (size != 1) { 45 return ((uint64_t)1 << (size * 8)) - 1; 46 } 47 48 switch (addr & 3) { 49 case 0: 50 val = bm->cmd; 51 break; 52 case 2: 53 val = bm->status; 54 break; 55 default: 56 val = 0xff; 57 break; 58 } 59 60 trace_bmdma_read_via(addr, val); 61 return val; 62 } 63 64 static void bmdma_write(void *opaque, hwaddr addr, 65 uint64_t val, unsigned size) 66 { 67 BMDMAState *bm = opaque; 68 69 if (size != 1) { 70 return; 71 } 72 73 trace_bmdma_write_via(addr, val); 74 switch (addr & 3) { 75 case 0: 76 bmdma_cmd_writeb(bm, val); 77 break; 78 case 2: 79 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 80 break; 81 default:; 82 } 83 } 84 85 static const MemoryRegionOps via_bmdma_ops = { 86 .read = bmdma_read, 87 .write = bmdma_write, 88 }; 89 90 static void bmdma_setup_bar(PCIIDEState *d) 91 { 92 int i; 93 94 memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16); 95 for(i = 0;i < 2; i++) { 96 BMDMAState *bm = &d->bmdma[i]; 97 98 memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm, 99 "via-bmdma", 4); 100 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 101 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 102 &bmdma_addr_ioport_ops, bm, "bmdma", 4); 103 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 104 } 105 } 106 107 static void via_reset(void *opaque) 108 { 109 PCIIDEState *d = opaque; 110 PCIDevice *pd = PCI_DEVICE(d); 111 uint8_t *pci_conf = pd->config; 112 int i; 113 114 for (i = 0; i < 2; i++) { 115 ide_bus_reset(&d->bus[i]); 116 } 117 118 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT); 119 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 120 PCI_STATUS_DEVSEL_MEDIUM); 121 122 pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0); 123 pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4); 124 pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170); 125 pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374); 126 pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */ 127 pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e); 128 129 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ 130 pci_set_long(pci_conf + 0x40, 0x0a090600); 131 /* IDE misc configuration 1/2/3 */ 132 pci_set_long(pci_conf + 0x44, 0x00c00068); 133 /* IDE Timing control */ 134 pci_set_long(pci_conf + 0x48, 0xa8a8a8a8); 135 /* IDE Address Setup Time */ 136 pci_set_long(pci_conf + 0x4c, 0x000000ff); 137 /* UltraDMA Extended Timing Control*/ 138 pci_set_long(pci_conf + 0x50, 0x07070707); 139 /* UltraDMA FIFO Control */ 140 pci_set_long(pci_conf + 0x54, 0x00000004); 141 /* IDE primary sector size */ 142 pci_set_long(pci_conf + 0x60, 0x00000200); 143 /* IDE secondary sector size */ 144 pci_set_long(pci_conf + 0x68, 0x00000200); 145 /* PCI PM Block */ 146 pci_set_long(pci_conf + 0xc0, 0x00020001); 147 } 148 149 static void vt82c686b_init_ports(PCIIDEState *d) { 150 static const struct { 151 int iobase; 152 int iobase2; 153 int isairq; 154 } port_info[] = { 155 {0x1f0, 0x3f6, 14}, 156 {0x170, 0x376, 15}, 157 }; 158 int i; 159 160 for (i = 0; i < 2; i++) { 161 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); 162 ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, 163 port_info[i].iobase2); 164 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); 165 166 bmdma_init(&d->bus[i], &d->bmdma[i], d); 167 d->bmdma[i].bus = &d->bus[i]; 168 ide_register_restart_cb(&d->bus[i]); 169 } 170 } 171 172 /* via ide func */ 173 static void vt82c686b_ide_realize(PCIDevice *dev, Error **errp) 174 { 175 PCIIDEState *d = PCI_IDE(dev); 176 uint8_t *pci_conf = dev->config; 177 178 pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */ 179 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 180 181 qemu_register_reset(via_reset, d); 182 bmdma_setup_bar(d); 183 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 184 185 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); 186 187 vt82c686b_init_ports(d); 188 } 189 190 static void vt82c686b_ide_exitfn(PCIDevice *dev) 191 { 192 PCIIDEState *d = PCI_IDE(dev); 193 unsigned i; 194 195 for (i = 0; i < 2; ++i) { 196 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 197 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 198 } 199 } 200 201 void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 202 { 203 PCIDevice *dev; 204 205 dev = pci_create_simple(bus, devfn, "via-ide"); 206 pci_ide_create_devs(dev, hd_table); 207 } 208 209 static void via_ide_class_init(ObjectClass *klass, void *data) 210 { 211 DeviceClass *dc = DEVICE_CLASS(klass); 212 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 213 214 k->realize = vt82c686b_ide_realize; 215 k->exit = vt82c686b_ide_exitfn; 216 k->vendor_id = PCI_VENDOR_ID_VIA; 217 k->device_id = PCI_DEVICE_ID_VIA_IDE; 218 k->revision = 0x06; 219 k->class_id = PCI_CLASS_STORAGE_IDE; 220 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 221 } 222 223 static const TypeInfo via_ide_info = { 224 .name = "via-ide", 225 .parent = TYPE_PCI_IDE, 226 .class_init = via_ide_class_init, 227 }; 228 229 static void via_ide_register_types(void) 230 { 231 type_register_static(&via_ide_info); 232 } 233 234 type_init(via_ide_register_types) 235