1 /* 2 * QEMU IDE Emulation: PCI VIA82C686B support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "qemu/osdep.h" 27 #include "hw/hw.h" 28 #include "hw/pci/pci.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/dma.h" 31 32 #include "hw/ide/pci.h" 33 #include "trace.h" 34 35 static uint64_t bmdma_read(void *opaque, hwaddr addr, 36 unsigned size) 37 { 38 BMDMAState *bm = opaque; 39 uint32_t val; 40 41 if (size != 1) { 42 return ((uint64_t)1 << (size * 8)) - 1; 43 } 44 45 switch (addr & 3) { 46 case 0: 47 val = bm->cmd; 48 break; 49 case 2: 50 val = bm->status; 51 break; 52 default: 53 val = 0xff; 54 break; 55 } 56 57 trace_bmdma_read_via(addr, val); 58 return val; 59 } 60 61 static void bmdma_write(void *opaque, hwaddr addr, 62 uint64_t val, unsigned size) 63 { 64 BMDMAState *bm = opaque; 65 66 if (size != 1) { 67 return; 68 } 69 70 trace_bmdma_write_via(addr, val); 71 switch (addr & 3) { 72 case 0: 73 bmdma_cmd_writeb(bm, val); 74 break; 75 case 2: 76 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 77 break; 78 default:; 79 } 80 } 81 82 static const MemoryRegionOps via_bmdma_ops = { 83 .read = bmdma_read, 84 .write = bmdma_write, 85 }; 86 87 static void bmdma_setup_bar(PCIIDEState *d) 88 { 89 int i; 90 91 memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16); 92 for(i = 0;i < 2; i++) { 93 BMDMAState *bm = &d->bmdma[i]; 94 95 memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm, 96 "via-bmdma", 4); 97 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 98 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 99 &bmdma_addr_ioport_ops, bm, "bmdma", 4); 100 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 101 } 102 } 103 104 static void via_reset(void *opaque) 105 { 106 PCIIDEState *d = opaque; 107 PCIDevice *pd = PCI_DEVICE(d); 108 uint8_t *pci_conf = pd->config; 109 int i; 110 111 for (i = 0; i < 2; i++) { 112 ide_bus_reset(&d->bus[i]); 113 } 114 115 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT); 116 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 117 PCI_STATUS_DEVSEL_MEDIUM); 118 119 pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0); 120 pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4); 121 pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170); 122 pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374); 123 pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */ 124 pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e); 125 126 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ 127 pci_set_long(pci_conf + 0x40, 0x0a090600); 128 /* IDE misc configuration 1/2/3 */ 129 pci_set_long(pci_conf + 0x44, 0x00c00068); 130 /* IDE Timing control */ 131 pci_set_long(pci_conf + 0x48, 0xa8a8a8a8); 132 /* IDE Address Setup Time */ 133 pci_set_long(pci_conf + 0x4c, 0x000000ff); 134 /* UltraDMA Extended Timing Control*/ 135 pci_set_long(pci_conf + 0x50, 0x07070707); 136 /* UltraDMA FIFO Control */ 137 pci_set_long(pci_conf + 0x54, 0x00000004); 138 /* IDE primary sector size */ 139 pci_set_long(pci_conf + 0x60, 0x00000200); 140 /* IDE secondary sector size */ 141 pci_set_long(pci_conf + 0x68, 0x00000200); 142 /* PCI PM Block */ 143 pci_set_long(pci_conf + 0xc0, 0x00020001); 144 } 145 146 static void vt82c686b_init_ports(PCIIDEState *d) { 147 static const struct { 148 int iobase; 149 int iobase2; 150 int isairq; 151 } port_info[] = { 152 {0x1f0, 0x3f6, 14}, 153 {0x170, 0x376, 15}, 154 }; 155 int i; 156 157 for (i = 0; i < 2; i++) { 158 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); 159 ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, 160 port_info[i].iobase2); 161 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); 162 163 bmdma_init(&d->bus[i], &d->bmdma[i], d); 164 d->bmdma[i].bus = &d->bus[i]; 165 ide_register_restart_cb(&d->bus[i]); 166 } 167 } 168 169 /* via ide func */ 170 static void vt82c686b_ide_realize(PCIDevice *dev, Error **errp) 171 { 172 PCIIDEState *d = PCI_IDE(dev); 173 uint8_t *pci_conf = dev->config; 174 175 pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */ 176 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 177 178 qemu_register_reset(via_reset, d); 179 bmdma_setup_bar(d); 180 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 181 182 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); 183 184 vt82c686b_init_ports(d); 185 } 186 187 static void vt82c686b_ide_exitfn(PCIDevice *dev) 188 { 189 PCIIDEState *d = PCI_IDE(dev); 190 unsigned i; 191 192 for (i = 0; i < 2; ++i) { 193 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 194 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 195 } 196 } 197 198 void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 199 { 200 PCIDevice *dev; 201 202 dev = pci_create_simple(bus, devfn, "via-ide"); 203 pci_ide_create_devs(dev, hd_table); 204 } 205 206 static void via_ide_class_init(ObjectClass *klass, void *data) 207 { 208 DeviceClass *dc = DEVICE_CLASS(klass); 209 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 210 211 k->realize = vt82c686b_ide_realize; 212 k->exit = vt82c686b_ide_exitfn; 213 k->vendor_id = PCI_VENDOR_ID_VIA; 214 k->device_id = PCI_DEVICE_ID_VIA_IDE; 215 k->revision = 0x06; 216 k->class_id = PCI_CLASS_STORAGE_IDE; 217 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 218 } 219 220 static const TypeInfo via_ide_info = { 221 .name = "via-ide", 222 .parent = TYPE_PCI_IDE, 223 .class_init = via_ide_class_init, 224 }; 225 226 static void via_ide_register_types(void) 227 { 228 type_register_static(&via_ide_info); 229 } 230 231 type_init(via_ide_register_types) 232