1 /* 2 * QEMU IDE Emulation: PCI VIA82C686B support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/pci/pci.h" 29 #include "migration/vmstate.h" 30 #include "qemu/module.h" 31 #include "sysemu/dma.h" 32 33 #include "hw/ide/pci.h" 34 #include "trace.h" 35 36 static uint64_t bmdma_read(void *opaque, hwaddr addr, 37 unsigned size) 38 { 39 BMDMAState *bm = opaque; 40 uint32_t val; 41 42 if (size != 1) { 43 return ((uint64_t)1 << (size * 8)) - 1; 44 } 45 46 switch (addr & 3) { 47 case 0: 48 val = bm->cmd; 49 break; 50 case 2: 51 val = bm->status; 52 break; 53 default: 54 val = 0xff; 55 break; 56 } 57 58 trace_bmdma_read_via(addr, val); 59 return val; 60 } 61 62 static void bmdma_write(void *opaque, hwaddr addr, 63 uint64_t val, unsigned size) 64 { 65 BMDMAState *bm = opaque; 66 67 if (size != 1) { 68 return; 69 } 70 71 trace_bmdma_write_via(addr, val); 72 switch (addr & 3) { 73 case 0: 74 bmdma_cmd_writeb(bm, val); 75 break; 76 case 2: 77 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 78 break; 79 default:; 80 } 81 } 82 83 static const MemoryRegionOps via_bmdma_ops = { 84 .read = bmdma_read, 85 .write = bmdma_write, 86 }; 87 88 static void bmdma_setup_bar(PCIIDEState *d) 89 { 90 int i; 91 92 memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16); 93 for(i = 0;i < 2; i++) { 94 BMDMAState *bm = &d->bmdma[i]; 95 96 memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm, 97 "via-bmdma", 4); 98 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 99 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 100 &bmdma_addr_ioport_ops, bm, "bmdma", 4); 101 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 102 } 103 } 104 105 static void via_ide_set_irq(void *opaque, int n, int level) 106 { 107 PCIDevice *d = PCI_DEVICE(opaque); 108 109 if (level) { 110 d->config[0x70 + n * 8] |= 0x80; 111 } else { 112 d->config[0x70 + n * 8] &= ~0x80; 113 } 114 115 level = (d->config[0x70] & 0x80) || (d->config[0x78] & 0x80); 116 n = pci_get_byte(d->config + PCI_INTERRUPT_LINE); 117 if (n) { 118 qemu_set_irq(isa_get_irq(NULL, n), level); 119 } 120 } 121 122 static void via_ide_reset(DeviceState *dev) 123 { 124 PCIIDEState *d = PCI_IDE(dev); 125 PCIDevice *pd = PCI_DEVICE(dev); 126 uint8_t *pci_conf = pd->config; 127 int i; 128 129 for (i = 0; i < 2; i++) { 130 ide_bus_reset(&d->bus[i]); 131 } 132 133 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_WAIT); 134 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 135 PCI_STATUS_DEVSEL_MEDIUM); 136 137 pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0); 138 pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4); 139 pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170); 140 pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374); 141 pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */ 142 pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e); 143 144 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ 145 pci_set_long(pci_conf + 0x40, 0x0a090600); 146 /* IDE misc configuration 1/2/3 */ 147 pci_set_long(pci_conf + 0x44, 0x00c00068); 148 /* IDE Timing control */ 149 pci_set_long(pci_conf + 0x48, 0xa8a8a8a8); 150 /* IDE Address Setup Time */ 151 pci_set_long(pci_conf + 0x4c, 0x000000ff); 152 /* UltraDMA Extended Timing Control*/ 153 pci_set_long(pci_conf + 0x50, 0x07070707); 154 /* UltraDMA FIFO Control */ 155 pci_set_long(pci_conf + 0x54, 0x00000004); 156 /* IDE primary sector size */ 157 pci_set_long(pci_conf + 0x60, 0x00000200); 158 /* IDE secondary sector size */ 159 pci_set_long(pci_conf + 0x68, 0x00000200); 160 /* PCI PM Block */ 161 pci_set_long(pci_conf + 0xc0, 0x00020001); 162 } 163 164 static void via_ide_realize(PCIDevice *dev, Error **errp) 165 { 166 PCIIDEState *d = PCI_IDE(dev); 167 uint8_t *pci_conf = dev->config; 168 int i; 169 170 pci_config_set_prog_interface(pci_conf, 0x8f); /* native PCI ATA mode */ 171 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 172 dev->wmask[PCI_INTERRUPT_LINE] = 0xf; 173 174 memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, 175 &d->bus[0], "via-ide0-data", 8); 176 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); 177 178 memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops, 179 &d->bus[0], "via-ide0-cmd", 4); 180 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]); 181 182 memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops, 183 &d->bus[1], "via-ide1-data", 8); 184 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]); 185 186 memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops, 187 &d->bus[1], "via-ide1-cmd", 4); 188 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); 189 190 bmdma_setup_bar(d); 191 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 192 193 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); 194 195 for (i = 0; i < 2; i++) { 196 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); 197 ide_init2(&d->bus[i], qemu_allocate_irq(via_ide_set_irq, d, i)); 198 199 bmdma_init(&d->bus[i], &d->bmdma[i], d); 200 d->bmdma[i].bus = &d->bus[i]; 201 ide_register_restart_cb(&d->bus[i]); 202 } 203 } 204 205 static void via_ide_exitfn(PCIDevice *dev) 206 { 207 PCIIDEState *d = PCI_IDE(dev); 208 unsigned i; 209 210 for (i = 0; i < 2; ++i) { 211 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 212 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 213 } 214 } 215 216 void via_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 217 { 218 PCIDevice *dev; 219 220 dev = pci_create_simple(bus, devfn, "via-ide"); 221 pci_ide_create_devs(dev, hd_table); 222 } 223 224 static void via_ide_class_init(ObjectClass *klass, void *data) 225 { 226 DeviceClass *dc = DEVICE_CLASS(klass); 227 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 228 229 dc->reset = via_ide_reset; 230 k->realize = via_ide_realize; 231 k->exit = via_ide_exitfn; 232 k->vendor_id = PCI_VENDOR_ID_VIA; 233 k->device_id = PCI_DEVICE_ID_VIA_IDE; 234 k->revision = 0x06; 235 k->class_id = PCI_CLASS_STORAGE_IDE; 236 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 237 } 238 239 static const TypeInfo via_ide_info = { 240 .name = "via-ide", 241 .parent = TYPE_PCI_IDE, 242 .class_init = via_ide_class_init, 243 }; 244 245 static void via_ide_register_types(void) 246 { 247 type_register_static(&via_ide_info); 248 } 249 250 type_init(via_ide_register_types) 251