1 /* 2 * QEMU SiI3112A PCI to Serial ATA Controller Emulation 3 * 4 * Copyright (C) 2017 BALATON Zoltan <balaton@eik.bme.hu> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 * 9 */ 10 11 /* For documentation on this and similar cards see: 12 * http://wiki.osdev.org/User:Quok/Silicon_Image_Datasheets 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/ide/pci.h" 17 #include "trace.h" 18 19 #define TYPE_SII3112_PCI "sii3112" 20 #define SII3112_PCI(obj) OBJECT_CHECK(SiI3112PCIState, (obj), \ 21 TYPE_SII3112_PCI) 22 23 typedef struct SiI3112Regs { 24 uint32_t confstat; 25 uint32_t scontrol; 26 uint16_t sien; 27 uint8_t swdata; 28 } SiI3112Regs; 29 30 typedef struct SiI3112PCIState { 31 PCIIDEState i; 32 MemoryRegion mmio; 33 SiI3112Regs regs[2]; 34 } SiI3112PCIState; 35 36 /* The sii3112_reg_read and sii3112_reg_write functions implement the 37 * Internal Register Space - BAR5 (section 6.7 of the data sheet). 38 */ 39 40 static uint64_t sii3112_reg_read(void *opaque, hwaddr addr, 41 unsigned int size) 42 { 43 SiI3112PCIState *d = opaque; 44 uint64_t val = 0; 45 46 switch (addr) { 47 case 0x00: 48 val = d->i.bmdma[0].cmd; 49 break; 50 case 0x01: 51 val = d->regs[0].swdata; 52 break; 53 case 0x02: 54 val = d->i.bmdma[0].status; 55 break; 56 case 0x03: 57 val = 0; 58 break; 59 case 0x04 ... 0x07: 60 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size); 61 break; 62 case 0x08: 63 val = d->i.bmdma[1].cmd; 64 break; 65 case 0x09: 66 val = d->regs[1].swdata; 67 break; 68 case 0x0a: 69 val = d->i.bmdma[1].status; 70 break; 71 case 0x0b: 72 val = 0; 73 break; 74 case 0x0c ... 0x0f: 75 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size); 76 break; 77 case 0x10: 78 val = d->i.bmdma[0].cmd; 79 val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/ 80 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/ 81 val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0); 82 val |= (uint32_t)d->i.bmdma[0].status << 16; 83 val |= (uint32_t)d->i.bmdma[1].status << 24; 84 break; 85 case 0x18: 86 val = d->i.bmdma[1].cmd; 87 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0); 88 val |= (uint32_t)d->i.bmdma[1].status << 16; 89 break; 90 case 0x80 ... 0x87: 91 if (size == 1) { 92 val = ide_ioport_read(&d->i.bus[0], addr - 0x80); 93 } else if (addr == 0x80) { 94 val = (size == 2) ? ide_data_readw(&d->i.bus[0], 0) : 95 ide_data_readl(&d->i.bus[0], 0); 96 } else { 97 val = (1ULL << (size * 8)) - 1; 98 } 99 break; 100 case 0x8a: 101 val = (size == 1) ? ide_status_read(&d->i.bus[0], 4) : 102 (1ULL << (size * 8)) - 1; 103 break; 104 case 0xa0: 105 val = d->regs[0].confstat; 106 break; 107 case 0xc0 ... 0xc7: 108 if (size == 1) { 109 val = ide_ioport_read(&d->i.bus[1], addr - 0xc0); 110 } else if (addr == 0xc0) { 111 val = (size == 2) ? ide_data_readw(&d->i.bus[1], 0) : 112 ide_data_readl(&d->i.bus[1], 0); 113 } else { 114 val = (1ULL << (size * 8)) - 1; 115 } 116 break; 117 case 0xca: 118 val = (size == 1) ? ide_status_read(&d->i.bus[0], 4) : 119 (1ULL << (size * 8)) - 1; 120 break; 121 case 0xe0: 122 val = d->regs[1].confstat; 123 break; 124 case 0x100: 125 val = d->regs[0].scontrol; 126 break; 127 case 0x104: 128 val = (d->i.bus[0].ifs[0].blk) ? 0x113 : 0; 129 break; 130 case 0x148: 131 val = (uint32_t)d->regs[0].sien << 16; 132 break; 133 case 0x180: 134 val = d->regs[1].scontrol; 135 break; 136 case 0x184: 137 val = (d->i.bus[1].ifs[0].blk) ? 0x113 : 0; 138 break; 139 case 0x1c8: 140 val = (uint32_t)d->regs[1].sien << 16; 141 break; 142 default: 143 val = 0; 144 } 145 trace_sii3112_read(size, addr, val); 146 return val; 147 } 148 149 static void sii3112_reg_write(void *opaque, hwaddr addr, 150 uint64_t val, unsigned int size) 151 { 152 SiI3112PCIState *d = opaque; 153 154 trace_sii3112_write(size, addr, val); 155 switch (addr) { 156 case 0x00: 157 case 0x10: 158 bmdma_cmd_writeb(&d->i.bmdma[0], val); 159 break; 160 case 0x01: 161 case 0x11: 162 d->regs[0].swdata = val & 0x3f; 163 break; 164 case 0x02: 165 case 0x12: 166 d->i.bmdma[0].status = (val & 0x60) | (d->i.bmdma[0].status & 1) | 167 (d->i.bmdma[0].status & ~val & 6); 168 break; 169 case 0x04 ... 0x07: 170 bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size); 171 break; 172 case 0x08: 173 case 0x18: 174 bmdma_cmd_writeb(&d->i.bmdma[1], val); 175 break; 176 case 0x09: 177 case 0x19: 178 d->regs[1].swdata = val & 0x3f; 179 break; 180 case 0x0a: 181 case 0x1a: 182 d->i.bmdma[1].status = (val & 0x60) | (d->i.bmdma[1].status & 1) | 183 (d->i.bmdma[1].status & ~val & 6); 184 break; 185 case 0x0c ... 0x0f: 186 bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size); 187 break; 188 case 0x80 ... 0x87: 189 if (size == 1) { 190 ide_ioport_write(&d->i.bus[0], addr - 0x80, val); 191 } else if (addr == 0x80) { 192 if (size == 2) { 193 ide_data_writew(&d->i.bus[0], 0, val); 194 } else { 195 ide_data_writel(&d->i.bus[0], 0, val); 196 } 197 } 198 break; 199 case 0x8a: 200 if (size == 1) { 201 ide_cmd_write(&d->i.bus[0], 4, val); 202 } 203 break; 204 case 0xc0 ... 0xc7: 205 if (size == 1) { 206 ide_ioport_write(&d->i.bus[1], addr - 0xc0, val); 207 } else if (addr == 0xc0) { 208 if (size == 2) { 209 ide_data_writew(&d->i.bus[1], 0, val); 210 } else { 211 ide_data_writel(&d->i.bus[1], 0, val); 212 } 213 } 214 break; 215 case 0xca: 216 if (size == 1) { 217 ide_cmd_write(&d->i.bus[1], 4, val); 218 } 219 break; 220 case 0x100: 221 d->regs[0].scontrol = val & 0xfff; 222 if (val & 1) { 223 ide_bus_reset(&d->i.bus[0]); 224 } 225 break; 226 case 0x148: 227 d->regs[0].sien = (val >> 16) & 0x3eed; 228 break; 229 case 0x180: 230 d->regs[1].scontrol = val & 0xfff; 231 if (val & 1) { 232 ide_bus_reset(&d->i.bus[1]); 233 } 234 break; 235 case 0x1c8: 236 d->regs[1].sien = (val >> 16) & 0x3eed; 237 break; 238 default: 239 val = 0; 240 } 241 } 242 243 static const MemoryRegionOps sii3112_reg_ops = { 244 .read = sii3112_reg_read, 245 .write = sii3112_reg_write, 246 .endianness = DEVICE_LITTLE_ENDIAN, 247 }; 248 249 /* the PCI irq level is the logical OR of the two channels */ 250 static void sii3112_update_irq(SiI3112PCIState *s) 251 { 252 int i, set = 0; 253 254 for (i = 0; i < 2; i++) { 255 set |= s->regs[i].confstat & (1UL << 11); 256 } 257 pci_set_irq(PCI_DEVICE(s), (set ? 1 : 0)); 258 } 259 260 static void sii3112_set_irq(void *opaque, int channel, int level) 261 { 262 SiI3112PCIState *s = opaque; 263 264 trace_sii3112_set_irq(channel, level); 265 if (level) { 266 s->regs[channel].confstat |= (1UL << 11); 267 } else { 268 s->regs[channel].confstat &= ~(1UL << 11); 269 } 270 271 sii3112_update_irq(s); 272 } 273 274 static void sii3112_reset(void *opaque) 275 { 276 SiI3112PCIState *s = opaque; 277 int i; 278 279 for (i = 0; i < 2; i++) { 280 s->regs[i].confstat = 0x6515 << 16; 281 ide_bus_reset(&s->i.bus[i]); 282 } 283 } 284 285 static void sii3112_pci_realize(PCIDevice *dev, Error **errp) 286 { 287 SiI3112PCIState *d = SII3112_PCI(dev); 288 PCIIDEState *s = PCI_IDE(dev); 289 MemoryRegion *mr; 290 qemu_irq *irq; 291 int i; 292 293 pci_config_set_interrupt_pin(dev->config, 1); 294 pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8); 295 296 /* BAR5 is in PCI memory space */ 297 memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d, 298 "sii3112.bar5", 0x200); 299 pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 300 301 /* BAR0-BAR4 are PCI I/O space aliases into BAR5 */ 302 mr = g_new(MemoryRegion, 1); 303 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80, 8); 304 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, mr); 305 mr = g_new(MemoryRegion, 1); 306 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88, 4); 307 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, mr); 308 mr = g_new(MemoryRegion, 1); 309 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0, 8); 310 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, mr); 311 mr = g_new(MemoryRegion, 1); 312 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8, 4); 313 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, mr); 314 mr = g_new(MemoryRegion, 1); 315 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16); 316 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, mr); 317 318 irq = qemu_allocate_irqs(sii3112_set_irq, d, 2); 319 for (i = 0; i < 2; i++) { 320 ide_bus_new(&s->bus[i], sizeof(s->bus[i]), DEVICE(dev), i, 1); 321 ide_init2(&s->bus[i], irq[i]); 322 323 bmdma_init(&s->bus[i], &s->bmdma[i], s); 324 s->bmdma[i].bus = &s->bus[i]; 325 ide_register_restart_cb(&s->bus[i]); 326 } 327 qemu_register_reset(sii3112_reset, s); 328 } 329 330 static void sii3112_pci_class_init(ObjectClass *klass, void *data) 331 { 332 DeviceClass *dc = DEVICE_CLASS(klass); 333 PCIDeviceClass *pd = PCI_DEVICE_CLASS(klass); 334 335 pd->vendor_id = 0x1095; 336 pd->device_id = 0x3112; 337 pd->class_id = PCI_CLASS_STORAGE_RAID; 338 pd->revision = 1; 339 pd->realize = sii3112_pci_realize; 340 dc->desc = "SiI3112A SATA controller"; 341 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 342 } 343 344 static const TypeInfo sii3112_pci_info = { 345 .name = TYPE_SII3112_PCI, 346 .parent = TYPE_PCI_IDE, 347 .instance_size = sizeof(SiI3112PCIState), 348 .class_init = sii3112_pci_class_init, 349 }; 350 351 static void sii3112_register_types(void) 352 { 353 type_register_static(&sii3112_pci_info); 354 } 355 356 type_init(sii3112_register_types) 357