1 /* 2 * QEMU SiI3112A PCI to Serial ATA Controller Emulation 3 * 4 * Copyright (C) 2017 BALATON Zoltan <balaton@eik.bme.hu> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 * 9 */ 10 11 /* For documentation on this and similar cards see: 12 * http://wiki.osdev.org/User:Quok/Silicon_Image_Datasheets 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/ide/pci.h" 17 #include "trace.h" 18 19 #define TYPE_SII3112_PCI "sii3112" 20 #define SII3112_PCI(obj) OBJECT_CHECK(SiI3112PCIState, (obj), \ 21 TYPE_SII3112_PCI) 22 23 typedef struct SiI3112Regs { 24 uint32_t confstat; 25 uint32_t scontrol; 26 uint16_t sien; 27 uint8_t swdata; 28 } SiI3112Regs; 29 30 typedef struct SiI3112PCIState { 31 PCIIDEState i; 32 MemoryRegion mmio; 33 SiI3112Regs regs[2]; 34 } SiI3112PCIState; 35 36 /* The sii3112_reg_read and sii3112_reg_write functions implement the 37 * Internal Register Space - BAR5 (section 6.7 of the data sheet). 38 */ 39 40 static uint64_t sii3112_reg_read(void *opaque, hwaddr addr, 41 unsigned int size) 42 { 43 SiI3112PCIState *d = opaque; 44 uint64_t val = 0; 45 46 switch (addr) { 47 case 0x00: 48 val = d->i.bmdma[0].cmd; 49 break; 50 case 0x01: 51 val = d->regs[0].swdata; 52 break; 53 case 0x02: 54 val = d->i.bmdma[0].status; 55 break; 56 case 0x03: 57 val = 0; 58 break; 59 case 0x04 ... 0x07: 60 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size); 61 break; 62 case 0x08: 63 val = d->i.bmdma[1].cmd; 64 break; 65 case 0x09: 66 val = d->regs[1].swdata; 67 break; 68 case 0x0a: 69 val = d->i.bmdma[1].status; 70 break; 71 case 0x0b: 72 val = 0; 73 break; 74 case 0x0c ... 0x0f: 75 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size); 76 break; 77 case 0x10: 78 val = d->i.bmdma[0].cmd; 79 val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/ 80 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/ 81 val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0); 82 val |= (uint32_t)d->i.bmdma[0].status << 16; 83 val |= (uint32_t)d->i.bmdma[1].status << 24; 84 break; 85 case 0x18: 86 val = d->i.bmdma[1].cmd; 87 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0); 88 val |= (uint32_t)d->i.bmdma[1].status << 16; 89 break; 90 case 0x80 ... 0x87: 91 val = pci_ide_data_le_ops.read(&d->i.bus[0], addr - 0x80, size); 92 break; 93 case 0x8a: 94 val = pci_ide_cmd_le_ops.read(&d->i.bus[0], 2, size); 95 break; 96 case 0xa0: 97 val = d->regs[0].confstat; 98 break; 99 case 0xc0 ... 0xc7: 100 val = pci_ide_data_le_ops.read(&d->i.bus[1], addr - 0xc0, size); 101 break; 102 case 0xca: 103 val = pci_ide_cmd_le_ops.read(&d->i.bus[1], 2, size); 104 break; 105 case 0xe0: 106 val = d->regs[1].confstat; 107 break; 108 case 0x100: 109 val = d->regs[0].scontrol; 110 break; 111 case 0x104: 112 val = (d->i.bus[0].ifs[0].blk) ? 0x113 : 0; 113 break; 114 case 0x148: 115 val = (uint32_t)d->regs[0].sien << 16; 116 break; 117 case 0x180: 118 val = d->regs[1].scontrol; 119 break; 120 case 0x184: 121 val = (d->i.bus[1].ifs[0].blk) ? 0x113 : 0; 122 break; 123 case 0x1c8: 124 val = (uint32_t)d->regs[1].sien << 16; 125 break; 126 default: 127 val = 0; 128 } 129 trace_sii3112_read(size, addr, val); 130 return val; 131 } 132 133 static void sii3112_reg_write(void *opaque, hwaddr addr, 134 uint64_t val, unsigned int size) 135 { 136 SiI3112PCIState *d = opaque; 137 138 trace_sii3112_write(size, addr, val); 139 switch (addr) { 140 case 0x00: 141 case 0x10: 142 bmdma_cmd_writeb(&d->i.bmdma[0], val); 143 break; 144 case 0x01: 145 case 0x11: 146 d->regs[0].swdata = val & 0x3f; 147 break; 148 case 0x02: 149 case 0x12: 150 d->i.bmdma[0].status = (val & 0x60) | (d->i.bmdma[0].status & 1) | 151 (d->i.bmdma[0].status & ~val & 6); 152 break; 153 case 0x04 ... 0x07: 154 bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size); 155 break; 156 case 0x08: 157 case 0x18: 158 bmdma_cmd_writeb(&d->i.bmdma[1], val); 159 break; 160 case 0x09: 161 case 0x19: 162 d->regs[1].swdata = val & 0x3f; 163 break; 164 case 0x0a: 165 case 0x1a: 166 d->i.bmdma[1].status = (val & 0x60) | (d->i.bmdma[1].status & 1) | 167 (d->i.bmdma[1].status & ~val & 6); 168 break; 169 case 0x0c ... 0x0f: 170 bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size); 171 break; 172 case 0x80 ... 0x87: 173 pci_ide_data_le_ops.write(&d->i.bus[0], addr - 0x80, val, size); 174 break; 175 case 0x8a: 176 pci_ide_cmd_le_ops.write(&d->i.bus[0], 2, val, size); 177 break; 178 case 0xc0 ... 0xc7: 179 pci_ide_data_le_ops.write(&d->i.bus[1], addr - 0xc0, val, size); 180 break; 181 case 0xca: 182 pci_ide_cmd_le_ops.write(&d->i.bus[1], 2, val, size); 183 break; 184 case 0x100: 185 d->regs[0].scontrol = val & 0xfff; 186 if (val & 1) { 187 ide_bus_reset(&d->i.bus[0]); 188 } 189 break; 190 case 0x148: 191 d->regs[0].sien = (val >> 16) & 0x3eed; 192 break; 193 case 0x180: 194 d->regs[1].scontrol = val & 0xfff; 195 if (val & 1) { 196 ide_bus_reset(&d->i.bus[1]); 197 } 198 break; 199 case 0x1c8: 200 d->regs[1].sien = (val >> 16) & 0x3eed; 201 break; 202 default: 203 val = 0; 204 } 205 } 206 207 static const MemoryRegionOps sii3112_reg_ops = { 208 .read = sii3112_reg_read, 209 .write = sii3112_reg_write, 210 .endianness = DEVICE_LITTLE_ENDIAN, 211 }; 212 213 /* the PCI irq level is the logical OR of the two channels */ 214 static void sii3112_update_irq(SiI3112PCIState *s) 215 { 216 int i, set = 0; 217 218 for (i = 0; i < 2; i++) { 219 set |= s->regs[i].confstat & (1UL << 11); 220 } 221 pci_set_irq(PCI_DEVICE(s), (set ? 1 : 0)); 222 } 223 224 static void sii3112_set_irq(void *opaque, int channel, int level) 225 { 226 SiI3112PCIState *s = opaque; 227 228 trace_sii3112_set_irq(channel, level); 229 if (level) { 230 s->regs[channel].confstat |= (1UL << 11); 231 } else { 232 s->regs[channel].confstat &= ~(1UL << 11); 233 } 234 235 sii3112_update_irq(s); 236 } 237 238 static void sii3112_reset(void *opaque) 239 { 240 SiI3112PCIState *s = opaque; 241 int i; 242 243 for (i = 0; i < 2; i++) { 244 s->regs[i].confstat = 0x6515 << 16; 245 ide_bus_reset(&s->i.bus[i]); 246 } 247 } 248 249 static void sii3112_pci_realize(PCIDevice *dev, Error **errp) 250 { 251 SiI3112PCIState *d = SII3112_PCI(dev); 252 PCIIDEState *s = PCI_IDE(dev); 253 MemoryRegion *mr; 254 qemu_irq *irq; 255 int i; 256 257 pci_config_set_interrupt_pin(dev->config, 1); 258 pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8); 259 260 /* BAR5 is in PCI memory space */ 261 memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d, 262 "sii3112.bar5", 0x200); 263 pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 264 265 /* BAR0-BAR4 are PCI I/O space aliases into BAR5 */ 266 mr = g_new(MemoryRegion, 1); 267 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80, 8); 268 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, mr); 269 mr = g_new(MemoryRegion, 1); 270 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88, 4); 271 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, mr); 272 mr = g_new(MemoryRegion, 1); 273 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0, 8); 274 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, mr); 275 mr = g_new(MemoryRegion, 1); 276 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8, 4); 277 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, mr); 278 mr = g_new(MemoryRegion, 1); 279 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16); 280 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, mr); 281 282 irq = qemu_allocate_irqs(sii3112_set_irq, d, 2); 283 for (i = 0; i < 2; i++) { 284 ide_bus_new(&s->bus[i], sizeof(s->bus[i]), DEVICE(dev), i, 1); 285 ide_init2(&s->bus[i], irq[i]); 286 287 bmdma_init(&s->bus[i], &s->bmdma[i], s); 288 s->bmdma[i].bus = &s->bus[i]; 289 ide_register_restart_cb(&s->bus[i]); 290 } 291 qemu_register_reset(sii3112_reset, s); 292 } 293 294 static void sii3112_pci_class_init(ObjectClass *klass, void *data) 295 { 296 DeviceClass *dc = DEVICE_CLASS(klass); 297 PCIDeviceClass *pd = PCI_DEVICE_CLASS(klass); 298 299 pd->vendor_id = 0x1095; 300 pd->device_id = 0x3112; 301 pd->class_id = PCI_CLASS_STORAGE_RAID; 302 pd->revision = 1; 303 pd->realize = sii3112_pci_realize; 304 dc->desc = "SiI3112A SATA controller"; 305 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 306 } 307 308 static const TypeInfo sii3112_pci_info = { 309 .name = TYPE_SII3112_PCI, 310 .parent = TYPE_PCI_IDE, 311 .instance_size = sizeof(SiI3112PCIState), 312 .class_init = sii3112_pci_class_init, 313 }; 314 315 static void sii3112_register_types(void) 316 { 317 type_register_static(&sii3112_pci_info); 318 } 319 320 type_init(sii3112_register_types) 321