1 /* 2 * QEMU SiI3112A PCI to Serial ATA Controller Emulation 3 * 4 * Copyright (C) 2017 BALATON Zoltan <balaton@eik.bme.hu> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 * 9 */ 10 11 /* For documentation on this and similar cards see: 12 * http://wiki.osdev.org/User:Quok/Silicon_Image_Datasheets 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/ide/pci.h" 17 #include "qemu/module.h" 18 #include "trace.h" 19 #include "qom/object.h" 20 21 #define TYPE_SII3112_PCI "sii3112" 22 OBJECT_DECLARE_SIMPLE_TYPE(SiI3112PCIState, SII3112_PCI) 23 24 typedef struct SiI3112Regs { 25 uint32_t confstat; 26 uint32_t scontrol; 27 uint16_t sien; 28 uint8_t swdata; 29 } SiI3112Regs; 30 31 struct SiI3112PCIState { 32 PCIIDEState i; 33 MemoryRegion mmio; 34 SiI3112Regs regs[2]; 35 }; 36 37 /* The sii3112_reg_read and sii3112_reg_write functions implement the 38 * Internal Register Space - BAR5 (section 6.7 of the data sheet). 39 */ 40 41 static uint64_t sii3112_reg_read(void *opaque, hwaddr addr, 42 unsigned int size) 43 { 44 SiI3112PCIState *d = opaque; 45 uint64_t val; 46 47 switch (addr) { 48 case 0x00: 49 val = d->i.bmdma[0].cmd; 50 break; 51 case 0x01: 52 val = d->regs[0].swdata; 53 break; 54 case 0x02: 55 val = d->i.bmdma[0].status; 56 break; 57 case 0x03: 58 val = 0; 59 break; 60 case 0x04 ... 0x07: 61 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size); 62 break; 63 case 0x08: 64 val = d->i.bmdma[1].cmd; 65 break; 66 case 0x09: 67 val = d->regs[1].swdata; 68 break; 69 case 0x0a: 70 val = d->i.bmdma[1].status; 71 break; 72 case 0x0b: 73 val = 0; 74 break; 75 case 0x0c ... 0x0f: 76 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size); 77 break; 78 case 0x10: 79 val = d->i.bmdma[0].cmd; 80 val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/ 81 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/ 82 val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0); 83 val |= (uint32_t)d->i.bmdma[0].status << 16; 84 val |= (uint32_t)d->i.bmdma[1].status << 24; 85 break; 86 case 0x18: 87 val = d->i.bmdma[1].cmd; 88 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0); 89 val |= (uint32_t)d->i.bmdma[1].status << 16; 90 break; 91 case 0x80 ... 0x87: 92 val = pci_ide_data_le_ops.read(&d->i.bus[0], addr - 0x80, size); 93 break; 94 case 0x8a: 95 val = pci_ide_cmd_le_ops.read(&d->i.bus[0], 2, size); 96 break; 97 case 0xa0: 98 val = d->regs[0].confstat; 99 break; 100 case 0xc0 ... 0xc7: 101 val = pci_ide_data_le_ops.read(&d->i.bus[1], addr - 0xc0, size); 102 break; 103 case 0xca: 104 val = pci_ide_cmd_le_ops.read(&d->i.bus[1], 2, size); 105 break; 106 case 0xe0: 107 val = d->regs[1].confstat; 108 break; 109 case 0x100: 110 val = d->regs[0].scontrol; 111 break; 112 case 0x104: 113 val = (d->i.bus[0].ifs[0].blk) ? 0x113 : 0; 114 break; 115 case 0x148: 116 val = (uint32_t)d->regs[0].sien << 16; 117 break; 118 case 0x180: 119 val = d->regs[1].scontrol; 120 break; 121 case 0x184: 122 val = (d->i.bus[1].ifs[0].blk) ? 0x113 : 0; 123 break; 124 case 0x1c8: 125 val = (uint32_t)d->regs[1].sien << 16; 126 break; 127 default: 128 val = 0; 129 break; 130 } 131 trace_sii3112_read(size, addr, val); 132 return val; 133 } 134 135 static void sii3112_reg_write(void *opaque, hwaddr addr, 136 uint64_t val, unsigned int size) 137 { 138 SiI3112PCIState *d = opaque; 139 140 trace_sii3112_write(size, addr, val); 141 switch (addr) { 142 case 0x00: 143 case 0x10: 144 bmdma_cmd_writeb(&d->i.bmdma[0], val); 145 break; 146 case 0x01: 147 case 0x11: 148 d->regs[0].swdata = val & 0x3f; 149 break; 150 case 0x02: 151 case 0x12: 152 bmdma_status_writeb(&d->i.bmdma[0], val); 153 break; 154 case 0x04 ... 0x07: 155 bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size); 156 break; 157 case 0x08: 158 case 0x18: 159 bmdma_cmd_writeb(&d->i.bmdma[1], val); 160 break; 161 case 0x09: 162 case 0x19: 163 d->regs[1].swdata = val & 0x3f; 164 break; 165 case 0x0a: 166 case 0x1a: 167 bmdma_status_writeb(&d->i.bmdma[1], val); 168 break; 169 case 0x0c ... 0x0f: 170 bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size); 171 break; 172 case 0x80 ... 0x87: 173 pci_ide_data_le_ops.write(&d->i.bus[0], addr - 0x80, val, size); 174 break; 175 case 0x8a: 176 pci_ide_cmd_le_ops.write(&d->i.bus[0], 2, val, size); 177 break; 178 case 0xc0 ... 0xc7: 179 pci_ide_data_le_ops.write(&d->i.bus[1], addr - 0xc0, val, size); 180 break; 181 case 0xca: 182 pci_ide_cmd_le_ops.write(&d->i.bus[1], 2, val, size); 183 break; 184 case 0x100: 185 d->regs[0].scontrol = val & 0xfff; 186 if (val & 1) { 187 ide_bus_reset(&d->i.bus[0]); 188 } 189 break; 190 case 0x148: 191 d->regs[0].sien = (val >> 16) & 0x3eed; 192 break; 193 case 0x180: 194 d->regs[1].scontrol = val & 0xfff; 195 if (val & 1) { 196 ide_bus_reset(&d->i.bus[1]); 197 } 198 break; 199 case 0x1c8: 200 d->regs[1].sien = (val >> 16) & 0x3eed; 201 break; 202 default: 203 break; 204 } 205 } 206 207 static const MemoryRegionOps sii3112_reg_ops = { 208 .read = sii3112_reg_read, 209 .write = sii3112_reg_write, 210 .endianness = DEVICE_LITTLE_ENDIAN, 211 }; 212 213 /* the PCI irq level is the logical OR of the two channels */ 214 static void sii3112_update_irq(SiI3112PCIState *s) 215 { 216 int i, set = 0; 217 218 for (i = 0; i < 2; i++) { 219 set |= s->regs[i].confstat & (1UL << 11); 220 } 221 pci_set_irq(PCI_DEVICE(s), (set ? 1 : 0)); 222 } 223 224 static void sii3112_set_irq(void *opaque, int channel, int level) 225 { 226 SiI3112PCIState *s = opaque; 227 228 trace_sii3112_set_irq(channel, level); 229 if (level) { 230 s->regs[channel].confstat |= (1UL << 11); 231 } else { 232 s->regs[channel].confstat &= ~(1UL << 11); 233 } 234 235 sii3112_update_irq(s); 236 } 237 238 static void sii3112_reset(DeviceState *dev) 239 { 240 SiI3112PCIState *s = SII3112_PCI(dev); 241 int i; 242 243 for (i = 0; i < 2; i++) { 244 s->regs[i].confstat = 0x6515 << 16; 245 ide_bus_reset(&s->i.bus[i]); 246 } 247 } 248 249 static void sii3112_pci_realize(PCIDevice *dev, Error **errp) 250 { 251 SiI3112PCIState *d = SII3112_PCI(dev); 252 PCIIDEState *s = PCI_IDE(dev); 253 DeviceState *ds = DEVICE(dev); 254 MemoryRegion *mr; 255 int i; 256 257 pci_config_set_interrupt_pin(dev->config, 1); 258 pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8); 259 260 /* BAR5 is in PCI memory space */ 261 memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d, 262 "sii3112.bar5", 0x200); 263 pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 264 265 /* BAR0-BAR4 are PCI I/O space aliases into BAR5 */ 266 mr = g_new(MemoryRegion, 1); 267 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80, 8); 268 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, mr); 269 mr = g_new(MemoryRegion, 1); 270 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88, 4); 271 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, mr); 272 mr = g_new(MemoryRegion, 1); 273 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0, 8); 274 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, mr); 275 mr = g_new(MemoryRegion, 1); 276 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8, 4); 277 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, mr); 278 mr = g_new(MemoryRegion, 1); 279 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16); 280 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, mr); 281 282 qdev_init_gpio_in(ds, sii3112_set_irq, 2); 283 for (i = 0; i < 2; i++) { 284 ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1); 285 ide_bus_init_output_irq(&s->bus[i], qdev_get_gpio_in(ds, i)); 286 287 bmdma_init(&s->bus[i], &s->bmdma[i], s); 288 ide_bus_register_restart_cb(&s->bus[i]); 289 } 290 } 291 292 static void sii3112_pci_class_init(ObjectClass *klass, void *data) 293 { 294 DeviceClass *dc = DEVICE_CLASS(klass); 295 PCIDeviceClass *pd = PCI_DEVICE_CLASS(klass); 296 297 pd->vendor_id = 0x1095; 298 pd->device_id = 0x3112; 299 pd->class_id = PCI_CLASS_STORAGE_RAID; 300 pd->revision = 1; 301 pd->realize = sii3112_pci_realize; 302 dc->reset = sii3112_reset; 303 dc->desc = "SiI3112A SATA controller"; 304 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 305 } 306 307 static const TypeInfo sii3112_pci_info = { 308 .name = TYPE_SII3112_PCI, 309 .parent = TYPE_PCI_IDE, 310 .instance_size = sizeof(SiI3112PCIState), 311 .class_init = sii3112_pci_class_init, 312 }; 313 314 static void sii3112_register_types(void) 315 { 316 type_register_static(&sii3112_pci_info); 317 } 318 319 type_init(sii3112_register_types) 320