1 /* 2 * QEMU IDE Emulation: PCI PIIX3/4 support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include <hw/hw.h> 28 #include <hw/i386/pc.h> 29 #include <hw/pci/pci.h> 30 #include <hw/isa/isa.h> 31 #include "sysemu/block-backend.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/dma.h" 34 35 #include <hw/ide/pci.h> 36 37 static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size) 38 { 39 BMDMAState *bm = opaque; 40 uint32_t val; 41 42 if (size != 1) { 43 return ((uint64_t)1 << (size * 8)) - 1; 44 } 45 46 switch(addr & 3) { 47 case 0: 48 val = bm->cmd; 49 break; 50 case 2: 51 val = bm->status; 52 break; 53 default: 54 val = 0xff; 55 break; 56 } 57 #ifdef DEBUG_IDE 58 printf("bmdma: readb 0x%02x : 0x%02x\n", (uint8_t)addr, val); 59 #endif 60 return val; 61 } 62 63 static void bmdma_write(void *opaque, hwaddr addr, 64 uint64_t val, unsigned size) 65 { 66 BMDMAState *bm = opaque; 67 68 if (size != 1) { 69 return; 70 } 71 72 #ifdef DEBUG_IDE 73 printf("bmdma: writeb 0x%02x : 0x%02x\n", (uint8_t)addr, (uint8_t)val); 74 #endif 75 switch(addr & 3) { 76 case 0: 77 bmdma_cmd_writeb(bm, val); 78 break; 79 case 2: 80 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 81 break; 82 } 83 } 84 85 static const MemoryRegionOps piix_bmdma_ops = { 86 .read = bmdma_read, 87 .write = bmdma_write, 88 }; 89 90 static void bmdma_setup_bar(PCIIDEState *d) 91 { 92 int i; 93 94 memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16); 95 for(i = 0;i < 2; i++) { 96 BMDMAState *bm = &d->bmdma[i]; 97 98 memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm, 99 "piix-bmdma", 4); 100 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 101 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 102 &bmdma_addr_ioport_ops, bm, "bmdma", 4); 103 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 104 } 105 } 106 107 static void piix3_reset(void *opaque) 108 { 109 PCIIDEState *d = opaque; 110 PCIDevice *pd = PCI_DEVICE(d); 111 uint8_t *pci_conf = pd->config; 112 int i; 113 114 for (i = 0; i < 2; i++) { 115 ide_bus_reset(&d->bus[i]); 116 } 117 118 /* TODO: this is the default. do not override. */ 119 pci_conf[PCI_COMMAND] = 0x00; 120 /* TODO: this is the default. do not override. */ 121 pci_conf[PCI_COMMAND + 1] = 0x00; 122 /* TODO: use pci_set_word */ 123 pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK; 124 pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8; 125 pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ 126 } 127 128 static void pci_piix_init_ports(PCIIDEState *d) { 129 static const struct { 130 int iobase; 131 int iobase2; 132 int isairq; 133 } port_info[] = { 134 {0x1f0, 0x3f6, 14}, 135 {0x170, 0x376, 15}, 136 }; 137 int i; 138 139 for (i = 0; i < 2; i++) { 140 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); 141 ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, 142 port_info[i].iobase2); 143 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); 144 145 bmdma_init(&d->bus[i], &d->bmdma[i], d); 146 d->bmdma[i].bus = &d->bus[i]; 147 ide_register_restart_cb(&d->bus[i]); 148 } 149 } 150 151 static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) 152 { 153 PCIIDEState *d = PCI_IDE(dev); 154 uint8_t *pci_conf = dev->config; 155 156 pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode 157 158 qemu_register_reset(piix3_reset, d); 159 160 bmdma_setup_bar(d); 161 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 162 163 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); 164 165 pci_piix_init_ports(d); 166 } 167 168 int pci_piix3_xen_ide_unplug(DeviceState *dev) 169 { 170 PCIIDEState *pci_ide; 171 DriveInfo *di; 172 int i; 173 IDEDevice *idedev; 174 175 pci_ide = PCI_IDE(dev); 176 177 for (i = 0; i < 4; i++) { 178 di = drive_get_by_index(IF_IDE, i); 179 if (di != NULL && !di->media_cd) { 180 BlockBackend *blk = blk_by_legacy_dinfo(di); 181 DeviceState *ds = blk_get_attached_dev(blk); 182 if (ds) { 183 blk_detach_dev(blk, ds); 184 } 185 pci_ide->bus[di->bus].ifs[di->unit].blk = NULL; 186 if (!(i % 2)) { 187 idedev = pci_ide->bus[di->bus].master; 188 } else { 189 idedev = pci_ide->bus[di->bus].slave; 190 } 191 idedev->conf.blk = NULL; 192 monitor_remove_blk(blk); 193 blk_unref(blk); 194 } 195 } 196 qdev_reset_all(DEVICE(dev)); 197 return 0; 198 } 199 200 PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 201 { 202 PCIDevice *dev; 203 204 dev = pci_create_simple(bus, devfn, "piix3-ide-xen"); 205 pci_ide_create_devs(dev, hd_table); 206 return dev; 207 } 208 209 static void pci_piix_ide_exitfn(PCIDevice *dev) 210 { 211 PCIIDEState *d = PCI_IDE(dev); 212 unsigned i; 213 214 for (i = 0; i < 2; ++i) { 215 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 216 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 217 } 218 } 219 220 /* hd_table must contain 4 block drivers */ 221 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ 222 PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 223 { 224 PCIDevice *dev; 225 226 dev = pci_create_simple(bus, devfn, "piix3-ide"); 227 pci_ide_create_devs(dev, hd_table); 228 return dev; 229 } 230 231 /* hd_table must contain 4 block drivers */ 232 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */ 233 PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 234 { 235 PCIDevice *dev; 236 237 dev = pci_create_simple(bus, devfn, "piix4-ide"); 238 pci_ide_create_devs(dev, hd_table); 239 return dev; 240 } 241 242 static void piix3_ide_class_init(ObjectClass *klass, void *data) 243 { 244 DeviceClass *dc = DEVICE_CLASS(klass); 245 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 246 247 k->realize = pci_piix_ide_realize; 248 k->exit = pci_piix_ide_exitfn; 249 k->vendor_id = PCI_VENDOR_ID_INTEL; 250 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; 251 k->class_id = PCI_CLASS_STORAGE_IDE; 252 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 253 dc->hotpluggable = false; 254 } 255 256 static const TypeInfo piix3_ide_info = { 257 .name = "piix3-ide", 258 .parent = TYPE_PCI_IDE, 259 .class_init = piix3_ide_class_init, 260 }; 261 262 static const TypeInfo piix3_ide_xen_info = { 263 .name = "piix3-ide-xen", 264 .parent = TYPE_PCI_IDE, 265 .class_init = piix3_ide_class_init, 266 }; 267 268 static void piix4_ide_class_init(ObjectClass *klass, void *data) 269 { 270 DeviceClass *dc = DEVICE_CLASS(klass); 271 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 272 273 k->realize = pci_piix_ide_realize; 274 k->exit = pci_piix_ide_exitfn; 275 k->vendor_id = PCI_VENDOR_ID_INTEL; 276 k->device_id = PCI_DEVICE_ID_INTEL_82371AB; 277 k->class_id = PCI_CLASS_STORAGE_IDE; 278 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 279 dc->hotpluggable = false; 280 } 281 282 static const TypeInfo piix4_ide_info = { 283 .name = "piix4-ide", 284 .parent = TYPE_PCI_IDE, 285 .class_init = piix4_ide_class_init, 286 }; 287 288 static void piix_ide_register_types(void) 289 { 290 type_register_static(&piix3_ide_info); 291 type_register_static(&piix3_ide_xen_info); 292 type_register_static(&piix4_ide_info); 293 } 294 295 type_init(piix_ide_register_types) 296