1 /* 2 * QEMU IDE Emulation: PCI PIIX3/4 support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include <hw/hw.h> 26 #include <hw/pc.h> 27 #include <hw/pci.h> 28 #include <hw/isa.h> 29 #include "block.h" 30 #include "sysemu.h" 31 #include "dma.h" 32 33 #include <hw/ide/pci.h> 34 35 static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size) 36 { 37 BMDMAState *bm = opaque; 38 uint32_t val; 39 40 if (size != 1) { 41 return ((uint64_t)1 << (size * 8)) - 1; 42 } 43 44 switch(addr & 3) { 45 case 0: 46 val = bm->cmd; 47 break; 48 case 2: 49 val = bm->status; 50 break; 51 default: 52 val = 0xff; 53 break; 54 } 55 #ifdef DEBUG_IDE 56 printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val); 57 #endif 58 return val; 59 } 60 61 static void bmdma_write(void *opaque, target_phys_addr_t addr, 62 uint64_t val, unsigned size) 63 { 64 BMDMAState *bm = opaque; 65 66 if (size != 1) { 67 return; 68 } 69 70 #ifdef DEBUG_IDE 71 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val); 72 #endif 73 switch(addr & 3) { 74 case 0: 75 return bmdma_cmd_writeb(bm, val); 76 case 2: 77 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 78 break; 79 } 80 } 81 82 static MemoryRegionOps piix_bmdma_ops = { 83 .read = bmdma_read, 84 .write = bmdma_write, 85 }; 86 87 static void bmdma_setup_bar(PCIIDEState *d) 88 { 89 int i; 90 91 memory_region_init(&d->bmdma_bar, "piix-bmdma-container", 16); 92 for(i = 0;i < 2; i++) { 93 BMDMAState *bm = &d->bmdma[i]; 94 95 memory_region_init_io(&bm->extra_io, &piix_bmdma_ops, bm, 96 "piix-bmdma", 4); 97 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 98 memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm, 99 "bmdma", 4); 100 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 101 } 102 } 103 104 static void piix3_reset(void *opaque) 105 { 106 PCIIDEState *d = opaque; 107 uint8_t *pci_conf = d->dev.config; 108 int i; 109 110 for (i = 0; i < 2; i++) { 111 ide_bus_reset(&d->bus[i]); 112 } 113 114 /* TODO: this is the default. do not override. */ 115 pci_conf[PCI_COMMAND] = 0x00; 116 /* TODO: this is the default. do not override. */ 117 pci_conf[PCI_COMMAND + 1] = 0x00; 118 /* TODO: use pci_set_word */ 119 pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK; 120 pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8; 121 pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ 122 } 123 124 static void pci_piix_init_ports(PCIIDEState *d) { 125 int i; 126 struct { 127 int iobase; 128 int iobase2; 129 int isairq; 130 } port_info[] = { 131 {0x1f0, 0x3f6, 14}, 132 {0x170, 0x376, 15}, 133 }; 134 135 for (i = 0; i < 2; i++) { 136 ide_bus_new(&d->bus[i], &d->dev.qdev, i); 137 ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2); 138 ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq)); 139 140 bmdma_init(&d->bus[i], &d->bmdma[i], d); 141 d->bmdma[i].bus = &d->bus[i]; 142 qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb, 143 &d->bmdma[i].dma); 144 } 145 } 146 147 static int pci_piix_ide_initfn(PCIDevice *dev) 148 { 149 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); 150 uint8_t *pci_conf = d->dev.config; 151 152 pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode 153 154 qemu_register_reset(piix3_reset, d); 155 156 bmdma_setup_bar(d); 157 pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 158 159 vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d); 160 161 pci_piix_init_ports(d); 162 163 return 0; 164 } 165 166 static int pci_piix3_xen_ide_unplug(DeviceState *dev) 167 { 168 PCIDevice *pci_dev; 169 PCIIDEState *pci_ide; 170 DriveInfo *di; 171 int i = 0; 172 173 pci_dev = DO_UPCAST(PCIDevice, qdev, dev); 174 pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev); 175 176 for (; i < 3; i++) { 177 di = drive_get_by_index(IF_IDE, i); 178 if (di != NULL && !di->media_cd) { 179 DeviceState *ds = bdrv_get_attached_dev(di->bdrv); 180 if (ds) { 181 bdrv_detach_dev(di->bdrv, ds); 182 } 183 bdrv_close(di->bdrv); 184 pci_ide->bus[di->bus].ifs[di->unit].bs = NULL; 185 drive_put_ref(di); 186 } 187 } 188 qdev_reset_all(&(pci_ide->dev.qdev)); 189 return 0; 190 } 191 192 PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 193 { 194 PCIDevice *dev; 195 196 dev = pci_create_simple(bus, devfn, "piix3-ide-xen"); 197 dev->qdev.info->unplug = pci_piix3_xen_ide_unplug; 198 pci_ide_create_devs(dev, hd_table); 199 return dev; 200 } 201 202 static int pci_piix_ide_exitfn(PCIDevice *dev) 203 { 204 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); 205 unsigned i; 206 207 for (i = 0; i < 2; ++i) { 208 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 209 memory_region_destroy(&d->bmdma[i].extra_io); 210 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 211 memory_region_destroy(&d->bmdma[i].addr_ioport); 212 } 213 memory_region_destroy(&d->bmdma_bar); 214 215 return 0; 216 } 217 218 /* hd_table must contain 4 block drivers */ 219 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ 220 PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 221 { 222 PCIDevice *dev; 223 224 dev = pci_create_simple(bus, devfn, "piix3-ide"); 225 pci_ide_create_devs(dev, hd_table); 226 return dev; 227 } 228 229 /* hd_table must contain 4 block drivers */ 230 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */ 231 PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 232 { 233 PCIDevice *dev; 234 235 dev = pci_create_simple(bus, devfn, "piix4-ide"); 236 pci_ide_create_devs(dev, hd_table); 237 return dev; 238 } 239 240 static PCIDeviceInfo piix_ide_info[] = { 241 { 242 .qdev.name = "piix3-ide", 243 .qdev.size = sizeof(PCIIDEState), 244 .qdev.no_user = 1, 245 .no_hotplug = 1, 246 .init = pci_piix_ide_initfn, 247 .exit = pci_piix_ide_exitfn, 248 .vendor_id = PCI_VENDOR_ID_INTEL, 249 .device_id = PCI_DEVICE_ID_INTEL_82371SB_1, 250 .class_id = PCI_CLASS_STORAGE_IDE, 251 },{ 252 .qdev.name = "piix3-ide-xen", 253 .qdev.size = sizeof(PCIIDEState), 254 .qdev.no_user = 1, 255 .init = pci_piix_ide_initfn, 256 .vendor_id = PCI_VENDOR_ID_INTEL, 257 .device_id = PCI_DEVICE_ID_INTEL_82371SB_1, 258 .class_id = PCI_CLASS_STORAGE_IDE, 259 },{ 260 .qdev.name = "piix4-ide", 261 .qdev.size = sizeof(PCIIDEState), 262 .qdev.no_user = 1, 263 .no_hotplug = 1, 264 .init = pci_piix_ide_initfn, 265 .exit = pci_piix_ide_exitfn, 266 .vendor_id = PCI_VENDOR_ID_INTEL, 267 .device_id = PCI_DEVICE_ID_INTEL_82371AB, 268 .class_id = PCI_CLASS_STORAGE_IDE, 269 },{ 270 /* end of list */ 271 } 272 }; 273 274 static void piix_ide_register(void) 275 { 276 pci_qdev_register_many(piix_ide_info); 277 } 278 device_init(piix_ide_register); 279