1 /* 2 * QEMU IDE Emulation: PCI PIIX3/4 support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * References: 26 * [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR, 27 * 290550-002, Intel Corporation, April 1997. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/pci/pci.h" 32 #include "migration/vmstate.h" 33 #include "qapi/error.h" 34 #include "qemu/module.h" 35 #include "sysemu/block-backend.h" 36 #include "sysemu/blockdev.h" 37 #include "sysemu/dma.h" 38 39 #include "hw/ide/pci.h" 40 #include "trace.h" 41 42 static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size) 43 { 44 BMDMAState *bm = opaque; 45 uint32_t val; 46 47 if (size != 1) { 48 return ((uint64_t)1 << (size * 8)) - 1; 49 } 50 51 switch(addr & 3) { 52 case 0: 53 val = bm->cmd; 54 break; 55 case 2: 56 val = bm->status; 57 break; 58 default: 59 val = 0xff; 60 break; 61 } 62 63 trace_bmdma_read(addr, val); 64 return val; 65 } 66 67 static void bmdma_write(void *opaque, hwaddr addr, 68 uint64_t val, unsigned size) 69 { 70 BMDMAState *bm = opaque; 71 72 if (size != 1) { 73 return; 74 } 75 76 trace_bmdma_write(addr, val); 77 78 switch(addr & 3) { 79 case 0: 80 bmdma_cmd_writeb(bm, val); 81 break; 82 case 2: 83 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 84 break; 85 } 86 } 87 88 static const MemoryRegionOps piix_bmdma_ops = { 89 .read = bmdma_read, 90 .write = bmdma_write, 91 }; 92 93 static void bmdma_setup_bar(PCIIDEState *d) 94 { 95 int i; 96 97 memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16); 98 for(i = 0;i < 2; i++) { 99 BMDMAState *bm = &d->bmdma[i]; 100 101 memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm, 102 "piix-bmdma", 4); 103 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 104 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 105 &bmdma_addr_ioport_ops, bm, "bmdma", 4); 106 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 107 } 108 } 109 110 static void piix_ide_reset(DeviceState *dev) 111 { 112 PCIIDEState *d = PCI_IDE(dev); 113 PCIDevice *pd = PCI_DEVICE(d); 114 uint8_t *pci_conf = pd->config; 115 int i; 116 117 for (i = 0; i < 2; i++) { 118 ide_bus_reset(&d->bus[i]); 119 } 120 121 /* PCI command register default value (0000h) per [1, p.48]. */ 122 pci_set_word(pci_conf + PCI_COMMAND, 0x0000); 123 pci_set_word(pci_conf + PCI_STATUS, 124 PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK); 125 pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */ 126 } 127 128 static int pci_piix_init_ports(PCIIDEState *d) 129 { 130 static const struct { 131 int iobase; 132 int iobase2; 133 int isairq; 134 } port_info[] = { 135 {0x1f0, 0x3f6, 14}, 136 {0x170, 0x376, 15}, 137 }; 138 int i, ret; 139 140 for (i = 0; i < 2; i++) { 141 ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); 142 ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, 143 port_info[i].iobase2); 144 if (ret) { 145 return ret; 146 } 147 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); 148 149 bmdma_init(&d->bus[i], &d->bmdma[i], d); 150 d->bmdma[i].bus = &d->bus[i]; 151 ide_register_restart_cb(&d->bus[i]); 152 } 153 154 return 0; 155 } 156 157 static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) 158 { 159 PCIIDEState *d = PCI_IDE(dev); 160 uint8_t *pci_conf = dev->config; 161 int rc; 162 163 pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode 164 165 bmdma_setup_bar(d); 166 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 167 168 vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d); 169 170 rc = pci_piix_init_ports(d); 171 if (rc) { 172 error_setg_errno(errp, -rc, "Failed to realize %s", 173 object_get_typename(OBJECT(dev))); 174 } 175 } 176 177 static void pci_piix_ide_exitfn(PCIDevice *dev) 178 { 179 PCIIDEState *d = PCI_IDE(dev); 180 unsigned i; 181 182 for (i = 0; i < 2; ++i) { 183 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 184 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 185 } 186 } 187 188 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ 189 static void piix3_ide_class_init(ObjectClass *klass, void *data) 190 { 191 DeviceClass *dc = DEVICE_CLASS(klass); 192 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 193 194 dc->reset = piix_ide_reset; 195 k->realize = pci_piix_ide_realize; 196 k->exit = pci_piix_ide_exitfn; 197 k->vendor_id = PCI_VENDOR_ID_INTEL; 198 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; 199 k->class_id = PCI_CLASS_STORAGE_IDE; 200 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 201 dc->hotpluggable = false; 202 } 203 204 static const TypeInfo piix3_ide_info = { 205 .name = "piix3-ide", 206 .parent = TYPE_PCI_IDE, 207 .class_init = piix3_ide_class_init, 208 }; 209 210 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */ 211 static void piix4_ide_class_init(ObjectClass *klass, void *data) 212 { 213 DeviceClass *dc = DEVICE_CLASS(klass); 214 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 215 216 dc->reset = piix_ide_reset; 217 k->realize = pci_piix_ide_realize; 218 k->exit = pci_piix_ide_exitfn; 219 k->vendor_id = PCI_VENDOR_ID_INTEL; 220 k->device_id = PCI_DEVICE_ID_INTEL_82371AB; 221 k->class_id = PCI_CLASS_STORAGE_IDE; 222 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 223 dc->hotpluggable = false; 224 } 225 226 static const TypeInfo piix4_ide_info = { 227 .name = "piix4-ide", 228 .parent = TYPE_PCI_IDE, 229 .class_init = piix4_ide_class_init, 230 }; 231 232 static void piix_ide_register_types(void) 233 { 234 type_register_static(&piix3_ide_info); 235 type_register_static(&piix4_ide_info); 236 } 237 238 type_init(piix_ide_register_types) 239