xref: /openbmc/qemu/hw/ide/piix.c (revision 3588185b)
1 /*
2  * QEMU IDE Emulation: PCI PIIX3/4 support.
3  *
4  * Copyright (c) 2003 Fabrice Bellard
5  * Copyright (c) 2006 Openedhand Ltd.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 
26 #include <hw/hw.h>
27 #include <hw/pc.h>
28 #include <hw/pci/pci.h>
29 #include <hw/isa.h>
30 #include "sysemu/blockdev.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/dma.h"
33 
34 #include <hw/ide/pci.h>
35 
36 static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
37 {
38     BMDMAState *bm = opaque;
39     uint32_t val;
40 
41     if (size != 1) {
42         return ((uint64_t)1 << (size * 8)) - 1;
43     }
44 
45     switch(addr & 3) {
46     case 0:
47         val = bm->cmd;
48         break;
49     case 2:
50         val = bm->status;
51         break;
52     default:
53         val = 0xff;
54         break;
55     }
56 #ifdef DEBUG_IDE
57     printf("bmdma: readb 0x%02x : 0x%02x\n", (uint8_t)addr, val);
58 #endif
59     return val;
60 }
61 
62 static void bmdma_write(void *opaque, hwaddr addr,
63                         uint64_t val, unsigned size)
64 {
65     BMDMAState *bm = opaque;
66 
67     if (size != 1) {
68         return;
69     }
70 
71 #ifdef DEBUG_IDE
72     printf("bmdma: writeb 0x%02x : 0x%02x\n", (uint8_t)addr, (uint8_t)val);
73 #endif
74     switch(addr & 3) {
75     case 0:
76         bmdma_cmd_writeb(bm, val);
77         break;
78     case 2:
79         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
80         break;
81     }
82 }
83 
84 static const MemoryRegionOps piix_bmdma_ops = {
85     .read = bmdma_read,
86     .write = bmdma_write,
87 };
88 
89 static void bmdma_setup_bar(PCIIDEState *d)
90 {
91     int i;
92 
93     memory_region_init(&d->bmdma_bar, "piix-bmdma-container", 16);
94     for(i = 0;i < 2; i++) {
95         BMDMAState *bm = &d->bmdma[i];
96 
97         memory_region_init_io(&bm->extra_io, &piix_bmdma_ops, bm,
98                               "piix-bmdma", 4);
99         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
100         memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
101                               "bmdma", 4);
102         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
103     }
104 }
105 
106 static void piix3_reset(void *opaque)
107 {
108     PCIIDEState *d = opaque;
109     uint8_t *pci_conf = d->dev.config;
110     int i;
111 
112     for (i = 0; i < 2; i++) {
113         ide_bus_reset(&d->bus[i]);
114     }
115 
116     /* TODO: this is the default. do not override. */
117     pci_conf[PCI_COMMAND] = 0x00;
118     /* TODO: this is the default. do not override. */
119     pci_conf[PCI_COMMAND + 1] = 0x00;
120     /* TODO: use pci_set_word */
121     pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
122     pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
123     pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
124 }
125 
126 static void pci_piix_init_ports(PCIIDEState *d) {
127     static const struct {
128         int iobase;
129         int iobase2;
130         int isairq;
131     } port_info[] = {
132         {0x1f0, 0x3f6, 14},
133         {0x170, 0x376, 15},
134     };
135     int i;
136 
137     for (i = 0; i < 2; i++) {
138         ide_bus_new(&d->bus[i], &d->dev.qdev, i);
139         ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
140                         port_info[i].iobase2);
141         ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
142 
143         bmdma_init(&d->bus[i], &d->bmdma[i], d);
144         d->bmdma[i].bus = &d->bus[i];
145         qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
146                                          &d->bmdma[i].dma);
147     }
148 }
149 
150 static int pci_piix_ide_initfn(PCIDevice *dev)
151 {
152     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
153     uint8_t *pci_conf = d->dev.config;
154 
155     pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
156 
157     qemu_register_reset(piix3_reset, d);
158 
159     bmdma_setup_bar(d);
160     pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
161 
162     vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
163 
164     pci_piix_init_ports(d);
165 
166     return 0;
167 }
168 
169 static int pci_piix3_xen_ide_unplug(DeviceState *dev)
170 {
171     PCIDevice *pci_dev;
172     PCIIDEState *pci_ide;
173     DriveInfo *di;
174     int i = 0;
175 
176     pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
177     pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);
178 
179     for (; i < 3; i++) {
180         di = drive_get_by_index(IF_IDE, i);
181         if (di != NULL && !di->media_cd) {
182             DeviceState *ds = bdrv_get_attached_dev(di->bdrv);
183             if (ds) {
184                 bdrv_detach_dev(di->bdrv, ds);
185             }
186             bdrv_close(di->bdrv);
187             pci_ide->bus[di->bus].ifs[di->unit].bs = NULL;
188             drive_put_ref(di);
189         }
190     }
191     qdev_reset_all(&(pci_ide->dev.qdev));
192     return 0;
193 }
194 
195 PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
196 {
197     PCIDevice *dev;
198 
199     dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
200     pci_ide_create_devs(dev, hd_table);
201     return dev;
202 }
203 
204 static void pci_piix_ide_exitfn(PCIDevice *dev)
205 {
206     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
207     unsigned i;
208 
209     for (i = 0; i < 2; ++i) {
210         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
211         memory_region_destroy(&d->bmdma[i].extra_io);
212         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
213         memory_region_destroy(&d->bmdma[i].addr_ioport);
214     }
215     memory_region_destroy(&d->bmdma_bar);
216 }
217 
218 /* hd_table must contain 4 block drivers */
219 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
220 PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
221 {
222     PCIDevice *dev;
223 
224     dev = pci_create_simple(bus, devfn, "piix3-ide");
225     pci_ide_create_devs(dev, hd_table);
226     return dev;
227 }
228 
229 /* hd_table must contain 4 block drivers */
230 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
231 PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
232 {
233     PCIDevice *dev;
234 
235     dev = pci_create_simple(bus, devfn, "piix4-ide");
236     pci_ide_create_devs(dev, hd_table);
237     return dev;
238 }
239 
240 static void piix3_ide_class_init(ObjectClass *klass, void *data)
241 {
242     DeviceClass *dc = DEVICE_CLASS(klass);
243     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
244 
245     k->no_hotplug = 1;
246     k->init = pci_piix_ide_initfn;
247     k->exit = pci_piix_ide_exitfn;
248     k->vendor_id = PCI_VENDOR_ID_INTEL;
249     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
250     k->class_id = PCI_CLASS_STORAGE_IDE;
251     dc->no_user = 1;
252 }
253 
254 static const TypeInfo piix3_ide_info = {
255     .name          = "piix3-ide",
256     .parent        = TYPE_PCI_DEVICE,
257     .instance_size = sizeof(PCIIDEState),
258     .class_init    = piix3_ide_class_init,
259 };
260 
261 static void piix3_ide_xen_class_init(ObjectClass *klass, void *data)
262 {
263     DeviceClass *dc = DEVICE_CLASS(klass);
264     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
265 
266     k->init = pci_piix_ide_initfn;
267     k->vendor_id = PCI_VENDOR_ID_INTEL;
268     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
269     k->class_id = PCI_CLASS_STORAGE_IDE;
270     dc->no_user = 1;
271     dc->unplug = pci_piix3_xen_ide_unplug;
272 }
273 
274 static const TypeInfo piix3_ide_xen_info = {
275     .name          = "piix3-ide-xen",
276     .parent        = TYPE_PCI_DEVICE,
277     .instance_size = sizeof(PCIIDEState),
278     .class_init    = piix3_ide_xen_class_init,
279 };
280 
281 static void piix4_ide_class_init(ObjectClass *klass, void *data)
282 {
283     DeviceClass *dc = DEVICE_CLASS(klass);
284     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
285 
286     k->no_hotplug = 1;
287     k->init = pci_piix_ide_initfn;
288     k->exit = pci_piix_ide_exitfn;
289     k->vendor_id = PCI_VENDOR_ID_INTEL;
290     k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
291     k->class_id = PCI_CLASS_STORAGE_IDE;
292     dc->no_user = 1;
293 }
294 
295 static const TypeInfo piix4_ide_info = {
296     .name          = "piix4-ide",
297     .parent        = TYPE_PCI_DEVICE,
298     .instance_size = sizeof(PCIIDEState),
299     .class_init    = piix4_ide_class_init,
300 };
301 
302 static void piix_ide_register_types(void)
303 {
304     type_register_static(&piix3_ide_info);
305     type_register_static(&piix3_ide_xen_info);
306     type_register_static(&piix4_ide_info);
307 }
308 
309 type_init(piix_ide_register_types)
310