1 /* 2 * QEMU IDE Emulation: mmio support (for embedded). 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "qemu/module.h" 30 #include "sysemu/dma.h" 31 32 #include "hw/ide/internal.h" 33 #include "hw/qdev-properties.h" 34 #include "qom/object.h" 35 36 /***********************************************************/ 37 /* MMIO based ide port 38 * This emulates IDE device connected directly to the CPU bus without 39 * dedicated ide controller, which is often seen on embedded boards. 40 */ 41 42 #define TYPE_MMIO_IDE "mmio-ide" 43 OBJECT_DECLARE_SIMPLE_TYPE(MMIOIDEState, MMIO_IDE) 44 45 struct MMIOIDEState { 46 /*< private >*/ 47 SysBusDevice parent_obj; 48 /*< public >*/ 49 50 IDEBus bus; 51 52 uint32_t shift; 53 qemu_irq irq; 54 MemoryRegion iomem1, iomem2; 55 }; 56 57 static void mmio_ide_reset(DeviceState *dev) 58 { 59 MMIOIDEState *s = MMIO_IDE(dev); 60 61 ide_bus_reset(&s->bus); 62 } 63 64 static uint64_t mmio_ide_read(void *opaque, hwaddr addr, 65 unsigned size) 66 { 67 MMIOIDEState *s = opaque; 68 addr >>= s->shift; 69 if (addr & 7) 70 return ide_ioport_read(&s->bus, addr); 71 else 72 return ide_data_readw(&s->bus, 0); 73 } 74 75 static void mmio_ide_write(void *opaque, hwaddr addr, 76 uint64_t val, unsigned size) 77 { 78 MMIOIDEState *s = opaque; 79 addr >>= s->shift; 80 if (addr & 7) 81 ide_ioport_write(&s->bus, addr, val); 82 else 83 ide_data_writew(&s->bus, 0, val); 84 } 85 86 static const MemoryRegionOps mmio_ide_ops = { 87 .read = mmio_ide_read, 88 .write = mmio_ide_write, 89 .endianness = DEVICE_LITTLE_ENDIAN, 90 }; 91 92 static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr, 93 unsigned size) 94 { 95 MMIOIDEState *s = opaque; 96 return ide_status_read(&s->bus, 0); 97 } 98 99 static void mmio_ide_ctrl_write(void *opaque, hwaddr addr, 100 uint64_t val, unsigned size) 101 { 102 MMIOIDEState *s = opaque; 103 ide_ctrl_write(&s->bus, 0, val); 104 } 105 106 static const MemoryRegionOps mmio_ide_cs_ops = { 107 .read = mmio_ide_status_read, 108 .write = mmio_ide_ctrl_write, 109 .endianness = DEVICE_LITTLE_ENDIAN, 110 }; 111 112 static const VMStateDescription vmstate_ide_mmio = { 113 .name = "mmio-ide", 114 .version_id = 3, 115 .minimum_version_id = 0, 116 .fields = (VMStateField[]) { 117 VMSTATE_IDE_BUS(bus, MMIOIDEState), 118 VMSTATE_IDE_DRIVES(bus.ifs, MMIOIDEState), 119 VMSTATE_END_OF_LIST() 120 } 121 }; 122 123 static void mmio_ide_realizefn(DeviceState *dev, Error **errp) 124 { 125 SysBusDevice *d = SYS_BUS_DEVICE(dev); 126 MMIOIDEState *s = MMIO_IDE(dev); 127 128 ide_init2(&s->bus, s->irq); 129 130 memory_region_init_io(&s->iomem1, OBJECT(s), &mmio_ide_ops, s, 131 "ide-mmio.1", 16 << s->shift); 132 memory_region_init_io(&s->iomem2, OBJECT(s), &mmio_ide_cs_ops, s, 133 "ide-mmio.2", 2 << s->shift); 134 sysbus_init_mmio(d, &s->iomem1); 135 sysbus_init_mmio(d, &s->iomem2); 136 } 137 138 static void mmio_ide_initfn(Object *obj) 139 { 140 SysBusDevice *d = SYS_BUS_DEVICE(obj); 141 MMIOIDEState *s = MMIO_IDE(obj); 142 143 ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); 144 sysbus_init_irq(d, &s->irq); 145 } 146 147 static Property mmio_ide_properties[] = { 148 DEFINE_PROP_UINT32("shift", MMIOIDEState, shift, 0), 149 DEFINE_PROP_END_OF_LIST() 150 }; 151 152 static void mmio_ide_class_init(ObjectClass *oc, void *data) 153 { 154 DeviceClass *dc = DEVICE_CLASS(oc); 155 156 dc->realize = mmio_ide_realizefn; 157 dc->reset = mmio_ide_reset; 158 device_class_set_props(dc, mmio_ide_properties); 159 dc->vmsd = &vmstate_ide_mmio; 160 } 161 162 static const TypeInfo mmio_ide_type_info = { 163 .name = TYPE_MMIO_IDE, 164 .parent = TYPE_SYS_BUS_DEVICE, 165 .instance_size = sizeof(MMIOIDEState), 166 .instance_init = mmio_ide_initfn, 167 .class_init = mmio_ide_class_init, 168 }; 169 170 static void mmio_ide_register_types(void) 171 { 172 type_register_static(&mmio_ide_type_info); 173 } 174 175 void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1) 176 { 177 MMIOIDEState *s = MMIO_IDE(dev); 178 179 if (hd0 != NULL) { 180 ide_create_drive(&s->bus, 0, hd0); 181 } 182 if (hd1 != NULL) { 183 ide_create_drive(&s->bus, 1, hd1); 184 } 185 } 186 187 type_init(mmio_ide_register_types) 188