1 /* 2 * QEMU IDE Emulation: mmio support (for embedded). 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "qemu/module.h" 30 #include "sysemu/dma.h" 31 32 #include "hw/ide/internal.h" 33 #include "hw/qdev-properties.h" 34 35 /***********************************************************/ 36 /* MMIO based ide port 37 * This emulates IDE device connected directly to the CPU bus without 38 * dedicated ide controller, which is often seen on embedded boards. 39 */ 40 41 #define TYPE_MMIO_IDE "mmio-ide" 42 #define MMIO_IDE(obj) OBJECT_CHECK(MMIOState, (obj), TYPE_MMIO_IDE) 43 44 typedef struct MMIOIDEState { 45 /*< private >*/ 46 SysBusDevice parent_obj; 47 /*< public >*/ 48 49 IDEBus bus; 50 51 uint32_t shift; 52 qemu_irq irq; 53 MemoryRegion iomem1, iomem2; 54 } MMIOState; 55 56 static void mmio_ide_reset(DeviceState *dev) 57 { 58 MMIOState *s = MMIO_IDE(dev); 59 60 ide_bus_reset(&s->bus); 61 } 62 63 static uint64_t mmio_ide_read(void *opaque, hwaddr addr, 64 unsigned size) 65 { 66 MMIOState *s = opaque; 67 addr >>= s->shift; 68 if (addr & 7) 69 return ide_ioport_read(&s->bus, addr); 70 else 71 return ide_data_readw(&s->bus, 0); 72 } 73 74 static void mmio_ide_write(void *opaque, hwaddr addr, 75 uint64_t val, unsigned size) 76 { 77 MMIOState *s = opaque; 78 addr >>= s->shift; 79 if (addr & 7) 80 ide_ioport_write(&s->bus, addr, val); 81 else 82 ide_data_writew(&s->bus, 0, val); 83 } 84 85 static const MemoryRegionOps mmio_ide_ops = { 86 .read = mmio_ide_read, 87 .write = mmio_ide_write, 88 .endianness = DEVICE_LITTLE_ENDIAN, 89 }; 90 91 static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr, 92 unsigned size) 93 { 94 MMIOState *s= opaque; 95 return ide_status_read(&s->bus, 0); 96 } 97 98 static void mmio_ide_cmd_write(void *opaque, hwaddr addr, 99 uint64_t val, unsigned size) 100 { 101 MMIOState *s = opaque; 102 ide_cmd_write(&s->bus, 0, val); 103 } 104 105 static const MemoryRegionOps mmio_ide_cs_ops = { 106 .read = mmio_ide_status_read, 107 .write = mmio_ide_cmd_write, 108 .endianness = DEVICE_LITTLE_ENDIAN, 109 }; 110 111 static const VMStateDescription vmstate_ide_mmio = { 112 .name = "mmio-ide", 113 .version_id = 3, 114 .minimum_version_id = 0, 115 .fields = (VMStateField[]) { 116 VMSTATE_IDE_BUS(bus, MMIOState), 117 VMSTATE_IDE_DRIVES(bus.ifs, MMIOState), 118 VMSTATE_END_OF_LIST() 119 } 120 }; 121 122 static void mmio_ide_realizefn(DeviceState *dev, Error **errp) 123 { 124 SysBusDevice *d = SYS_BUS_DEVICE(dev); 125 MMIOState *s = MMIO_IDE(dev); 126 127 ide_init2(&s->bus, s->irq); 128 129 memory_region_init_io(&s->iomem1, OBJECT(s), &mmio_ide_ops, s, 130 "ide-mmio.1", 16 << s->shift); 131 memory_region_init_io(&s->iomem2, OBJECT(s), &mmio_ide_cs_ops, s, 132 "ide-mmio.2", 2 << s->shift); 133 sysbus_init_mmio(d, &s->iomem1); 134 sysbus_init_mmio(d, &s->iomem2); 135 } 136 137 static void mmio_ide_initfn(Object *obj) 138 { 139 SysBusDevice *d = SYS_BUS_DEVICE(obj); 140 MMIOState *s = MMIO_IDE(obj); 141 142 ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); 143 sysbus_init_irq(d, &s->irq); 144 } 145 146 static Property mmio_ide_properties[] = { 147 DEFINE_PROP_UINT32("shift", MMIOState, shift, 0), 148 DEFINE_PROP_END_OF_LIST() 149 }; 150 151 static void mmio_ide_class_init(ObjectClass *oc, void *data) 152 { 153 DeviceClass *dc = DEVICE_CLASS(oc); 154 155 dc->realize = mmio_ide_realizefn; 156 dc->reset = mmio_ide_reset; 157 device_class_set_props(dc, mmio_ide_properties); 158 dc->vmsd = &vmstate_ide_mmio; 159 } 160 161 static const TypeInfo mmio_ide_type_info = { 162 .name = TYPE_MMIO_IDE, 163 .parent = TYPE_SYS_BUS_DEVICE, 164 .instance_size = sizeof(MMIOState), 165 .instance_init = mmio_ide_initfn, 166 .class_init = mmio_ide_class_init, 167 }; 168 169 static void mmio_ide_register_types(void) 170 { 171 type_register_static(&mmio_ide_type_info); 172 } 173 174 void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1) 175 { 176 MMIOState *s = MMIO_IDE(dev); 177 178 if (hd0 != NULL) { 179 ide_create_drive(&s->bus, 0, hd0); 180 } 181 if (hd1 != NULL) { 182 ide_create_drive(&s->bus, 1, hd1); 183 } 184 } 185 186 type_init(mmio_ide_register_types) 187