1 /* 2 * QEMU IDE Emulation: mmio support (for embedded). 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "qemu/module.h" 30 #include "sysemu/dma.h" 31 32 #include "hw/ide/mmio.h" 33 #include "hw/qdev-properties.h" 34 #include "ide-internal.h" 35 36 /***********************************************************/ 37 /* MMIO based ide port 38 * This emulates IDE device connected directly to the CPU bus without 39 * dedicated ide controller, which is often seen on embedded boards. 40 */ 41 42 struct MMIOIDEState { 43 /*< private >*/ 44 SysBusDevice parent_obj; 45 /*< public >*/ 46 47 IDEBus bus; 48 49 uint32_t shift; 50 qemu_irq irq; 51 MemoryRegion iomem1, iomem2; 52 }; 53 54 static void mmio_ide_reset(DeviceState *dev) 55 { 56 MMIOIDEState *s = MMIO_IDE(dev); 57 58 ide_bus_reset(&s->bus); 59 } 60 61 static uint64_t mmio_ide_read(void *opaque, hwaddr addr, 62 unsigned size) 63 { 64 MMIOIDEState *s = opaque; 65 addr >>= s->shift; 66 if (addr & 7) 67 return ide_ioport_read(&s->bus, addr); 68 else 69 return ide_data_readw(&s->bus, 0); 70 } 71 72 static void mmio_ide_write(void *opaque, hwaddr addr, 73 uint64_t val, unsigned size) 74 { 75 MMIOIDEState *s = opaque; 76 addr >>= s->shift; 77 if (addr & 7) 78 ide_ioport_write(&s->bus, addr, val); 79 else 80 ide_data_writew(&s->bus, 0, val); 81 } 82 83 static const MemoryRegionOps mmio_ide_ops = { 84 .read = mmio_ide_read, 85 .write = mmio_ide_write, 86 .endianness = DEVICE_LITTLE_ENDIAN, 87 }; 88 89 static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr, 90 unsigned size) 91 { 92 MMIOIDEState *s = opaque; 93 return ide_status_read(&s->bus, 0); 94 } 95 96 static void mmio_ide_ctrl_write(void *opaque, hwaddr addr, 97 uint64_t val, unsigned size) 98 { 99 MMIOIDEState *s = opaque; 100 ide_ctrl_write(&s->bus, 0, val); 101 } 102 103 static const MemoryRegionOps mmio_ide_cs_ops = { 104 .read = mmio_ide_status_read, 105 .write = mmio_ide_ctrl_write, 106 .endianness = DEVICE_LITTLE_ENDIAN, 107 }; 108 109 static const VMStateDescription vmstate_ide_mmio = { 110 .name = "mmio-ide", 111 .version_id = 3, 112 .minimum_version_id = 0, 113 .fields = (const VMStateField[]) { 114 VMSTATE_IDE_BUS(bus, MMIOIDEState), 115 VMSTATE_IDE_DRIVES(bus.ifs, MMIOIDEState), 116 VMSTATE_END_OF_LIST() 117 } 118 }; 119 120 static void mmio_ide_realizefn(DeviceState *dev, Error **errp) 121 { 122 SysBusDevice *d = SYS_BUS_DEVICE(dev); 123 MMIOIDEState *s = MMIO_IDE(dev); 124 125 ide_bus_init_output_irq(&s->bus, s->irq); 126 127 memory_region_init_io(&s->iomem1, OBJECT(s), &mmio_ide_ops, s, 128 "ide-mmio.1", 16 << s->shift); 129 memory_region_init_io(&s->iomem2, OBJECT(s), &mmio_ide_cs_ops, s, 130 "ide-mmio.2", 2 << s->shift); 131 sysbus_init_mmio(d, &s->iomem1); 132 sysbus_init_mmio(d, &s->iomem2); 133 } 134 135 static void mmio_ide_initfn(Object *obj) 136 { 137 SysBusDevice *d = SYS_BUS_DEVICE(obj); 138 MMIOIDEState *s = MMIO_IDE(obj); 139 140 ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); 141 sysbus_init_irq(d, &s->irq); 142 } 143 144 static Property mmio_ide_properties[] = { 145 DEFINE_PROP_UINT32("shift", MMIOIDEState, shift, 0), 146 DEFINE_PROP_END_OF_LIST() 147 }; 148 149 static void mmio_ide_class_init(ObjectClass *oc, void *data) 150 { 151 DeviceClass *dc = DEVICE_CLASS(oc); 152 153 dc->realize = mmio_ide_realizefn; 154 device_class_set_legacy_reset(dc, mmio_ide_reset); 155 device_class_set_props(dc, mmio_ide_properties); 156 dc->vmsd = &vmstate_ide_mmio; 157 } 158 159 static const TypeInfo mmio_ide_type_info = { 160 .name = TYPE_MMIO_IDE, 161 .parent = TYPE_SYS_BUS_DEVICE, 162 .instance_size = sizeof(MMIOIDEState), 163 .instance_init = mmio_ide_initfn, 164 .class_init = mmio_ide_class_init, 165 }; 166 167 static void mmio_ide_register_types(void) 168 { 169 type_register_static(&mmio_ide_type_info); 170 } 171 172 void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1) 173 { 174 MMIOIDEState *s = MMIO_IDE(dev); 175 176 if (hd0 != NULL) { 177 ide_bus_create_drive(&s->bus, 0, hd0); 178 } 179 if (hd1 != NULL) { 180 ide_bus_create_drive(&s->bus, 1, hd1); 181 } 182 } 183 184 type_init(mmio_ide_register_types) 185