1 /* 2 * QEMU IDE Emulation: mmio support (for embedded). 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/hw.h" 28 #include "hw/sysbus.h" 29 #include "qemu/module.h" 30 #include "sysemu/dma.h" 31 32 #include "hw/ide/internal.h" 33 34 /***********************************************************/ 35 /* MMIO based ide port 36 * This emulates IDE device connected directly to the CPU bus without 37 * dedicated ide controller, which is often seen on embedded boards. 38 */ 39 40 #define TYPE_MMIO_IDE "mmio-ide" 41 #define MMIO_IDE(obj) OBJECT_CHECK(MMIOState, (obj), TYPE_MMIO_IDE) 42 43 typedef struct MMIOIDEState { 44 /*< private >*/ 45 SysBusDevice parent_obj; 46 /*< public >*/ 47 48 IDEBus bus; 49 50 uint32_t shift; 51 qemu_irq irq; 52 MemoryRegion iomem1, iomem2; 53 } MMIOState; 54 55 static void mmio_ide_reset(DeviceState *dev) 56 { 57 MMIOState *s = MMIO_IDE(dev); 58 59 ide_bus_reset(&s->bus); 60 } 61 62 static uint64_t mmio_ide_read(void *opaque, hwaddr addr, 63 unsigned size) 64 { 65 MMIOState *s = opaque; 66 addr >>= s->shift; 67 if (addr & 7) 68 return ide_ioport_read(&s->bus, addr); 69 else 70 return ide_data_readw(&s->bus, 0); 71 } 72 73 static void mmio_ide_write(void *opaque, hwaddr addr, 74 uint64_t val, unsigned size) 75 { 76 MMIOState *s = opaque; 77 addr >>= s->shift; 78 if (addr & 7) 79 ide_ioport_write(&s->bus, addr, val); 80 else 81 ide_data_writew(&s->bus, 0, val); 82 } 83 84 static const MemoryRegionOps mmio_ide_ops = { 85 .read = mmio_ide_read, 86 .write = mmio_ide_write, 87 .endianness = DEVICE_LITTLE_ENDIAN, 88 }; 89 90 static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr, 91 unsigned size) 92 { 93 MMIOState *s= opaque; 94 return ide_status_read(&s->bus, 0); 95 } 96 97 static void mmio_ide_cmd_write(void *opaque, hwaddr addr, 98 uint64_t val, unsigned size) 99 { 100 MMIOState *s = opaque; 101 ide_cmd_write(&s->bus, 0, val); 102 } 103 104 static const MemoryRegionOps mmio_ide_cs_ops = { 105 .read = mmio_ide_status_read, 106 .write = mmio_ide_cmd_write, 107 .endianness = DEVICE_LITTLE_ENDIAN, 108 }; 109 110 static const VMStateDescription vmstate_ide_mmio = { 111 .name = "mmio-ide", 112 .version_id = 3, 113 .minimum_version_id = 0, 114 .fields = (VMStateField[]) { 115 VMSTATE_IDE_BUS(bus, MMIOState), 116 VMSTATE_IDE_DRIVES(bus.ifs, MMIOState), 117 VMSTATE_END_OF_LIST() 118 } 119 }; 120 121 static void mmio_ide_realizefn(DeviceState *dev, Error **errp) 122 { 123 SysBusDevice *d = SYS_BUS_DEVICE(dev); 124 MMIOState *s = MMIO_IDE(dev); 125 126 ide_init2(&s->bus, s->irq); 127 128 memory_region_init_io(&s->iomem1, OBJECT(s), &mmio_ide_ops, s, 129 "ide-mmio.1", 16 << s->shift); 130 memory_region_init_io(&s->iomem2, OBJECT(s), &mmio_ide_cs_ops, s, 131 "ide-mmio.2", 2 << s->shift); 132 sysbus_init_mmio(d, &s->iomem1); 133 sysbus_init_mmio(d, &s->iomem2); 134 } 135 136 static void mmio_ide_initfn(Object *obj) 137 { 138 SysBusDevice *d = SYS_BUS_DEVICE(obj); 139 MMIOState *s = MMIO_IDE(obj); 140 141 ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); 142 sysbus_init_irq(d, &s->irq); 143 } 144 145 static Property mmio_ide_properties[] = { 146 DEFINE_PROP_UINT32("shift", MMIOState, shift, 0), 147 DEFINE_PROP_END_OF_LIST() 148 }; 149 150 static void mmio_ide_class_init(ObjectClass *oc, void *data) 151 { 152 DeviceClass *dc = DEVICE_CLASS(oc); 153 154 dc->realize = mmio_ide_realizefn; 155 dc->reset = mmio_ide_reset; 156 dc->props = mmio_ide_properties; 157 dc->vmsd = &vmstate_ide_mmio; 158 } 159 160 static const TypeInfo mmio_ide_type_info = { 161 .name = TYPE_MMIO_IDE, 162 .parent = TYPE_SYS_BUS_DEVICE, 163 .instance_size = sizeof(MMIOState), 164 .instance_init = mmio_ide_initfn, 165 .class_init = mmio_ide_class_init, 166 }; 167 168 static void mmio_ide_register_types(void) 169 { 170 type_register_static(&mmio_ide_type_info); 171 } 172 173 void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1) 174 { 175 MMIOState *s = MMIO_IDE(dev); 176 177 if (hd0 != NULL) { 178 ide_create_drive(&s->bus, 0, hd0); 179 } 180 if (hd1 != NULL) { 181 ide_create_drive(&s->bus, 1, hd1); 182 } 183 } 184 185 type_init(mmio_ide_register_types) 186