1 /* 2 * QEMU IDE Emulation: mmio support (for embedded). 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include <hw/hw.h> 26 #include "block.h" 27 #include "block_int.h" 28 #include "sysemu.h" 29 #include "dma.h" 30 31 #include <hw/ide/internal.h> 32 33 /***********************************************************/ 34 /* MMIO based ide port 35 * This emulates IDE device connected directly to the CPU bus without 36 * dedicated ide controller, which is often seen on embedded boards. 37 */ 38 39 typedef struct { 40 IDEBus bus; 41 int shift; 42 } MMIOState; 43 44 static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) 45 { 46 MMIOState *s = opaque; 47 addr >>= s->shift; 48 if (addr & 7) 49 return ide_ioport_read(&s->bus, addr); 50 else 51 return ide_data_readw(&s->bus, 0); 52 } 53 54 static void mmio_ide_write (void *opaque, target_phys_addr_t addr, 55 uint32_t val) 56 { 57 MMIOState *s = opaque; 58 addr >>= s->shift; 59 if (addr & 7) 60 ide_ioport_write(&s->bus, addr, val); 61 else 62 ide_data_writew(&s->bus, 0, val); 63 } 64 65 static CPUReadMemoryFunc * const mmio_ide_reads[] = { 66 mmio_ide_read, 67 mmio_ide_read, 68 mmio_ide_read, 69 }; 70 71 static CPUWriteMemoryFunc * const mmio_ide_writes[] = { 72 mmio_ide_write, 73 mmio_ide_write, 74 mmio_ide_write, 75 }; 76 77 static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) 78 { 79 MMIOState *s= opaque; 80 return ide_status_read(&s->bus, 0); 81 } 82 83 static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, 84 uint32_t val) 85 { 86 MMIOState *s = opaque; 87 ide_cmd_write(&s->bus, 0, val); 88 } 89 90 static CPUReadMemoryFunc * const mmio_ide_status[] = { 91 mmio_ide_status_read, 92 mmio_ide_status_read, 93 mmio_ide_status_read, 94 }; 95 96 static CPUWriteMemoryFunc * const mmio_ide_cmd[] = { 97 mmio_ide_cmd_write, 98 mmio_ide_cmd_write, 99 mmio_ide_cmd_write, 100 }; 101 102 static const VMStateDescription vmstate_ide_mmio = { 103 .name = "mmio-ide", 104 .version_id = 3, 105 .minimum_version_id = 0, 106 .minimum_version_id_old = 0, 107 .fields = (VMStateField []) { 108 VMSTATE_IDE_BUS(bus, MMIOState), 109 VMSTATE_IDE_DRIVES(bus.ifs, MMIOState), 110 VMSTATE_END_OF_LIST() 111 } 112 }; 113 114 void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, 115 qemu_irq irq, int shift, 116 DriveInfo *hd0, DriveInfo *hd1) 117 { 118 MMIOState *s = qemu_mallocz(sizeof(MMIOState)); 119 int mem1, mem2; 120 121 ide_init2(&s->bus, hd0, hd1, irq); 122 123 s->shift = shift; 124 125 mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s); 126 mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s); 127 cpu_register_physical_memory(membase, 16 << shift, mem1); 128 cpu_register_physical_memory(membase2, 2 << shift, mem2); 129 vmstate_register(0, &vmstate_ide_mmio, s); 130 } 131 132