1 /* 2 * QEMU IDE Emulation: microdrive (CF / PCMCIA) 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/pcmcia.h" 28 #include "sysemu/dma.h" 29 30 #include "hw/ide/internal.h" 31 32 #define TYPE_MICRODRIVE "microdrive" 33 #define MICRODRIVE(obj) OBJECT_CHECK(MicroDriveState, (obj), TYPE_MICRODRIVE) 34 35 /***********************************************************/ 36 /* CF-ATA Microdrive */ 37 38 #define METADATA_SIZE 0x20 39 40 /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */ 41 42 typedef struct MicroDriveState { 43 /*< private >*/ 44 PCMCIACardState parent_obj; 45 /*< public >*/ 46 47 IDEBus bus; 48 uint32_t attr_base; 49 uint32_t io_base; 50 51 /* Card state */ 52 uint8_t opt; 53 uint8_t stat; 54 uint8_t pins; 55 56 uint8_t ctrl; 57 uint16_t io; 58 uint8_t cycle; 59 } MicroDriveState; 60 61 /* Register bitfields */ 62 enum md_opt { 63 OPT_MODE_MMAP = 0, 64 OPT_MODE_IOMAP16 = 1, 65 OPT_MODE_IOMAP1 = 2, 66 OPT_MODE_IOMAP2 = 3, 67 OPT_MODE = 0x3f, 68 OPT_LEVIREQ = 0x40, 69 OPT_SRESET = 0x80, 70 }; 71 enum md_cstat { 72 STAT_INT = 0x02, 73 STAT_PWRDWN = 0x04, 74 STAT_XE = 0x10, 75 STAT_IOIS8 = 0x20, 76 STAT_SIGCHG = 0x40, 77 STAT_CHANGED = 0x80, 78 }; 79 enum md_pins { 80 PINS_MRDY = 0x02, 81 PINS_CRDY = 0x20, 82 }; 83 enum md_ctrl { 84 CTRL_IEN = 0x02, 85 CTRL_SRST = 0x04, 86 }; 87 88 static inline void md_interrupt_update(MicroDriveState *s) 89 { 90 PCMCIACardState *card = PCMCIA_CARD(s); 91 92 if (card->slot == NULL) { 93 return; 94 } 95 96 qemu_set_irq(card->slot->irq, 97 !(s->stat & STAT_INT) && /* Inverted */ 98 !(s->ctrl & (CTRL_IEN | CTRL_SRST)) && 99 !(s->opt & OPT_SRESET)); 100 } 101 102 static void md_set_irq(void *opaque, int irq, int level) 103 { 104 MicroDriveState *s = opaque; 105 106 if (level) { 107 s->stat |= STAT_INT; 108 } else { 109 s->stat &= ~STAT_INT; 110 } 111 112 md_interrupt_update(s); 113 } 114 115 static void md_reset(DeviceState *dev) 116 { 117 MicroDriveState *s = MICRODRIVE(dev); 118 119 s->opt = OPT_MODE_MMAP; 120 s->stat = 0; 121 s->pins = 0; 122 s->cycle = 0; 123 s->ctrl = 0; 124 ide_bus_reset(&s->bus); 125 } 126 127 static uint8_t md_attr_read(PCMCIACardState *card, uint32_t at) 128 { 129 MicroDriveState *s = MICRODRIVE(card); 130 PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card); 131 132 if (at < s->attr_base) { 133 if (at < pcc->cis_len) { 134 return pcc->cis[at]; 135 } else { 136 return 0x00; 137 } 138 } 139 140 at -= s->attr_base; 141 142 switch (at) { 143 case 0x00: /* Configuration Option Register */ 144 return s->opt; 145 case 0x02: /* Card Configuration Status Register */ 146 if (s->ctrl & CTRL_IEN) { 147 return s->stat & ~STAT_INT; 148 } else { 149 return s->stat; 150 } 151 case 0x04: /* Pin Replacement Register */ 152 return (s->pins & PINS_CRDY) | 0x0c; 153 case 0x06: /* Socket and Copy Register */ 154 return 0x00; 155 #ifdef VERBOSE 156 default: 157 printf("%s: Bad attribute space register %02x\n", __func__, at); 158 #endif 159 } 160 161 return 0; 162 } 163 164 static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value) 165 { 166 MicroDriveState *s = MICRODRIVE(card); 167 168 at -= s->attr_base; 169 170 switch (at) { 171 case 0x00: /* Configuration Option Register */ 172 s->opt = value & 0xcf; 173 if (value & OPT_SRESET) { 174 device_reset(DEVICE(s)); 175 } 176 md_interrupt_update(s); 177 break; 178 case 0x02: /* Card Configuration Status Register */ 179 if ((s->stat ^ value) & STAT_PWRDWN) { 180 s->pins |= PINS_CRDY; 181 } 182 s->stat &= 0x82; 183 s->stat |= value & 0x74; 184 md_interrupt_update(s); 185 /* Word 170 in Identify Device must be equal to STAT_XE */ 186 break; 187 case 0x04: /* Pin Replacement Register */ 188 s->pins &= PINS_CRDY; 189 s->pins |= value & PINS_MRDY; 190 break; 191 case 0x06: /* Socket and Copy Register */ 192 break; 193 default: 194 printf("%s: Bad attribute space register %02x\n", __func__, at); 195 } 196 } 197 198 static uint16_t md_common_read(PCMCIACardState *card, uint32_t at) 199 { 200 MicroDriveState *s = MICRODRIVE(card); 201 IDEState *ifs; 202 uint16_t ret; 203 at -= s->io_base; 204 205 switch (s->opt & OPT_MODE) { 206 case OPT_MODE_MMAP: 207 if ((at & ~0x3ff) == 0x400) { 208 at = 0; 209 } 210 break; 211 case OPT_MODE_IOMAP16: 212 at &= 0xf; 213 break; 214 case OPT_MODE_IOMAP1: 215 if ((at & ~0xf) == 0x3f0) { 216 at -= 0x3e8; 217 } else if ((at & ~0xf) == 0x1f0) { 218 at -= 0x1f0; 219 } 220 break; 221 case OPT_MODE_IOMAP2: 222 if ((at & ~0xf) == 0x370) { 223 at -= 0x368; 224 } else if ((at & ~0xf) == 0x170) { 225 at -= 0x170; 226 } 227 } 228 229 switch (at) { 230 case 0x0: /* Even RD Data */ 231 case 0x8: 232 return ide_data_readw(&s->bus, 0); 233 234 /* TODO: 8-bit accesses */ 235 if (s->cycle) { 236 ret = s->io >> 8; 237 } else { 238 s->io = ide_data_readw(&s->bus, 0); 239 ret = s->io & 0xff; 240 } 241 s->cycle = !s->cycle; 242 return ret; 243 case 0x9: /* Odd RD Data */ 244 return s->io >> 8; 245 case 0xd: /* Error */ 246 return ide_ioport_read(&s->bus, 0x1); 247 case 0xe: /* Alternate Status */ 248 ifs = idebus_active_if(&s->bus); 249 if (ifs->blk) { 250 return ifs->status; 251 } else { 252 return 0; 253 } 254 case 0xf: /* Device Address */ 255 ifs = idebus_active_if(&s->bus); 256 return 0xc2 | ((~ifs->select << 2) & 0x3c); 257 default: 258 return ide_ioport_read(&s->bus, at); 259 } 260 261 return 0; 262 } 263 264 static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value) 265 { 266 MicroDriveState *s = MICRODRIVE(card); 267 at -= s->io_base; 268 269 switch (s->opt & OPT_MODE) { 270 case OPT_MODE_MMAP: 271 if ((at & ~0x3ff) == 0x400) { 272 at = 0; 273 } 274 break; 275 case OPT_MODE_IOMAP16: 276 at &= 0xf; 277 break; 278 case OPT_MODE_IOMAP1: 279 if ((at & ~0xf) == 0x3f0) { 280 at -= 0x3e8; 281 } else if ((at & ~0xf) == 0x1f0) { 282 at -= 0x1f0; 283 } 284 break; 285 case OPT_MODE_IOMAP2: 286 if ((at & ~0xf) == 0x370) { 287 at -= 0x368; 288 } else if ((at & ~0xf) == 0x170) { 289 at -= 0x170; 290 } 291 } 292 293 switch (at) { 294 case 0x0: /* Even WR Data */ 295 case 0x8: 296 ide_data_writew(&s->bus, 0, value); 297 break; 298 299 /* TODO: 8-bit accesses */ 300 if (s->cycle) { 301 ide_data_writew(&s->bus, 0, s->io | (value << 8)); 302 } else { 303 s->io = value & 0xff; 304 } 305 s->cycle = !s->cycle; 306 break; 307 case 0x9: 308 s->io = value & 0xff; 309 s->cycle = !s->cycle; 310 break; 311 case 0xd: /* Features */ 312 ide_ioport_write(&s->bus, 0x1, value); 313 break; 314 case 0xe: /* Device Control */ 315 s->ctrl = value; 316 if (value & CTRL_SRST) { 317 device_reset(DEVICE(s)); 318 } 319 md_interrupt_update(s); 320 break; 321 default: 322 if (s->stat & STAT_PWRDWN) { 323 s->pins |= PINS_CRDY; 324 s->stat &= ~STAT_PWRDWN; 325 } 326 ide_ioport_write(&s->bus, at, value); 327 } 328 } 329 330 static const VMStateDescription vmstate_microdrive = { 331 .name = "microdrive", 332 .version_id = 3, 333 .minimum_version_id = 0, 334 .fields = (VMStateField[]) { 335 VMSTATE_UINT8(opt, MicroDriveState), 336 VMSTATE_UINT8(stat, MicroDriveState), 337 VMSTATE_UINT8(pins, MicroDriveState), 338 VMSTATE_UINT8(ctrl, MicroDriveState), 339 VMSTATE_UINT16(io, MicroDriveState), 340 VMSTATE_UINT8(cycle, MicroDriveState), 341 VMSTATE_IDE_BUS(bus, MicroDriveState), 342 VMSTATE_IDE_DRIVES(bus.ifs, MicroDriveState), 343 VMSTATE_END_OF_LIST() 344 } 345 }; 346 347 static const uint8_t dscm1xxxx_cis[0x14a] = { 348 [0x000] = CISTPL_DEVICE, /* 5V Device Information */ 349 [0x002] = 0x03, /* Tuple length = 4 bytes */ 350 [0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */ 351 [0x006] = 0x01, /* Size = 2K bytes */ 352 [0x008] = CISTPL_ENDMARK, 353 354 [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */ 355 [0x00c] = 0x04, /* Tuple length = 4 byest */ 356 [0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */ 357 [0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */ 358 [0x012] = 0x01, /* Size = 2K bytes */ 359 [0x014] = CISTPL_ENDMARK, 360 361 [0x016] = CISTPL_JEDEC_C, /* JEDEC ID */ 362 [0x018] = 0x02, /* Tuple length = 2 bytes */ 363 [0x01a] = 0xdf, /* PC Card ATA with no Vpp required */ 364 [0x01c] = 0x01, 365 366 [0x01e] = CISTPL_MANFID, /* Manufacture ID */ 367 [0x020] = 0x04, /* Tuple length = 4 bytes */ 368 [0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */ 369 [0x024] = 0x00, 370 [0x026] = 0x00, /* PLMID_CARD = 0000 */ 371 [0x028] = 0x00, 372 373 [0x02a] = CISTPL_VERS_1, /* Level 1 Version */ 374 [0x02c] = 0x12, /* Tuple length = 23 bytes */ 375 [0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */ 376 [0x030] = 0x01, /* Minor Version = 1 */ 377 [0x032] = 'I', 378 [0x034] = 'B', 379 [0x036] = 'M', 380 [0x038] = 0x00, 381 [0x03a] = 'm', 382 [0x03c] = 'i', 383 [0x03e] = 'c', 384 [0x040] = 'r', 385 [0x042] = 'o', 386 [0x044] = 'd', 387 [0x046] = 'r', 388 [0x048] = 'i', 389 [0x04a] = 'v', 390 [0x04c] = 'e', 391 [0x04e] = 0x00, 392 [0x050] = CISTPL_ENDMARK, 393 394 [0x052] = CISTPL_FUNCID, /* Function ID */ 395 [0x054] = 0x02, /* Tuple length = 2 bytes */ 396 [0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */ 397 [0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */ 398 399 [0x05a] = CISTPL_FUNCE, /* Function Extension */ 400 [0x05c] = 0x02, /* Tuple length = 2 bytes */ 401 [0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */ 402 [0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */ 403 404 [0x062] = CISTPL_FUNCE, /* Function Extension */ 405 [0x064] = 0x03, /* Tuple length = 3 bytes */ 406 [0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */ 407 [0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */ 408 [0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */ 409 410 [0x06c] = CISTPL_CONFIG, /* Configuration */ 411 [0x06e] = 0x05, /* Tuple length = 5 bytes */ 412 [0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */ 413 [0x072] = 0x07, /* TPCC_LAST = 7 */ 414 [0x074] = 0x00, /* TPCC_RADR = 0200 */ 415 [0x076] = 0x02, 416 [0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */ 417 418 [0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ 419 [0x07c] = 0x0b, /* Tuple length = 11 bytes */ 420 [0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */ 421 [0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */ 422 [0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */ 423 [0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ 424 [0x086] = 0x55, /* NomV: 5.0 V */ 425 [0x088] = 0x4d, /* MinV: 4.5 V */ 426 [0x08a] = 0x5d, /* MaxV: 5.5 V */ 427 [0x08c] = 0x4e, /* Peakl: 450 mA */ 428 [0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */ 429 [0x090] = 0x00, /* Window descriptor: Window length = 0 */ 430 [0x092] = 0x20, /* TPCE_MI: support power down mode, RW */ 431 432 [0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ 433 [0x096] = 0x06, /* Tuple length = 6 bytes */ 434 [0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */ 435 [0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ 436 [0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ 437 [0x09e] = 0xb5, /* NomV: 3.3 V */ 438 [0x0a0] = 0x1e, 439 [0x0a2] = 0x3e, /* Peakl: 350 mA */ 440 441 [0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ 442 [0x0a6] = 0x0d, /* Tuple length = 13 bytes */ 443 [0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */ 444 [0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ 445 [0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ 446 [0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ 447 [0x0b0] = 0x55, /* NomV: 5.0 V */ 448 [0x0b2] = 0x4d, /* MinV: 4.5 V */ 449 [0x0b4] = 0x5d, /* MaxV: 5.5 V */ 450 [0x0b6] = 0x4e, /* Peakl: 450 mA */ 451 [0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */ 452 [0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */ 453 [0x0bc] = 0xff, /* IRQ0..IRQ7 supported */ 454 [0x0be] = 0xff, /* IRQ8..IRQ15 supported */ 455 [0x0c0] = 0x20, /* TPCE_MI = support power down mode */ 456 457 [0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ 458 [0x0c4] = 0x06, /* Tuple length = 6 bytes */ 459 [0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */ 460 [0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ 461 [0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ 462 [0x0cc] = 0xb5, /* NomV: 3.3 V */ 463 [0x0ce] = 0x1e, 464 [0x0d0] = 0x3e, /* Peakl: 350 mA */ 465 466 [0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ 467 [0x0d4] = 0x12, /* Tuple length = 18 bytes */ 468 [0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */ 469 [0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ 470 [0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ 471 [0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ 472 [0x0de] = 0x55, /* NomV: 5.0 V */ 473 [0x0e0] = 0x4d, /* MinV: 4.5 V */ 474 [0x0e2] = 0x5d, /* MaxV: 5.5 V */ 475 [0x0e4] = 0x4e, /* Peakl: 450 mA */ 476 [0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */ 477 [0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */ 478 [0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */ 479 [0x0ec] = 0x01, 480 [0x0ee] = 0x07, /* Address block length = 8 */ 481 [0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */ 482 [0x0f2] = 0x03, 483 [0x0f4] = 0x01, /* Address block length = 2 */ 484 [0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */ 485 [0x0f8] = 0x20, /* TPCE_MI = support power down mode */ 486 487 [0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ 488 [0x0fc] = 0x06, /* Tuple length = 6 bytes */ 489 [0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */ 490 [0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ 491 [0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ 492 [0x104] = 0xb5, /* NomV: 3.3 V */ 493 [0x106] = 0x1e, 494 [0x108] = 0x3e, /* Peakl: 350 mA */ 495 496 [0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ 497 [0x10c] = 0x12, /* Tuple length = 18 bytes */ 498 [0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */ 499 [0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ 500 [0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ 501 [0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ 502 [0x116] = 0x55, /* NomV: 5.0 V */ 503 [0x118] = 0x4d, /* MinV: 4.5 V */ 504 [0x11a] = 0x5d, /* MaxV: 5.5 V */ 505 [0x11c] = 0x4e, /* Peakl: 450 mA */ 506 [0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */ 507 [0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */ 508 [0x122] = 0x70, /* Field 1 address = 0x0170 */ 509 [0x124] = 0x01, 510 [0x126] = 0x07, /* Address block length = 8 */ 511 [0x128] = 0x76, /* Field 2 address = 0x0376 */ 512 [0x12a] = 0x03, 513 [0x12c] = 0x01, /* Address block length = 2 */ 514 [0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */ 515 [0x130] = 0x20, /* TPCE_MI = support power down mode */ 516 517 [0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ 518 [0x134] = 0x06, /* Tuple length = 6 bytes */ 519 [0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */ 520 [0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ 521 [0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ 522 [0x13c] = 0xb5, /* NomV: 3.3 V */ 523 [0x13e] = 0x1e, 524 [0x140] = 0x3e, /* Peakl: 350 mA */ 525 526 [0x142] = CISTPL_NO_LINK, /* No Link */ 527 [0x144] = 0x00, /* Tuple length = 0 bytes */ 528 529 [0x146] = CISTPL_END, /* Tuple End */ 530 }; 531 532 #define TYPE_DSCM1XXXX "dscm1xxxx" 533 534 static int dscm1xxxx_attach(PCMCIACardState *card) 535 { 536 MicroDriveState *md = MICRODRIVE(card); 537 PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card); 538 539 md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8); 540 md->io_base = 0x0; 541 542 device_reset(DEVICE(md)); 543 md_interrupt_update(md); 544 545 return 0; 546 } 547 548 static int dscm1xxxx_detach(PCMCIACardState *card) 549 { 550 MicroDriveState *md = MICRODRIVE(card); 551 552 device_reset(DEVICE(md)); 553 return 0; 554 } 555 556 PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo) 557 { 558 MicroDriveState *md; 559 560 md = MICRODRIVE(object_new(TYPE_DSCM1XXXX)); 561 qdev_init_nofail(DEVICE(md)); 562 563 if (dinfo != NULL) { 564 ide_create_drive(&md->bus, 0, dinfo); 565 } 566 md->bus.ifs[0].drive_kind = IDE_CFATA; 567 md->bus.ifs[0].mdata_size = METADATA_SIZE; 568 md->bus.ifs[0].mdata_storage = g_malloc0(METADATA_SIZE); 569 570 return PCMCIA_CARD(md); 571 } 572 573 static void dscm1xxxx_class_init(ObjectClass *oc, void *data) 574 { 575 PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc); 576 DeviceClass *dc = DEVICE_CLASS(oc); 577 578 pcc->cis = dscm1xxxx_cis; 579 pcc->cis_len = sizeof(dscm1xxxx_cis); 580 581 pcc->attach = dscm1xxxx_attach; 582 pcc->detach = dscm1xxxx_detach; 583 /* Reason: Needs to be wired-up in code, see dscm1xxxx_init() */ 584 dc->user_creatable = false; 585 } 586 587 static const TypeInfo dscm1xxxx_type_info = { 588 .name = TYPE_DSCM1XXXX, 589 .parent = TYPE_MICRODRIVE, 590 .class_init = dscm1xxxx_class_init, 591 }; 592 593 static void microdrive_realize(DeviceState *dev, Error **errp) 594 { 595 MicroDriveState *md = MICRODRIVE(dev); 596 597 ide_init2(&md->bus, qemu_allocate_irq(md_set_irq, md, 0)); 598 } 599 600 static void microdrive_init(Object *obj) 601 { 602 MicroDriveState *md = MICRODRIVE(obj); 603 604 ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1); 605 } 606 607 static void microdrive_class_init(ObjectClass *oc, void *data) 608 { 609 DeviceClass *dc = DEVICE_CLASS(oc); 610 PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc); 611 612 pcc->attr_read = md_attr_read; 613 pcc->attr_write = md_attr_write; 614 pcc->common_read = md_common_read; 615 pcc->common_write = md_common_write; 616 pcc->io_read = md_common_read; 617 pcc->io_write = md_common_write; 618 619 dc->realize = microdrive_realize; 620 dc->reset = md_reset; 621 dc->vmsd = &vmstate_microdrive; 622 } 623 624 static const TypeInfo microdrive_type_info = { 625 .name = TYPE_MICRODRIVE, 626 .parent = TYPE_PCMCIA_CARD, 627 .instance_size = sizeof(MicroDriveState), 628 .instance_init = microdrive_init, 629 .abstract = true, 630 .class_init = microdrive_class_init, 631 }; 632 633 static void microdrive_register_types(void) 634 { 635 type_register_static(µdrive_type_info); 636 type_register_static(&dscm1xxxx_type_info); 637 } 638 639 type_init(microdrive_register_types) 640