1 /* 2 * QEMU IDE Emulation: MacIO support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/ppc/mac.h" 28 #include "hw/ppc/mac_dbdma.h" 29 #include "sysemu/block-backend.h" 30 #include "sysemu/dma.h" 31 32 #include "hw/ide/internal.h" 33 34 /* debug MACIO */ 35 // #define DEBUG_MACIO 36 37 #ifdef DEBUG_MACIO 38 static const int debug_macio = 1; 39 #else 40 static const int debug_macio = 0; 41 #endif 42 43 #define MACIO_DPRINTF(fmt, ...) do { \ 44 if (debug_macio) { \ 45 printf(fmt , ## __VA_ARGS__); \ 46 } \ 47 } while (0) 48 49 50 /***********************************************************/ 51 /* MacIO based PowerPC IDE */ 52 53 #define MACIO_PAGE_SIZE 4096 54 55 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret) 56 { 57 DBDMA_io *io = opaque; 58 MACIOIDEState *m = io->opaque; 59 IDEState *s = idebus_active_if(&m->bus); 60 int64_t offset; 61 62 MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n"); 63 64 if (ret < 0) { 65 MACIO_DPRINTF("DMA error: %d\n", ret); 66 qemu_sglist_destroy(&s->sg); 67 ide_atapi_io_error(s, ret); 68 goto done; 69 } 70 71 if (!m->dma_active) { 72 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n", 73 s->nsector, io->len, s->status); 74 /* data not ready yet, wait for the channel to get restarted */ 75 io->processing = false; 76 return; 77 } 78 79 if (s->io_buffer_size <= 0) { 80 MACIO_DPRINTF("End of IDE transfer\n"); 81 qemu_sglist_destroy(&s->sg); 82 ide_atapi_cmd_ok(s); 83 m->dma_active = false; 84 goto done; 85 } 86 87 if (io->len == 0) { 88 MACIO_DPRINTF("End of DMA transfer\n"); 89 goto done; 90 } 91 92 if (s->lba == -1) { 93 /* Non-block ATAPI transfer - just copy to RAM */ 94 s->io_buffer_size = MIN(s->io_buffer_size, io->len); 95 dma_memory_write(&address_space_memory, io->addr, s->io_buffer, 96 s->io_buffer_size); 97 io->len = 0; 98 ide_atapi_cmd_ok(s); 99 m->dma_active = false; 100 goto done; 101 } 102 103 /* Calculate current offset */ 104 offset = ((int64_t)s->lba << 11) + s->io_buffer_index; 105 106 qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1, 107 &address_space_memory); 108 qemu_sglist_add(&s->sg, io->addr, io->len); 109 s->io_buffer_size -= io->len; 110 s->io_buffer_index += io->len; 111 io->len = 0; 112 113 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1, 114 pmac_ide_atapi_transfer_cb, io); 115 return; 116 117 done: 118 dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len, 119 io->dir, io->dma_len); 120 121 if (ret < 0) { 122 block_acct_failed(blk_get_stats(s->blk), &s->acct); 123 } else { 124 block_acct_done(blk_get_stats(s->blk), &s->acct); 125 } 126 127 ide_set_inactive(s, false); 128 io->dma_end(opaque); 129 } 130 131 static void pmac_ide_transfer_cb(void *opaque, int ret) 132 { 133 DBDMA_io *io = opaque; 134 MACIOIDEState *m = io->opaque; 135 IDEState *s = idebus_active_if(&m->bus); 136 int64_t offset; 137 138 MACIO_DPRINTF("pmac_ide_transfer_cb\n"); 139 140 if (ret < 0) { 141 MACIO_DPRINTF("DMA error: %d\n", ret); 142 qemu_sglist_destroy(&s->sg); 143 ide_dma_error(s); 144 goto done; 145 } 146 147 if (!m->dma_active) { 148 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n", 149 s->nsector, io->len, s->status); 150 /* data not ready yet, wait for the channel to get restarted */ 151 io->processing = false; 152 return; 153 } 154 155 if (s->io_buffer_size <= 0) { 156 MACIO_DPRINTF("End of IDE transfer\n"); 157 qemu_sglist_destroy(&s->sg); 158 s->status = READY_STAT | SEEK_STAT; 159 ide_set_irq(s->bus); 160 m->dma_active = false; 161 goto done; 162 } 163 164 if (io->len == 0) { 165 MACIO_DPRINTF("End of DMA transfer\n"); 166 goto done; 167 } 168 169 /* Calculate number of sectors */ 170 offset = (ide_get_sector(s) << 9) + s->io_buffer_index; 171 172 qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1, 173 &address_space_memory); 174 qemu_sglist_add(&s->sg, io->addr, io->len); 175 s->io_buffer_size -= io->len; 176 s->io_buffer_index += io->len; 177 io->len = 0; 178 179 switch (s->dma_cmd) { 180 case IDE_DMA_READ: 181 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1, 182 pmac_ide_atapi_transfer_cb, io); 183 break; 184 case IDE_DMA_WRITE: 185 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset, 0x1, 186 pmac_ide_transfer_cb, io); 187 break; 188 case IDE_DMA_TRIM: 189 s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk), &s->sg, 190 offset, 0x1, ide_issue_trim, s->blk, 191 pmac_ide_transfer_cb, io, 192 DMA_DIRECTION_TO_DEVICE); 193 break; 194 default: 195 abort(); 196 } 197 198 return; 199 200 done: 201 dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len, 202 io->dir, io->dma_len); 203 204 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { 205 if (ret < 0) { 206 block_acct_failed(blk_get_stats(s->blk), &s->acct); 207 } else { 208 block_acct_done(blk_get_stats(s->blk), &s->acct); 209 } 210 } 211 212 ide_set_inactive(s, false); 213 io->dma_end(opaque); 214 } 215 216 static void pmac_ide_transfer(DBDMA_io *io) 217 { 218 MACIOIDEState *m = io->opaque; 219 IDEState *s = idebus_active_if(&m->bus); 220 221 MACIO_DPRINTF("\n"); 222 223 if (s->drive_kind == IDE_CD) { 224 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len, 225 BLOCK_ACCT_READ); 226 227 pmac_ide_atapi_transfer_cb(io, 0); 228 return; 229 } 230 231 switch (s->dma_cmd) { 232 case IDE_DMA_READ: 233 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len, 234 BLOCK_ACCT_READ); 235 break; 236 case IDE_DMA_WRITE: 237 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len, 238 BLOCK_ACCT_WRITE); 239 break; 240 default: 241 break; 242 } 243 244 pmac_ide_transfer_cb(io, 0); 245 } 246 247 static void pmac_ide_flush(DBDMA_io *io) 248 { 249 MACIOIDEState *m = io->opaque; 250 IDEState *s = idebus_active_if(&m->bus); 251 252 if (s->bus->dma->aiocb) { 253 blk_drain(s->blk); 254 } 255 } 256 257 /* PowerMac IDE memory IO */ 258 static void pmac_ide_writeb (void *opaque, 259 hwaddr addr, uint32_t val) 260 { 261 MACIOIDEState *d = opaque; 262 263 addr = (addr & 0xFFF) >> 4; 264 switch (addr) { 265 case 1 ... 7: 266 ide_ioport_write(&d->bus, addr, val); 267 break; 268 case 8: 269 case 22: 270 ide_cmd_write(&d->bus, 0, val); 271 break; 272 default: 273 break; 274 } 275 } 276 277 static uint32_t pmac_ide_readb (void *opaque,hwaddr addr) 278 { 279 uint8_t retval; 280 MACIOIDEState *d = opaque; 281 282 addr = (addr & 0xFFF) >> 4; 283 switch (addr) { 284 case 1 ... 7: 285 retval = ide_ioport_read(&d->bus, addr); 286 break; 287 case 8: 288 case 22: 289 retval = ide_status_read(&d->bus, 0); 290 break; 291 default: 292 retval = 0xFF; 293 break; 294 } 295 return retval; 296 } 297 298 static void pmac_ide_writew (void *opaque, 299 hwaddr addr, uint32_t val) 300 { 301 MACIOIDEState *d = opaque; 302 303 addr = (addr & 0xFFF) >> 4; 304 val = bswap16(val); 305 if (addr == 0) { 306 ide_data_writew(&d->bus, 0, val); 307 } 308 } 309 310 static uint32_t pmac_ide_readw (void *opaque,hwaddr addr) 311 { 312 uint16_t retval; 313 MACIOIDEState *d = opaque; 314 315 addr = (addr & 0xFFF) >> 4; 316 if (addr == 0) { 317 retval = ide_data_readw(&d->bus, 0); 318 } else { 319 retval = 0xFFFF; 320 } 321 retval = bswap16(retval); 322 return retval; 323 } 324 325 static void pmac_ide_writel (void *opaque, 326 hwaddr addr, uint32_t val) 327 { 328 MACIOIDEState *d = opaque; 329 330 addr = (addr & 0xFFF) >> 4; 331 val = bswap32(val); 332 if (addr == 0) { 333 ide_data_writel(&d->bus, 0, val); 334 } 335 } 336 337 static uint32_t pmac_ide_readl (void *opaque,hwaddr addr) 338 { 339 uint32_t retval; 340 MACIOIDEState *d = opaque; 341 342 addr = (addr & 0xFFF) >> 4; 343 if (addr == 0) { 344 retval = ide_data_readl(&d->bus, 0); 345 } else { 346 retval = 0xFFFFFFFF; 347 } 348 retval = bswap32(retval); 349 return retval; 350 } 351 352 static const MemoryRegionOps pmac_ide_ops = { 353 .old_mmio = { 354 .write = { 355 pmac_ide_writeb, 356 pmac_ide_writew, 357 pmac_ide_writel, 358 }, 359 .read = { 360 pmac_ide_readb, 361 pmac_ide_readw, 362 pmac_ide_readl, 363 }, 364 }, 365 .endianness = DEVICE_NATIVE_ENDIAN, 366 }; 367 368 static const VMStateDescription vmstate_pmac = { 369 .name = "ide", 370 .version_id = 4, 371 .minimum_version_id = 0, 372 .fields = (VMStateField[]) { 373 VMSTATE_IDE_BUS(bus, MACIOIDEState), 374 VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState), 375 VMSTATE_BOOL(dma_active, MACIOIDEState), 376 VMSTATE_END_OF_LIST() 377 } 378 }; 379 380 static void macio_ide_reset(DeviceState *dev) 381 { 382 MACIOIDEState *d = MACIO_IDE(dev); 383 384 ide_bus_reset(&d->bus); 385 } 386 387 static int ide_nop_int(IDEDMA *dma, int x) 388 { 389 return 0; 390 } 391 392 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l) 393 { 394 return 0; 395 } 396 397 static void ide_dbdma_start(IDEDMA *dma, IDEState *s, 398 BlockCompletionFunc *cb) 399 { 400 MACIOIDEState *m = container_of(dma, MACIOIDEState, dma); 401 402 s->io_buffer_index = 0; 403 if (s->drive_kind == IDE_CD) { 404 s->io_buffer_size = s->packet_transfer_size; 405 } else { 406 s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE; 407 } 408 409 MACIO_DPRINTF("\n\n------------ IDE transfer\n"); 410 MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n", 411 s->io_buffer_size, s->io_buffer_index); 412 MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size); 413 MACIO_DPRINTF("-------------------------\n"); 414 415 m->dma_active = true; 416 DBDMA_kick(m->dbdma); 417 } 418 419 static const IDEDMAOps dbdma_ops = { 420 .start_dma = ide_dbdma_start, 421 .prepare_buf = ide_nop_int32, 422 .rw_buf = ide_nop_int, 423 }; 424 425 static void macio_ide_realizefn(DeviceState *dev, Error **errp) 426 { 427 MACIOIDEState *s = MACIO_IDE(dev); 428 429 ide_init2(&s->bus, s->irq); 430 431 /* Register DMA callbacks */ 432 s->dma.ops = &dbdma_ops; 433 s->bus.dma = &s->dma; 434 } 435 436 static void macio_ide_initfn(Object *obj) 437 { 438 SysBusDevice *d = SYS_BUS_DEVICE(obj); 439 MACIOIDEState *s = MACIO_IDE(obj); 440 441 ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); 442 memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000); 443 sysbus_init_mmio(d, &s->mem); 444 sysbus_init_irq(d, &s->irq); 445 sysbus_init_irq(d, &s->dma_irq); 446 } 447 448 static void macio_ide_class_init(ObjectClass *oc, void *data) 449 { 450 DeviceClass *dc = DEVICE_CLASS(oc); 451 452 dc->realize = macio_ide_realizefn; 453 dc->reset = macio_ide_reset; 454 dc->vmsd = &vmstate_pmac; 455 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 456 } 457 458 static const TypeInfo macio_ide_type_info = { 459 .name = TYPE_MACIO_IDE, 460 .parent = TYPE_SYS_BUS_DEVICE, 461 .instance_size = sizeof(MACIOIDEState), 462 .instance_init = macio_ide_initfn, 463 .class_init = macio_ide_class_init, 464 }; 465 466 static void macio_ide_register_types(void) 467 { 468 type_register_static(&macio_ide_type_info); 469 } 470 471 /* hd_table must contain 2 block drivers */ 472 void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table) 473 { 474 int i; 475 476 for (i = 0; i < 2; i++) { 477 if (hd_table[i]) { 478 ide_create_drive(&s->bus, i, hd_table[i]); 479 } 480 } 481 } 482 483 void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel) 484 { 485 s->dbdma = dbdma; 486 DBDMA_register_channel(dbdma, channel, s->dma_irq, 487 pmac_ide_transfer, pmac_ide_flush, s); 488 } 489 490 type_init(macio_ide_register_types) 491