xref: /openbmc/qemu/hw/ide/macio.c (revision 2d7fedeb)
1 /*
2  * QEMU IDE Emulation: MacIO support.
3  *
4  * Copyright (c) 2003 Fabrice Bellard
5  * Copyright (c) 2006 Openedhand Ltd.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "hw/ppc/mac.h"
28 #include "hw/ppc/mac_dbdma.h"
29 #include "sysemu/block-backend.h"
30 #include "sysemu/dma.h"
31 
32 #include <hw/ide/internal.h>
33 
34 /* debug MACIO */
35 // #define DEBUG_MACIO
36 
37 #ifdef DEBUG_MACIO
38 static const int debug_macio = 1;
39 #else
40 static const int debug_macio = 0;
41 #endif
42 
43 #define MACIO_DPRINTF(fmt, ...) do { \
44         if (debug_macio) { \
45             printf(fmt , ## __VA_ARGS__); \
46         } \
47     } while (0)
48 
49 
50 /***********************************************************/
51 /* MacIO based PowerPC IDE */
52 
53 #define MACIO_PAGE_SIZE 4096
54 
55 /*
56  * Unaligned DMA read/write access functions required for OS X/Darwin which
57  * don't perform DMA transactions on sector boundaries. These functions are
58  * modelled on bdrv_co_preadv()/bdrv_co_pwritev() and so should be easy to
59  * remove if the unaligned block APIs are ever exposed.
60  */
61 
62 static void pmac_dma_read(BlockBackend *blk,
63                           int64_t offset, unsigned int bytes,
64                           void (*cb)(void *opaque, int ret), void *opaque)
65 {
66     DBDMA_io *io = opaque;
67     MACIOIDEState *m = io->opaque;
68     IDEState *s = idebus_active_if(&m->bus);
69     dma_addr_t dma_addr, dma_len;
70     void *mem;
71     int64_t sector_num;
72     int nsector;
73     uint64_t align = BDRV_SECTOR_SIZE;
74     size_t head_bytes, tail_bytes;
75 
76     qemu_iovec_destroy(&io->iov);
77     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
78 
79     sector_num = (offset >> 9);
80     nsector = (io->len >> 9);
81 
82     MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): "
83                   "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
84                   sector_num, nsector);
85 
86     dma_addr = io->addr;
87     dma_len = io->len;
88     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
89                          DMA_DIRECTION_FROM_DEVICE);
90 
91     if (offset & (align - 1)) {
92         head_bytes = offset & (align - 1);
93 
94         MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", "
95                       "discarding %zu bytes\n", sector_num, head_bytes);
96 
97         qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
98 
99         bytes += offset & (align - 1);
100         offset = offset & ~(align - 1);
101     }
102 
103     qemu_iovec_add(&io->iov, mem, io->len);
104 
105     if ((offset + bytes) & (align - 1)) {
106         tail_bytes = (offset + bytes) & (align - 1);
107 
108         MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", "
109                       "discarding bytes %zu\n", sector_num, tail_bytes);
110 
111         qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes);
112         bytes = ROUND_UP(bytes, align);
113     }
114 
115     s->io_buffer_size -= io->len;
116     s->io_buffer_index += io->len;
117 
118     io->len = 0;
119 
120     MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 "  "
121                   "nsector: %x\n", (offset >> 9), (bytes >> 9));
122 
123     s->bus->dma->aiocb = blk_aio_preadv(blk, offset, &io->iov, 0, cb, io);
124 }
125 
126 static void pmac_dma_write(BlockBackend *blk,
127                          int64_t offset, int bytes,
128                          void (*cb)(void *opaque, int ret), void *opaque)
129 {
130     DBDMA_io *io = opaque;
131     MACIOIDEState *m = io->opaque;
132     IDEState *s = idebus_active_if(&m->bus);
133     dma_addr_t dma_addr, dma_len;
134     void *mem;
135     int64_t sector_num;
136     int nsector;
137     uint64_t align = BDRV_SECTOR_SIZE;
138     size_t head_bytes, tail_bytes;
139     bool unaligned_head = false, unaligned_tail = false;
140 
141     qemu_iovec_destroy(&io->iov);
142     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
143 
144     sector_num = (offset >> 9);
145     nsector = (io->len >> 9);
146 
147     MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): "
148                   "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
149                   sector_num, nsector);
150 
151     dma_addr = io->addr;
152     dma_len = io->len;
153     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
154                          DMA_DIRECTION_TO_DEVICE);
155 
156     if (offset & (align - 1)) {
157         head_bytes = offset & (align - 1);
158         sector_num = ((offset & ~(align - 1)) >> 9);
159 
160         MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
161                       PRId64 "\n", sector_num);
162 
163         blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align);
164 
165         qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
166         qemu_iovec_add(&io->iov, mem, io->len);
167 
168         bytes += offset & (align - 1);
169         offset = offset & ~(align - 1);
170 
171         unaligned_head = true;
172     }
173 
174     if ((offset + bytes) & (align - 1)) {
175         tail_bytes = (offset + bytes) & (align - 1);
176         sector_num = (((offset + bytes) & ~(align - 1)) >> 9);
177 
178         MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
179                       PRId64 "\n", sector_num);
180 
181         blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align);
182 
183         if (!unaligned_head) {
184             qemu_iovec_add(&io->iov, mem, io->len);
185         }
186 
187         qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes,
188                        align - tail_bytes);
189 
190         bytes = ROUND_UP(bytes, align);
191 
192         unaligned_tail = true;
193     }
194 
195     if (!unaligned_head && !unaligned_tail) {
196         qemu_iovec_add(&io->iov, mem, io->len);
197     }
198 
199     s->io_buffer_size -= io->len;
200     s->io_buffer_index += io->len;
201 
202     io->len = 0;
203 
204     MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 "  "
205                   "nsector: %x\n", (offset >> 9), (bytes >> 9));
206 
207     s->bus->dma->aiocb = blk_aio_pwritev(blk, offset, &io->iov, 0, cb, io);
208 }
209 
210 static void pmac_dma_trim(BlockBackend *blk,
211                         int64_t offset, int bytes,
212                         void (*cb)(void *opaque, int ret), void *opaque)
213 {
214     DBDMA_io *io = opaque;
215     MACIOIDEState *m = io->opaque;
216     IDEState *s = idebus_active_if(&m->bus);
217     dma_addr_t dma_addr, dma_len;
218     void *mem;
219 
220     qemu_iovec_destroy(&io->iov);
221     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
222 
223     dma_addr = io->addr;
224     dma_len = io->len;
225     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
226                          DMA_DIRECTION_TO_DEVICE);
227 
228     qemu_iovec_add(&io->iov, mem, io->len);
229     s->io_buffer_size -= io->len;
230     s->io_buffer_index += io->len;
231     io->len = 0;
232 
233     s->bus->dma->aiocb = ide_issue_trim(offset, &io->iov, cb, io, blk);
234 }
235 
236 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
237 {
238     DBDMA_io *io = opaque;
239     MACIOIDEState *m = io->opaque;
240     IDEState *s = idebus_active_if(&m->bus);
241     int64_t offset;
242 
243     MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
244 
245     if (ret < 0) {
246         MACIO_DPRINTF("DMA error: %d\n", ret);
247         ide_atapi_io_error(s, ret);
248         goto done;
249     }
250 
251     if (!m->dma_active) {
252         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
253                       s->nsector, io->len, s->status);
254         /* data not ready yet, wait for the channel to get restarted */
255         io->processing = false;
256         return;
257     }
258 
259     if (s->io_buffer_size <= 0) {
260         MACIO_DPRINTF("End of IDE transfer\n");
261         ide_atapi_cmd_ok(s);
262         m->dma_active = false;
263         goto done;
264     }
265 
266     if (io->len == 0) {
267         MACIO_DPRINTF("End of DMA transfer\n");
268         goto done;
269     }
270 
271     if (s->lba == -1) {
272         /* Non-block ATAPI transfer - just copy to RAM */
273         s->io_buffer_size = MIN(s->io_buffer_size, io->len);
274         dma_memory_write(&address_space_memory, io->addr, s->io_buffer,
275                          s->io_buffer_size);
276         ide_atapi_cmd_ok(s);
277         m->dma_active = false;
278         goto done;
279     }
280 
281     /* Calculate current offset */
282     offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
283 
284     pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io);
285     return;
286 
287 done:
288     if (ret < 0) {
289         block_acct_failed(blk_get_stats(s->blk), &s->acct);
290     } else {
291         block_acct_done(blk_get_stats(s->blk), &s->acct);
292     }
293 
294     ide_set_inactive(s, false);
295     io->dma_end(opaque);
296 }
297 
298 static void pmac_ide_transfer_cb(void *opaque, int ret)
299 {
300     DBDMA_io *io = opaque;
301     MACIOIDEState *m = io->opaque;
302     IDEState *s = idebus_active_if(&m->bus);
303     int64_t offset;
304 
305     MACIO_DPRINTF("pmac_ide_transfer_cb\n");
306 
307     if (ret < 0) {
308         MACIO_DPRINTF("DMA error: %d\n", ret);
309         ide_dma_error(s);
310         goto done;
311     }
312 
313     if (!m->dma_active) {
314         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
315                       s->nsector, io->len, s->status);
316         /* data not ready yet, wait for the channel to get restarted */
317         io->processing = false;
318         return;
319     }
320 
321     if (s->io_buffer_size <= 0) {
322         MACIO_DPRINTF("End of IDE transfer\n");
323         s->status = READY_STAT | SEEK_STAT;
324         ide_set_irq(s->bus);
325         m->dma_active = false;
326         goto done;
327     }
328 
329     if (io->len == 0) {
330         MACIO_DPRINTF("End of DMA transfer\n");
331         goto done;
332     }
333 
334     /* Calculate number of sectors */
335     offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
336 
337     switch (s->dma_cmd) {
338     case IDE_DMA_READ:
339         pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
340         break;
341     case IDE_DMA_WRITE:
342         pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
343         break;
344     case IDE_DMA_TRIM:
345         pmac_dma_trim(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
346         break;
347     default:
348         abort();
349     }
350 
351     return;
352 
353 done:
354     if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
355         if (ret < 0) {
356             block_acct_failed(blk_get_stats(s->blk), &s->acct);
357         } else {
358             block_acct_done(blk_get_stats(s->blk), &s->acct);
359         }
360     }
361 
362     ide_set_inactive(s, false);
363     io->dma_end(opaque);
364 }
365 
366 static void pmac_ide_transfer(DBDMA_io *io)
367 {
368     MACIOIDEState *m = io->opaque;
369     IDEState *s = idebus_active_if(&m->bus);
370 
371     MACIO_DPRINTF("\n");
372 
373     if (s->drive_kind == IDE_CD) {
374         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
375                          BLOCK_ACCT_READ);
376 
377         pmac_ide_atapi_transfer_cb(io, 0);
378         return;
379     }
380 
381     switch (s->dma_cmd) {
382     case IDE_DMA_READ:
383         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
384                          BLOCK_ACCT_READ);
385         break;
386     case IDE_DMA_WRITE:
387         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
388                          BLOCK_ACCT_WRITE);
389         break;
390     default:
391         break;
392     }
393 
394     pmac_ide_transfer_cb(io, 0);
395 }
396 
397 static void pmac_ide_flush(DBDMA_io *io)
398 {
399     MACIOIDEState *m = io->opaque;
400     IDEState *s = idebus_active_if(&m->bus);
401 
402     if (s->bus->dma->aiocb) {
403         blk_drain_all();
404     }
405 }
406 
407 /* PowerMac IDE memory IO */
408 static void pmac_ide_writeb (void *opaque,
409                              hwaddr addr, uint32_t val)
410 {
411     MACIOIDEState *d = opaque;
412 
413     addr = (addr & 0xFFF) >> 4;
414     switch (addr) {
415     case 1 ... 7:
416         ide_ioport_write(&d->bus, addr, val);
417         break;
418     case 8:
419     case 22:
420         ide_cmd_write(&d->bus, 0, val);
421         break;
422     default:
423         break;
424     }
425 }
426 
427 static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
428 {
429     uint8_t retval;
430     MACIOIDEState *d = opaque;
431 
432     addr = (addr & 0xFFF) >> 4;
433     switch (addr) {
434     case 1 ... 7:
435         retval = ide_ioport_read(&d->bus, addr);
436         break;
437     case 8:
438     case 22:
439         retval = ide_status_read(&d->bus, 0);
440         break;
441     default:
442         retval = 0xFF;
443         break;
444     }
445     return retval;
446 }
447 
448 static void pmac_ide_writew (void *opaque,
449                              hwaddr addr, uint32_t val)
450 {
451     MACIOIDEState *d = opaque;
452 
453     addr = (addr & 0xFFF) >> 4;
454     val = bswap16(val);
455     if (addr == 0) {
456         ide_data_writew(&d->bus, 0, val);
457     }
458 }
459 
460 static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
461 {
462     uint16_t retval;
463     MACIOIDEState *d = opaque;
464 
465     addr = (addr & 0xFFF) >> 4;
466     if (addr == 0) {
467         retval = ide_data_readw(&d->bus, 0);
468     } else {
469         retval = 0xFFFF;
470     }
471     retval = bswap16(retval);
472     return retval;
473 }
474 
475 static void pmac_ide_writel (void *opaque,
476                              hwaddr addr, uint32_t val)
477 {
478     MACIOIDEState *d = opaque;
479 
480     addr = (addr & 0xFFF) >> 4;
481     val = bswap32(val);
482     if (addr == 0) {
483         ide_data_writel(&d->bus, 0, val);
484     }
485 }
486 
487 static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
488 {
489     uint32_t retval;
490     MACIOIDEState *d = opaque;
491 
492     addr = (addr & 0xFFF) >> 4;
493     if (addr == 0) {
494         retval = ide_data_readl(&d->bus, 0);
495     } else {
496         retval = 0xFFFFFFFF;
497     }
498     retval = bswap32(retval);
499     return retval;
500 }
501 
502 static const MemoryRegionOps pmac_ide_ops = {
503     .old_mmio = {
504         .write = {
505             pmac_ide_writeb,
506             pmac_ide_writew,
507             pmac_ide_writel,
508         },
509         .read = {
510             pmac_ide_readb,
511             pmac_ide_readw,
512             pmac_ide_readl,
513         },
514     },
515     .endianness = DEVICE_NATIVE_ENDIAN,
516 };
517 
518 static const VMStateDescription vmstate_pmac = {
519     .name = "ide",
520     .version_id = 4,
521     .minimum_version_id = 0,
522     .fields = (VMStateField[]) {
523         VMSTATE_IDE_BUS(bus, MACIOIDEState),
524         VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
525         VMSTATE_BOOL(dma_active, MACIOIDEState),
526         VMSTATE_END_OF_LIST()
527     }
528 };
529 
530 static void macio_ide_reset(DeviceState *dev)
531 {
532     MACIOIDEState *d = MACIO_IDE(dev);
533 
534     ide_bus_reset(&d->bus);
535 }
536 
537 static int ide_nop_int(IDEDMA *dma, int x)
538 {
539     return 0;
540 }
541 
542 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
543 {
544     return 0;
545 }
546 
547 static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
548                             BlockCompletionFunc *cb)
549 {
550     MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
551 
552     s->io_buffer_index = 0;
553     if (s->drive_kind == IDE_CD) {
554         s->io_buffer_size = s->packet_transfer_size;
555     } else {
556         s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
557     }
558 
559     MACIO_DPRINTF("\n\n------------ IDE transfer\n");
560     MACIO_DPRINTF("buffer_size: %x   buffer_index: %x\n",
561                   s->io_buffer_size, s->io_buffer_index);
562     MACIO_DPRINTF("lba: %x    size: %x\n", s->lba, s->io_buffer_size);
563     MACIO_DPRINTF("-------------------------\n");
564 
565     m->dma_active = true;
566     DBDMA_kick(m->dbdma);
567 }
568 
569 static const IDEDMAOps dbdma_ops = {
570     .start_dma      = ide_dbdma_start,
571     .prepare_buf    = ide_nop_int32,
572     .rw_buf         = ide_nop_int,
573 };
574 
575 static void macio_ide_realizefn(DeviceState *dev, Error **errp)
576 {
577     MACIOIDEState *s = MACIO_IDE(dev);
578 
579     ide_init2(&s->bus, s->irq);
580 
581     /* Register DMA callbacks */
582     s->dma.ops = &dbdma_ops;
583     s->bus.dma = &s->dma;
584 }
585 
586 static void macio_ide_initfn(Object *obj)
587 {
588     SysBusDevice *d = SYS_BUS_DEVICE(obj);
589     MACIOIDEState *s = MACIO_IDE(obj);
590 
591     ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
592     memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
593     sysbus_init_mmio(d, &s->mem);
594     sysbus_init_irq(d, &s->irq);
595     sysbus_init_irq(d, &s->dma_irq);
596 }
597 
598 static void macio_ide_class_init(ObjectClass *oc, void *data)
599 {
600     DeviceClass *dc = DEVICE_CLASS(oc);
601 
602     dc->realize = macio_ide_realizefn;
603     dc->reset = macio_ide_reset;
604     dc->vmsd = &vmstate_pmac;
605     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
606 }
607 
608 static const TypeInfo macio_ide_type_info = {
609     .name = TYPE_MACIO_IDE,
610     .parent = TYPE_SYS_BUS_DEVICE,
611     .instance_size = sizeof(MACIOIDEState),
612     .instance_init = macio_ide_initfn,
613     .class_init = macio_ide_class_init,
614 };
615 
616 static void macio_ide_register_types(void)
617 {
618     type_register_static(&macio_ide_type_info);
619 }
620 
621 /* hd_table must contain 2 block drivers */
622 void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
623 {
624     int i;
625 
626     for (i = 0; i < 2; i++) {
627         if (hd_table[i]) {
628             ide_create_drive(&s->bus, i, hd_table[i]);
629         }
630     }
631 }
632 
633 void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
634 {
635     s->dbdma = dbdma;
636     DBDMA_register_channel(dbdma, channel, s->dma_irq,
637                            pmac_ide_transfer, pmac_ide_flush, s);
638 }
639 
640 type_init(macio_ide_register_types)
641