1 /* 2 * QEMU IDE disk and CD/DVD-ROM Emulator 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include <hw/hw.h> 26 #include <hw/i386/pc.h> 27 #include <hw/pci/pci.h> 28 #include <hw/isa/isa.h> 29 #include "qemu/error-report.h" 30 #include "qemu/timer.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/dma.h" 33 #include "hw/block/block.h" 34 #include "sysemu/block-backend.h" 35 36 #include <hw/ide/internal.h> 37 38 /* These values were based on a Seagate ST3500418AS but have been modified 39 to make more sense in QEMU */ 40 static const int smart_attributes[][12] = { 41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */ 42 /* raw read error rate*/ 43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06}, 44 /* spin up */ 45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 46 /* start stop count */ 47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14}, 48 /* remapped sectors */ 49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24}, 50 /* power on hours */ 51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 52 /* power cycle count */ 53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 54 /* airflow-temperature-celsius */ 55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32}, 56 }; 57 58 static int ide_handle_rw_error(IDEState *s, int error, int op); 59 static void ide_dummy_transfer_stop(IDEState *s); 60 61 static void padstr(char *str, const char *src, int len) 62 { 63 int i, v; 64 for(i = 0; i < len; i++) { 65 if (*src) 66 v = *src++; 67 else 68 v = ' '; 69 str[i^1] = v; 70 } 71 } 72 73 static void put_le16(uint16_t *p, unsigned int v) 74 { 75 *p = cpu_to_le16(v); 76 } 77 78 static void ide_identify_size(IDEState *s) 79 { 80 uint16_t *p = (uint16_t *)s->identify_data; 81 put_le16(p + 60, s->nb_sectors); 82 put_le16(p + 61, s->nb_sectors >> 16); 83 put_le16(p + 100, s->nb_sectors); 84 put_le16(p + 101, s->nb_sectors >> 16); 85 put_le16(p + 102, s->nb_sectors >> 32); 86 put_le16(p + 103, s->nb_sectors >> 48); 87 } 88 89 static void ide_identify(IDEState *s) 90 { 91 uint16_t *p; 92 unsigned int oldsize; 93 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master; 94 95 p = (uint16_t *)s->identify_data; 96 if (s->identify_set) { 97 goto fill_buffer; 98 } 99 memset(p, 0, sizeof(s->identify_data)); 100 101 put_le16(p + 0, 0x0040); 102 put_le16(p + 1, s->cylinders); 103 put_le16(p + 3, s->heads); 104 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */ 105 put_le16(p + 5, 512); /* XXX: retired, remove ? */ 106 put_le16(p + 6, s->sectors); 107 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 108 put_le16(p + 20, 3); /* XXX: retired, remove ? */ 109 put_le16(p + 21, 512); /* cache size in sectors */ 110 put_le16(p + 22, 4); /* ecc bytes */ 111 padstr((char *)(p + 23), s->version, 8); /* firmware version */ 112 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */ 113 #if MAX_MULT_SECTORS > 1 114 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); 115 #endif 116 put_le16(p + 48, 1); /* dword I/O */ 117 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */ 118 put_le16(p + 51, 0x200); /* PIO transfer cycle */ 119 put_le16(p + 52, 0x200); /* DMA transfer cycle */ 120 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */ 121 put_le16(p + 54, s->cylinders); 122 put_le16(p + 55, s->heads); 123 put_le16(p + 56, s->sectors); 124 oldsize = s->cylinders * s->heads * s->sectors; 125 put_le16(p + 57, oldsize); 126 put_le16(p + 58, oldsize >> 16); 127 if (s->mult_sectors) 128 put_le16(p + 59, 0x100 | s->mult_sectors); 129 /* *(p + 60) := nb_sectors -- see ide_identify_size */ 130 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */ 131 put_le16(p + 62, 0x07); /* single word dma0-2 supported */ 132 put_le16(p + 63, 0x07); /* mdma0-2 supported */ 133 put_le16(p + 64, 0x03); /* pio3-4 supported */ 134 put_le16(p + 65, 120); 135 put_le16(p + 66, 120); 136 put_le16(p + 67, 120); 137 put_le16(p + 68, 120); 138 if (dev && dev->conf.discard_granularity) { 139 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */ 140 } 141 142 if (s->ncq_queues) { 143 put_le16(p + 75, s->ncq_queues - 1); 144 /* NCQ supported */ 145 put_le16(p + 76, (1 << 8)); 146 } 147 148 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */ 149 put_le16(p + 81, 0x16); /* conforms to ata5 */ 150 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */ 151 put_le16(p + 82, (1 << 14) | (1 << 5) | 1); 152 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ 153 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); 154 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */ 155 if (s->wwn) { 156 put_le16(p + 84, (1 << 14) | (1 << 8) | 0); 157 } else { 158 put_le16(p + 84, (1 << 14) | 0); 159 } 160 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */ 161 if (blk_enable_write_cache(s->blk)) { 162 put_le16(p + 85, (1 << 14) | (1 << 5) | 1); 163 } else { 164 put_le16(p + 85, (1 << 14) | 1); 165 } 166 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ 167 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10)); 168 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */ 169 if (s->wwn) { 170 put_le16(p + 87, (1 << 14) | (1 << 8) | 0); 171 } else { 172 put_le16(p + 87, (1 << 14) | 0); 173 } 174 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ 175 put_le16(p + 93, 1 | (1 << 14) | 0x2000); 176 /* *(p + 100) := nb_sectors -- see ide_identify_size */ 177 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */ 178 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */ 179 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */ 180 181 if (dev && dev->conf.physical_block_size) 182 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf)); 183 if (s->wwn) { 184 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */ 185 put_le16(p + 108, s->wwn >> 48); 186 put_le16(p + 109, s->wwn >> 32); 187 put_le16(p + 110, s->wwn >> 16); 188 put_le16(p + 111, s->wwn); 189 } 190 if (dev && dev->conf.discard_granularity) { 191 put_le16(p + 169, 1); /* TRIM support */ 192 } 193 194 ide_identify_size(s); 195 s->identify_set = 1; 196 197 fill_buffer: 198 memcpy(s->io_buffer, p, sizeof(s->identify_data)); 199 } 200 201 static void ide_atapi_identify(IDEState *s) 202 { 203 uint16_t *p; 204 205 p = (uint16_t *)s->identify_data; 206 if (s->identify_set) { 207 goto fill_buffer; 208 } 209 memset(p, 0, sizeof(s->identify_data)); 210 211 /* Removable CDROM, 50us response, 12 byte packets */ 212 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0)); 213 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 214 put_le16(p + 20, 3); /* buffer type */ 215 put_le16(p + 21, 512); /* cache size in sectors */ 216 put_le16(p + 22, 4); /* ecc bytes */ 217 padstr((char *)(p + 23), s->version, 8); /* firmware version */ 218 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */ 219 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */ 220 #ifdef USE_DMA_CDROM 221 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */ 222 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */ 223 put_le16(p + 62, 7); /* single word dma0-2 supported */ 224 put_le16(p + 63, 7); /* mdma0-2 supported */ 225 #else 226 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */ 227 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */ 228 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */ 229 #endif 230 put_le16(p + 64, 3); /* pio3-4 supported */ 231 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */ 232 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */ 233 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */ 234 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */ 235 236 put_le16(p + 71, 30); /* in ns */ 237 put_le16(p + 72, 30); /* in ns */ 238 239 if (s->ncq_queues) { 240 put_le16(p + 75, s->ncq_queues - 1); 241 /* NCQ supported */ 242 put_le16(p + 76, (1 << 8)); 243 } 244 245 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */ 246 if (s->wwn) { 247 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */ 248 put_le16(p + 87, (1 << 8)); /* WWN enabled */ 249 } 250 251 #ifdef USE_DMA_CDROM 252 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ 253 #endif 254 255 if (s->wwn) { 256 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */ 257 put_le16(p + 108, s->wwn >> 48); 258 put_le16(p + 109, s->wwn >> 32); 259 put_le16(p + 110, s->wwn >> 16); 260 put_le16(p + 111, s->wwn); 261 } 262 263 s->identify_set = 1; 264 265 fill_buffer: 266 memcpy(s->io_buffer, p, sizeof(s->identify_data)); 267 } 268 269 static void ide_cfata_identify_size(IDEState *s) 270 { 271 uint16_t *p = (uint16_t *)s->identify_data; 272 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */ 273 put_le16(p + 8, s->nb_sectors); /* Sectors per card */ 274 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */ 275 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */ 276 } 277 278 static void ide_cfata_identify(IDEState *s) 279 { 280 uint16_t *p; 281 uint32_t cur_sec; 282 283 p = (uint16_t *)s->identify_data; 284 if (s->identify_set) { 285 goto fill_buffer; 286 } 287 memset(p, 0, sizeof(s->identify_data)); 288 289 cur_sec = s->cylinders * s->heads * s->sectors; 290 291 put_le16(p + 0, 0x848a); /* CF Storage Card signature */ 292 put_le16(p + 1, s->cylinders); /* Default cylinders */ 293 put_le16(p + 3, s->heads); /* Default heads */ 294 put_le16(p + 6, s->sectors); /* Default sectors per track */ 295 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */ 296 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */ 297 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 298 put_le16(p + 22, 0x0004); /* ECC bytes */ 299 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */ 300 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */ 301 #if MAX_MULT_SECTORS > 1 302 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); 303 #else 304 put_le16(p + 47, 0x0000); 305 #endif 306 put_le16(p + 49, 0x0f00); /* Capabilities */ 307 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */ 308 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */ 309 put_le16(p + 53, 0x0003); /* Translation params valid */ 310 put_le16(p + 54, s->cylinders); /* Current cylinders */ 311 put_le16(p + 55, s->heads); /* Current heads */ 312 put_le16(p + 56, s->sectors); /* Current sectors */ 313 put_le16(p + 57, cur_sec); /* Current capacity */ 314 put_le16(p + 58, cur_sec >> 16); /* Current capacity */ 315 if (s->mult_sectors) /* Multiple sector setting */ 316 put_le16(p + 59, 0x100 | s->mult_sectors); 317 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */ 318 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */ 319 put_le16(p + 63, 0x0203); /* Multiword DMA capability */ 320 put_le16(p + 64, 0x0001); /* Flow Control PIO support */ 321 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */ 322 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */ 323 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */ 324 put_le16(p + 82, 0x400c); /* Command Set supported */ 325 put_le16(p + 83, 0x7068); /* Command Set supported */ 326 put_le16(p + 84, 0x4000); /* Features supported */ 327 put_le16(p + 85, 0x000c); /* Command Set enabled */ 328 put_le16(p + 86, 0x7044); /* Command Set enabled */ 329 put_le16(p + 87, 0x4000); /* Features enabled */ 330 put_le16(p + 91, 0x4060); /* Current APM level */ 331 put_le16(p + 129, 0x0002); /* Current features option */ 332 put_le16(p + 130, 0x0005); /* Reassigned sectors */ 333 put_le16(p + 131, 0x0001); /* Initial power mode */ 334 put_le16(p + 132, 0x0000); /* User signature */ 335 put_le16(p + 160, 0x8100); /* Power requirement */ 336 put_le16(p + 161, 0x8001); /* CF command set */ 337 338 ide_cfata_identify_size(s); 339 s->identify_set = 1; 340 341 fill_buffer: 342 memcpy(s->io_buffer, p, sizeof(s->identify_data)); 343 } 344 345 static void ide_set_signature(IDEState *s) 346 { 347 s->select &= 0xf0; /* clear head */ 348 /* put signature */ 349 s->nsector = 1; 350 s->sector = 1; 351 if (s->drive_kind == IDE_CD) { 352 s->lcyl = 0x14; 353 s->hcyl = 0xeb; 354 } else if (s->blk) { 355 s->lcyl = 0; 356 s->hcyl = 0; 357 } else { 358 s->lcyl = 0xff; 359 s->hcyl = 0xff; 360 } 361 } 362 363 typedef struct TrimAIOCB { 364 BlockAIOCB common; 365 BlockBackend *blk; 366 QEMUBH *bh; 367 int ret; 368 QEMUIOVector *qiov; 369 BlockAIOCB *aiocb; 370 int i, j; 371 } TrimAIOCB; 372 373 static void trim_aio_cancel(BlockAIOCB *acb) 374 { 375 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common); 376 377 /* Exit the loop so ide_issue_trim_cb will not continue */ 378 iocb->j = iocb->qiov->niov - 1; 379 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1; 380 381 iocb->ret = -ECANCELED; 382 383 if (iocb->aiocb) { 384 blk_aio_cancel_async(iocb->aiocb); 385 iocb->aiocb = NULL; 386 } 387 } 388 389 static const AIOCBInfo trim_aiocb_info = { 390 .aiocb_size = sizeof(TrimAIOCB), 391 .cancel_async = trim_aio_cancel, 392 }; 393 394 static void ide_trim_bh_cb(void *opaque) 395 { 396 TrimAIOCB *iocb = opaque; 397 398 iocb->common.cb(iocb->common.opaque, iocb->ret); 399 400 qemu_bh_delete(iocb->bh); 401 iocb->bh = NULL; 402 qemu_aio_unref(iocb); 403 } 404 405 static void ide_issue_trim_cb(void *opaque, int ret) 406 { 407 TrimAIOCB *iocb = opaque; 408 if (ret >= 0) { 409 while (iocb->j < iocb->qiov->niov) { 410 int j = iocb->j; 411 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) { 412 int i = iocb->i; 413 uint64_t *buffer = iocb->qiov->iov[j].iov_base; 414 415 /* 6-byte LBA + 2-byte range per entry */ 416 uint64_t entry = le64_to_cpu(buffer[i]); 417 uint64_t sector = entry & 0x0000ffffffffffffULL; 418 uint16_t count = entry >> 48; 419 420 if (count == 0) { 421 continue; 422 } 423 424 /* Got an entry! Submit and exit. */ 425 iocb->aiocb = blk_aio_discard(iocb->blk, sector, count, 426 ide_issue_trim_cb, opaque); 427 return; 428 } 429 430 iocb->j++; 431 iocb->i = -1; 432 } 433 } else { 434 iocb->ret = ret; 435 } 436 437 iocb->aiocb = NULL; 438 if (iocb->bh) { 439 qemu_bh_schedule(iocb->bh); 440 } 441 } 442 443 BlockAIOCB *ide_issue_trim(BlockBackend *blk, 444 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, 445 BlockCompletionFunc *cb, void *opaque) 446 { 447 TrimAIOCB *iocb; 448 449 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque); 450 iocb->blk = blk; 451 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb); 452 iocb->ret = 0; 453 iocb->qiov = qiov; 454 iocb->i = -1; 455 iocb->j = 0; 456 ide_issue_trim_cb(iocb, 0); 457 return &iocb->common; 458 } 459 460 static inline void ide_abort_command(IDEState *s) 461 { 462 ide_transfer_stop(s); 463 s->status = READY_STAT | ERR_STAT; 464 s->error = ABRT_ERR; 465 } 466 467 /* prepare data transfer and tell what to do after */ 468 void ide_transfer_start(IDEState *s, uint8_t *buf, int size, 469 EndTransferFunc *end_transfer_func) 470 { 471 s->end_transfer_func = end_transfer_func; 472 s->data_ptr = buf; 473 s->data_end = buf + size; 474 if (!(s->status & ERR_STAT)) { 475 s->status |= DRQ_STAT; 476 } 477 if (s->bus->dma->ops->start_transfer) { 478 s->bus->dma->ops->start_transfer(s->bus->dma); 479 } 480 } 481 482 static void ide_cmd_done(IDEState *s) 483 { 484 if (s->bus->dma->ops->cmd_done) { 485 s->bus->dma->ops->cmd_done(s->bus->dma); 486 } 487 } 488 489 void ide_transfer_stop(IDEState *s) 490 { 491 s->end_transfer_func = ide_transfer_stop; 492 s->data_ptr = s->io_buffer; 493 s->data_end = s->io_buffer; 494 s->status &= ~DRQ_STAT; 495 ide_cmd_done(s); 496 } 497 498 int64_t ide_get_sector(IDEState *s) 499 { 500 int64_t sector_num; 501 if (s->select & 0x40) { 502 /* lba */ 503 if (!s->lba48) { 504 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | 505 (s->lcyl << 8) | s->sector; 506 } else { 507 sector_num = ((int64_t)s->hob_hcyl << 40) | 508 ((int64_t) s->hob_lcyl << 32) | 509 ((int64_t) s->hob_sector << 24) | 510 ((int64_t) s->hcyl << 16) | 511 ((int64_t) s->lcyl << 8) | s->sector; 512 } 513 } else { 514 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors + 515 (s->select & 0x0f) * s->sectors + (s->sector - 1); 516 } 517 return sector_num; 518 } 519 520 void ide_set_sector(IDEState *s, int64_t sector_num) 521 { 522 unsigned int cyl, r; 523 if (s->select & 0x40) { 524 if (!s->lba48) { 525 s->select = (s->select & 0xf0) | (sector_num >> 24); 526 s->hcyl = (sector_num >> 16); 527 s->lcyl = (sector_num >> 8); 528 s->sector = (sector_num); 529 } else { 530 s->sector = sector_num; 531 s->lcyl = sector_num >> 8; 532 s->hcyl = sector_num >> 16; 533 s->hob_sector = sector_num >> 24; 534 s->hob_lcyl = sector_num >> 32; 535 s->hob_hcyl = sector_num >> 40; 536 } 537 } else { 538 cyl = sector_num / (s->heads * s->sectors); 539 r = sector_num % (s->heads * s->sectors); 540 s->hcyl = cyl >> 8; 541 s->lcyl = cyl; 542 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f); 543 s->sector = (r % s->sectors) + 1; 544 } 545 } 546 547 static void ide_rw_error(IDEState *s) { 548 ide_abort_command(s); 549 ide_set_irq(s->bus); 550 } 551 552 static bool ide_sect_range_ok(IDEState *s, 553 uint64_t sector, uint64_t nb_sectors) 554 { 555 uint64_t total_sectors; 556 557 blk_get_geometry(s->blk, &total_sectors); 558 if (sector > total_sectors || nb_sectors > total_sectors - sector) { 559 return false; 560 } 561 return true; 562 } 563 564 static void ide_sector_read_cb(void *opaque, int ret) 565 { 566 IDEState *s = opaque; 567 int n; 568 569 s->pio_aiocb = NULL; 570 s->status &= ~BUSY_STAT; 571 572 if (ret == -ECANCELED) { 573 return; 574 } 575 block_acct_done(blk_get_stats(s->blk), &s->acct); 576 if (ret != 0) { 577 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO | 578 IDE_RETRY_READ)) { 579 return; 580 } 581 } 582 583 n = s->nsector; 584 if (n > s->req_nb_sectors) { 585 n = s->req_nb_sectors; 586 } 587 588 /* Allow the guest to read the io_buffer */ 589 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read); 590 591 ide_set_irq(s->bus); 592 593 ide_set_sector(s, ide_get_sector(s) + n); 594 s->nsector -= n; 595 } 596 597 void ide_sector_read(IDEState *s) 598 { 599 int64_t sector_num; 600 int n; 601 602 s->status = READY_STAT | SEEK_STAT; 603 s->error = 0; /* not needed by IDE spec, but needed by Windows */ 604 sector_num = ide_get_sector(s); 605 n = s->nsector; 606 607 if (n == 0) { 608 ide_transfer_stop(s); 609 return; 610 } 611 612 s->status |= BUSY_STAT; 613 614 if (n > s->req_nb_sectors) { 615 n = s->req_nb_sectors; 616 } 617 618 #if defined(DEBUG_IDE) 619 printf("sector=%" PRId64 "\n", sector_num); 620 #endif 621 622 if (!ide_sect_range_ok(s, sector_num, n)) { 623 ide_rw_error(s); 624 return; 625 } 626 627 s->iov.iov_base = s->io_buffer; 628 s->iov.iov_len = n * BDRV_SECTOR_SIZE; 629 qemu_iovec_init_external(&s->qiov, &s->iov, 1); 630 631 block_acct_start(blk_get_stats(s->blk), &s->acct, 632 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ); 633 s->pio_aiocb = blk_aio_readv(s->blk, sector_num, &s->qiov, n, 634 ide_sector_read_cb, s); 635 } 636 637 static void dma_buf_commit(IDEState *s, uint32_t tx_bytes) 638 { 639 if (s->bus->dma->ops->commit_buf) { 640 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes); 641 } 642 qemu_sglist_destroy(&s->sg); 643 } 644 645 void ide_set_inactive(IDEState *s, bool more) 646 { 647 s->bus->dma->aiocb = NULL; 648 if (s->bus->dma->ops->set_inactive) { 649 s->bus->dma->ops->set_inactive(s->bus->dma, more); 650 } 651 ide_cmd_done(s); 652 } 653 654 void ide_dma_error(IDEState *s) 655 { 656 dma_buf_commit(s, 0); 657 ide_abort_command(s); 658 ide_set_inactive(s, false); 659 ide_set_irq(s->bus); 660 } 661 662 static int ide_handle_rw_error(IDEState *s, int error, int op) 663 { 664 bool is_read = (op & IDE_RETRY_READ) != 0; 665 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error); 666 667 if (action == BLOCK_ERROR_ACTION_STOP) { 668 s->bus->dma->ops->set_unit(s->bus->dma, s->unit); 669 s->bus->error_status = op; 670 } else if (action == BLOCK_ERROR_ACTION_REPORT) { 671 if (op & IDE_RETRY_DMA) { 672 ide_dma_error(s); 673 } else { 674 ide_rw_error(s); 675 } 676 } 677 blk_error_action(s->blk, action, is_read, error); 678 return action != BLOCK_ERROR_ACTION_IGNORE; 679 } 680 681 void ide_dma_cb(void *opaque, int ret) 682 { 683 IDEState *s = opaque; 684 int n; 685 int64_t sector_num; 686 bool stay_active = false; 687 688 if (ret == -ECANCELED) { 689 return; 690 } 691 if (ret < 0) { 692 int op = IDE_RETRY_DMA; 693 694 if (s->dma_cmd == IDE_DMA_READ) 695 op |= IDE_RETRY_READ; 696 else if (s->dma_cmd == IDE_DMA_TRIM) 697 op |= IDE_RETRY_TRIM; 698 699 if (ide_handle_rw_error(s, -ret, op)) { 700 return; 701 } 702 } 703 704 n = s->io_buffer_size >> 9; 705 if (n > s->nsector) { 706 /* The PRDs were longer than needed for this request. Shorten them so 707 * we don't get a negative remainder. The Active bit must remain set 708 * after the request completes. */ 709 n = s->nsector; 710 stay_active = true; 711 } 712 713 sector_num = ide_get_sector(s); 714 if (n > 0) { 715 assert(s->io_buffer_size == s->sg.size); 716 dma_buf_commit(s, s->io_buffer_size); 717 sector_num += n; 718 ide_set_sector(s, sector_num); 719 s->nsector -= n; 720 } 721 722 /* end of transfer ? */ 723 if (s->nsector == 0) { 724 s->status = READY_STAT | SEEK_STAT; 725 ide_set_irq(s->bus); 726 goto eot; 727 } 728 729 /* launch next transfer */ 730 n = s->nsector; 731 s->io_buffer_index = 0; 732 s->io_buffer_size = n * 512; 733 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) { 734 /* The PRDs were too short. Reset the Active bit, but don't raise an 735 * interrupt. */ 736 s->status = READY_STAT | SEEK_STAT; 737 goto eot; 738 } 739 740 #ifdef DEBUG_AIO 741 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n", 742 sector_num, n, s->dma_cmd); 743 #endif 744 745 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) && 746 !ide_sect_range_ok(s, sector_num, n)) { 747 ide_dma_error(s); 748 return; 749 } 750 751 switch (s->dma_cmd) { 752 case IDE_DMA_READ: 753 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, sector_num, 754 ide_dma_cb, s); 755 break; 756 case IDE_DMA_WRITE: 757 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, sector_num, 758 ide_dma_cb, s); 759 break; 760 case IDE_DMA_TRIM: 761 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, sector_num, 762 ide_issue_trim, ide_dma_cb, s, 763 DMA_DIRECTION_TO_DEVICE); 764 break; 765 } 766 return; 767 768 eot: 769 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { 770 block_acct_done(blk_get_stats(s->blk), &s->acct); 771 } 772 ide_set_inactive(s, stay_active); 773 } 774 775 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd) 776 { 777 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; 778 s->io_buffer_index = 0; 779 s->io_buffer_size = 0; 780 s->dma_cmd = dma_cmd; 781 782 switch (dma_cmd) { 783 case IDE_DMA_READ: 784 block_acct_start(blk_get_stats(s->blk), &s->acct, 785 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ); 786 break; 787 case IDE_DMA_WRITE: 788 block_acct_start(blk_get_stats(s->blk), &s->acct, 789 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE); 790 break; 791 default: 792 break; 793 } 794 795 ide_start_dma(s, ide_dma_cb); 796 } 797 798 void ide_start_dma(IDEState *s, BlockCompletionFunc *cb) 799 { 800 if (s->bus->dma->ops->start_dma) { 801 s->bus->dma->ops->start_dma(s->bus->dma, s, cb); 802 } 803 } 804 805 static void ide_sector_write_timer_cb(void *opaque) 806 { 807 IDEState *s = opaque; 808 ide_set_irq(s->bus); 809 } 810 811 static void ide_sector_write_cb(void *opaque, int ret) 812 { 813 IDEState *s = opaque; 814 int n; 815 816 if (ret == -ECANCELED) { 817 return; 818 } 819 block_acct_done(blk_get_stats(s->blk), &s->acct); 820 821 s->pio_aiocb = NULL; 822 s->status &= ~BUSY_STAT; 823 824 if (ret != 0) { 825 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) { 826 return; 827 } 828 } 829 830 n = s->nsector; 831 if (n > s->req_nb_sectors) { 832 n = s->req_nb_sectors; 833 } 834 s->nsector -= n; 835 if (s->nsector == 0) { 836 /* no more sectors to write */ 837 ide_transfer_stop(s); 838 } else { 839 int n1 = s->nsector; 840 if (n1 > s->req_nb_sectors) { 841 n1 = s->req_nb_sectors; 842 } 843 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE, 844 ide_sector_write); 845 } 846 ide_set_sector(s, ide_get_sector(s) + n); 847 848 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) { 849 /* It seems there is a bug in the Windows 2000 installer HDD 850 IDE driver which fills the disk with empty logs when the 851 IDE write IRQ comes too early. This hack tries to correct 852 that at the expense of slower write performances. Use this 853 option _only_ to install Windows 2000. You must disable it 854 for normal use. */ 855 timer_mod(s->sector_write_timer, 856 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000)); 857 } else { 858 ide_set_irq(s->bus); 859 } 860 } 861 862 void ide_sector_write(IDEState *s) 863 { 864 int64_t sector_num; 865 int n; 866 867 s->status = READY_STAT | SEEK_STAT | BUSY_STAT; 868 sector_num = ide_get_sector(s); 869 #if defined(DEBUG_IDE) 870 printf("sector=%" PRId64 "\n", sector_num); 871 #endif 872 n = s->nsector; 873 if (n > s->req_nb_sectors) { 874 n = s->req_nb_sectors; 875 } 876 877 if (!ide_sect_range_ok(s, sector_num, n)) { 878 ide_rw_error(s); 879 return; 880 } 881 882 s->iov.iov_base = s->io_buffer; 883 s->iov.iov_len = n * BDRV_SECTOR_SIZE; 884 qemu_iovec_init_external(&s->qiov, &s->iov, 1); 885 886 block_acct_start(blk_get_stats(s->blk), &s->acct, 887 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ); 888 s->pio_aiocb = blk_aio_writev(s->blk, sector_num, &s->qiov, n, 889 ide_sector_write_cb, s); 890 } 891 892 static void ide_flush_cb(void *opaque, int ret) 893 { 894 IDEState *s = opaque; 895 896 s->pio_aiocb = NULL; 897 898 if (ret == -ECANCELED) { 899 return; 900 } 901 if (ret < 0) { 902 /* XXX: What sector number to set here? */ 903 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) { 904 return; 905 } 906 } 907 908 if (s->blk) { 909 block_acct_done(blk_get_stats(s->blk), &s->acct); 910 } 911 s->status = READY_STAT | SEEK_STAT; 912 ide_cmd_done(s); 913 ide_set_irq(s->bus); 914 } 915 916 void ide_flush_cache(IDEState *s) 917 { 918 if (s->blk == NULL) { 919 ide_flush_cb(s, 0); 920 return; 921 } 922 923 s->status |= BUSY_STAT; 924 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH); 925 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s); 926 } 927 928 static void ide_cfata_metadata_inquiry(IDEState *s) 929 { 930 uint16_t *p; 931 uint32_t spd; 932 933 p = (uint16_t *) s->io_buffer; 934 memset(p, 0, 0x200); 935 spd = ((s->mdata_size - 1) >> 9) + 1; 936 937 put_le16(p + 0, 0x0001); /* Data format revision */ 938 put_le16(p + 1, 0x0000); /* Media property: silicon */ 939 put_le16(p + 2, s->media_changed); /* Media status */ 940 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */ 941 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */ 942 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */ 943 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */ 944 } 945 946 static void ide_cfata_metadata_read(IDEState *s) 947 { 948 uint16_t *p; 949 950 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { 951 s->status = ERR_STAT; 952 s->error = ABRT_ERR; 953 return; 954 } 955 956 p = (uint16_t *) s->io_buffer; 957 memset(p, 0, 0x200); 958 959 put_le16(p + 0, s->media_changed); /* Media status */ 960 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), 961 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), 962 s->nsector << 9), 0x200 - 2)); 963 } 964 965 static void ide_cfata_metadata_write(IDEState *s) 966 { 967 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { 968 s->status = ERR_STAT; 969 s->error = ABRT_ERR; 970 return; 971 } 972 973 s->media_changed = 0; 974 975 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), 976 s->io_buffer + 2, 977 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), 978 s->nsector << 9), 0x200 - 2)); 979 } 980 981 /* called when the inserted state of the media has changed */ 982 static void ide_cd_change_cb(void *opaque, bool load) 983 { 984 IDEState *s = opaque; 985 uint64_t nb_sectors; 986 987 s->tray_open = !load; 988 blk_get_geometry(s->blk, &nb_sectors); 989 s->nb_sectors = nb_sectors; 990 991 /* 992 * First indicate to the guest that a CD has been removed. That's 993 * done on the next command the guest sends us. 994 * 995 * Then we set UNIT_ATTENTION, by which the guest will 996 * detect a new CD in the drive. See ide_atapi_cmd() for details. 997 */ 998 s->cdrom_changed = 1; 999 s->events.new_media = true; 1000 s->events.eject_request = false; 1001 ide_set_irq(s->bus); 1002 } 1003 1004 static void ide_cd_eject_request_cb(void *opaque, bool force) 1005 { 1006 IDEState *s = opaque; 1007 1008 s->events.eject_request = true; 1009 if (force) { 1010 s->tray_locked = false; 1011 } 1012 ide_set_irq(s->bus); 1013 } 1014 1015 static void ide_cmd_lba48_transform(IDEState *s, int lba48) 1016 { 1017 s->lba48 = lba48; 1018 1019 /* handle the 'magic' 0 nsector count conversion here. to avoid 1020 * fiddling with the rest of the read logic, we just store the 1021 * full sector count in ->nsector and ignore ->hob_nsector from now 1022 */ 1023 if (!s->lba48) { 1024 if (!s->nsector) 1025 s->nsector = 256; 1026 } else { 1027 if (!s->nsector && !s->hob_nsector) 1028 s->nsector = 65536; 1029 else { 1030 int lo = s->nsector; 1031 int hi = s->hob_nsector; 1032 1033 s->nsector = (hi << 8) | lo; 1034 } 1035 } 1036 } 1037 1038 static void ide_clear_hob(IDEBus *bus) 1039 { 1040 /* any write clears HOB high bit of device control register */ 1041 bus->ifs[0].select &= ~(1 << 7); 1042 bus->ifs[1].select &= ~(1 << 7); 1043 } 1044 1045 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1046 { 1047 IDEBus *bus = opaque; 1048 1049 #ifdef DEBUG_IDE 1050 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val); 1051 #endif 1052 1053 addr &= 7; 1054 1055 /* ignore writes to command block while busy with previous command */ 1056 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT))) 1057 return; 1058 1059 switch(addr) { 1060 case 0: 1061 break; 1062 case 1: 1063 ide_clear_hob(bus); 1064 /* NOTE: data is written to the two drives */ 1065 bus->ifs[0].hob_feature = bus->ifs[0].feature; 1066 bus->ifs[1].hob_feature = bus->ifs[1].feature; 1067 bus->ifs[0].feature = val; 1068 bus->ifs[1].feature = val; 1069 break; 1070 case 2: 1071 ide_clear_hob(bus); 1072 bus->ifs[0].hob_nsector = bus->ifs[0].nsector; 1073 bus->ifs[1].hob_nsector = bus->ifs[1].nsector; 1074 bus->ifs[0].nsector = val; 1075 bus->ifs[1].nsector = val; 1076 break; 1077 case 3: 1078 ide_clear_hob(bus); 1079 bus->ifs[0].hob_sector = bus->ifs[0].sector; 1080 bus->ifs[1].hob_sector = bus->ifs[1].sector; 1081 bus->ifs[0].sector = val; 1082 bus->ifs[1].sector = val; 1083 break; 1084 case 4: 1085 ide_clear_hob(bus); 1086 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl; 1087 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl; 1088 bus->ifs[0].lcyl = val; 1089 bus->ifs[1].lcyl = val; 1090 break; 1091 case 5: 1092 ide_clear_hob(bus); 1093 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl; 1094 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl; 1095 bus->ifs[0].hcyl = val; 1096 bus->ifs[1].hcyl = val; 1097 break; 1098 case 6: 1099 /* FIXME: HOB readback uses bit 7 */ 1100 bus->ifs[0].select = (val & ~0x10) | 0xa0; 1101 bus->ifs[1].select = (val | 0x10) | 0xa0; 1102 /* select drive */ 1103 bus->unit = (val >> 4) & 1; 1104 break; 1105 default: 1106 case 7: 1107 /* command */ 1108 ide_exec_cmd(bus, val); 1109 break; 1110 } 1111 } 1112 1113 static bool cmd_nop(IDEState *s, uint8_t cmd) 1114 { 1115 return true; 1116 } 1117 1118 static bool cmd_data_set_management(IDEState *s, uint8_t cmd) 1119 { 1120 switch (s->feature) { 1121 case DSM_TRIM: 1122 if (s->blk) { 1123 ide_sector_start_dma(s, IDE_DMA_TRIM); 1124 return false; 1125 } 1126 break; 1127 } 1128 1129 ide_abort_command(s); 1130 return true; 1131 } 1132 1133 static bool cmd_identify(IDEState *s, uint8_t cmd) 1134 { 1135 if (s->blk && s->drive_kind != IDE_CD) { 1136 if (s->drive_kind != IDE_CFATA) { 1137 ide_identify(s); 1138 } else { 1139 ide_cfata_identify(s); 1140 } 1141 s->status = READY_STAT | SEEK_STAT; 1142 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); 1143 ide_set_irq(s->bus); 1144 return false; 1145 } else { 1146 if (s->drive_kind == IDE_CD) { 1147 ide_set_signature(s); 1148 } 1149 ide_abort_command(s); 1150 } 1151 1152 return true; 1153 } 1154 1155 static bool cmd_verify(IDEState *s, uint8_t cmd) 1156 { 1157 bool lba48 = (cmd == WIN_VERIFY_EXT); 1158 1159 /* do sector number check ? */ 1160 ide_cmd_lba48_transform(s, lba48); 1161 1162 return true; 1163 } 1164 1165 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd) 1166 { 1167 if (s->drive_kind == IDE_CFATA && s->nsector == 0) { 1168 /* Disable Read and Write Multiple */ 1169 s->mult_sectors = 0; 1170 } else if ((s->nsector & 0xff) != 0 && 1171 ((s->nsector & 0xff) > MAX_MULT_SECTORS || 1172 (s->nsector & (s->nsector - 1)) != 0)) { 1173 ide_abort_command(s); 1174 } else { 1175 s->mult_sectors = s->nsector & 0xff; 1176 } 1177 1178 return true; 1179 } 1180 1181 static bool cmd_read_multiple(IDEState *s, uint8_t cmd) 1182 { 1183 bool lba48 = (cmd == WIN_MULTREAD_EXT); 1184 1185 if (!s->blk || !s->mult_sectors) { 1186 ide_abort_command(s); 1187 return true; 1188 } 1189 1190 ide_cmd_lba48_transform(s, lba48); 1191 s->req_nb_sectors = s->mult_sectors; 1192 ide_sector_read(s); 1193 return false; 1194 } 1195 1196 static bool cmd_write_multiple(IDEState *s, uint8_t cmd) 1197 { 1198 bool lba48 = (cmd == WIN_MULTWRITE_EXT); 1199 int n; 1200 1201 if (!s->blk || !s->mult_sectors) { 1202 ide_abort_command(s); 1203 return true; 1204 } 1205 1206 ide_cmd_lba48_transform(s, lba48); 1207 1208 s->req_nb_sectors = s->mult_sectors; 1209 n = MIN(s->nsector, s->req_nb_sectors); 1210 1211 s->status = SEEK_STAT | READY_STAT; 1212 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write); 1213 1214 s->media_changed = 1; 1215 1216 return false; 1217 } 1218 1219 static bool cmd_read_pio(IDEState *s, uint8_t cmd) 1220 { 1221 bool lba48 = (cmd == WIN_READ_EXT); 1222 1223 if (s->drive_kind == IDE_CD) { 1224 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */ 1225 ide_abort_command(s); 1226 return true; 1227 } 1228 1229 if (!s->blk) { 1230 ide_abort_command(s); 1231 return true; 1232 } 1233 1234 ide_cmd_lba48_transform(s, lba48); 1235 s->req_nb_sectors = 1; 1236 ide_sector_read(s); 1237 1238 return false; 1239 } 1240 1241 static bool cmd_write_pio(IDEState *s, uint8_t cmd) 1242 { 1243 bool lba48 = (cmd == WIN_WRITE_EXT); 1244 1245 if (!s->blk) { 1246 ide_abort_command(s); 1247 return true; 1248 } 1249 1250 ide_cmd_lba48_transform(s, lba48); 1251 1252 s->req_nb_sectors = 1; 1253 s->status = SEEK_STAT | READY_STAT; 1254 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write); 1255 1256 s->media_changed = 1; 1257 1258 return false; 1259 } 1260 1261 static bool cmd_read_dma(IDEState *s, uint8_t cmd) 1262 { 1263 bool lba48 = (cmd == WIN_READDMA_EXT); 1264 1265 if (!s->blk) { 1266 ide_abort_command(s); 1267 return true; 1268 } 1269 1270 ide_cmd_lba48_transform(s, lba48); 1271 ide_sector_start_dma(s, IDE_DMA_READ); 1272 1273 return false; 1274 } 1275 1276 static bool cmd_write_dma(IDEState *s, uint8_t cmd) 1277 { 1278 bool lba48 = (cmd == WIN_WRITEDMA_EXT); 1279 1280 if (!s->blk) { 1281 ide_abort_command(s); 1282 return true; 1283 } 1284 1285 ide_cmd_lba48_transform(s, lba48); 1286 ide_sector_start_dma(s, IDE_DMA_WRITE); 1287 1288 s->media_changed = 1; 1289 1290 return false; 1291 } 1292 1293 static bool cmd_flush_cache(IDEState *s, uint8_t cmd) 1294 { 1295 ide_flush_cache(s); 1296 return false; 1297 } 1298 1299 static bool cmd_seek(IDEState *s, uint8_t cmd) 1300 { 1301 /* XXX: Check that seek is within bounds */ 1302 return true; 1303 } 1304 1305 static bool cmd_read_native_max(IDEState *s, uint8_t cmd) 1306 { 1307 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT); 1308 1309 /* Refuse if no sectors are addressable (e.g. medium not inserted) */ 1310 if (s->nb_sectors == 0) { 1311 ide_abort_command(s); 1312 return true; 1313 } 1314 1315 ide_cmd_lba48_transform(s, lba48); 1316 ide_set_sector(s, s->nb_sectors - 1); 1317 1318 return true; 1319 } 1320 1321 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd) 1322 { 1323 s->nsector = 0xff; /* device active or idle */ 1324 return true; 1325 } 1326 1327 static bool cmd_set_features(IDEState *s, uint8_t cmd) 1328 { 1329 uint16_t *identify_data; 1330 1331 if (!s->blk) { 1332 ide_abort_command(s); 1333 return true; 1334 } 1335 1336 /* XXX: valid for CDROM ? */ 1337 switch (s->feature) { 1338 case 0x02: /* write cache enable */ 1339 blk_set_enable_write_cache(s->blk, true); 1340 identify_data = (uint16_t *)s->identify_data; 1341 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1); 1342 return true; 1343 case 0x82: /* write cache disable */ 1344 blk_set_enable_write_cache(s->blk, false); 1345 identify_data = (uint16_t *)s->identify_data; 1346 put_le16(identify_data + 85, (1 << 14) | 1); 1347 ide_flush_cache(s); 1348 return false; 1349 case 0xcc: /* reverting to power-on defaults enable */ 1350 case 0x66: /* reverting to power-on defaults disable */ 1351 case 0xaa: /* read look-ahead enable */ 1352 case 0x55: /* read look-ahead disable */ 1353 case 0x05: /* set advanced power management mode */ 1354 case 0x85: /* disable advanced power management mode */ 1355 case 0x69: /* NOP */ 1356 case 0x67: /* NOP */ 1357 case 0x96: /* NOP */ 1358 case 0x9a: /* NOP */ 1359 case 0x42: /* enable Automatic Acoustic Mode */ 1360 case 0xc2: /* disable Automatic Acoustic Mode */ 1361 return true; 1362 case 0x03: /* set transfer mode */ 1363 { 1364 uint8_t val = s->nsector & 0x07; 1365 identify_data = (uint16_t *)s->identify_data; 1366 1367 switch (s->nsector >> 3) { 1368 case 0x00: /* pio default */ 1369 case 0x01: /* pio mode */ 1370 put_le16(identify_data + 62, 0x07); 1371 put_le16(identify_data + 63, 0x07); 1372 put_le16(identify_data + 88, 0x3f); 1373 break; 1374 case 0x02: /* sigle word dma mode*/ 1375 put_le16(identify_data + 62, 0x07 | (1 << (val + 8))); 1376 put_le16(identify_data + 63, 0x07); 1377 put_le16(identify_data + 88, 0x3f); 1378 break; 1379 case 0x04: /* mdma mode */ 1380 put_le16(identify_data + 62, 0x07); 1381 put_le16(identify_data + 63, 0x07 | (1 << (val + 8))); 1382 put_le16(identify_data + 88, 0x3f); 1383 break; 1384 case 0x08: /* udma mode */ 1385 put_le16(identify_data + 62, 0x07); 1386 put_le16(identify_data + 63, 0x07); 1387 put_le16(identify_data + 88, 0x3f | (1 << (val + 8))); 1388 break; 1389 default: 1390 goto abort_cmd; 1391 } 1392 return true; 1393 } 1394 } 1395 1396 abort_cmd: 1397 ide_abort_command(s); 1398 return true; 1399 } 1400 1401 1402 /*** ATAPI commands ***/ 1403 1404 static bool cmd_identify_packet(IDEState *s, uint8_t cmd) 1405 { 1406 ide_atapi_identify(s); 1407 s->status = READY_STAT | SEEK_STAT; 1408 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); 1409 ide_set_irq(s->bus); 1410 return false; 1411 } 1412 1413 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd) 1414 { 1415 ide_set_signature(s); 1416 1417 if (s->drive_kind == IDE_CD) { 1418 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet 1419 * devices to return a clear status register 1420 * with READY_STAT *not* set. */ 1421 s->error = 0x01; 1422 } else { 1423 s->status = READY_STAT | SEEK_STAT; 1424 /* The bits of the error register are not as usual for this command! 1425 * They are part of the regular output (this is why ERR_STAT isn't set) 1426 * Device 0 passed, Device 1 passed or not present. */ 1427 s->error = 0x01; 1428 ide_set_irq(s->bus); 1429 } 1430 1431 return false; 1432 } 1433 1434 static bool cmd_device_reset(IDEState *s, uint8_t cmd) 1435 { 1436 ide_set_signature(s); 1437 s->status = 0x00; /* NOTE: READY is _not_ set */ 1438 s->error = 0x01; 1439 1440 return false; 1441 } 1442 1443 static bool cmd_packet(IDEState *s, uint8_t cmd) 1444 { 1445 /* overlapping commands not supported */ 1446 if (s->feature & 0x02) { 1447 ide_abort_command(s); 1448 return true; 1449 } 1450 1451 s->status = READY_STAT | SEEK_STAT; 1452 s->atapi_dma = s->feature & 1; 1453 s->nsector = 1; 1454 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, 1455 ide_atapi_cmd); 1456 return false; 1457 } 1458 1459 1460 /*** CF-ATA commands ***/ 1461 1462 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd) 1463 { 1464 s->error = 0x09; /* miscellaneous error */ 1465 s->status = READY_STAT | SEEK_STAT; 1466 ide_set_irq(s->bus); 1467 1468 return false; 1469 } 1470 1471 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd) 1472 { 1473 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is 1474 * required for Windows 8 to work with AHCI */ 1475 1476 if (cmd == CFA_WEAR_LEVEL) { 1477 s->nsector = 0; 1478 } 1479 1480 if (cmd == CFA_ERASE_SECTORS) { 1481 s->media_changed = 1; 1482 } 1483 1484 return true; 1485 } 1486 1487 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd) 1488 { 1489 s->status = READY_STAT | SEEK_STAT; 1490 1491 memset(s->io_buffer, 0, 0x200); 1492 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */ 1493 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */ 1494 s->io_buffer[0x02] = s->select; /* Head */ 1495 s->io_buffer[0x03] = s->sector; /* Sector */ 1496 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */ 1497 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */ 1498 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */ 1499 s->io_buffer[0x13] = 0x00; /* Erase flag */ 1500 s->io_buffer[0x18] = 0x00; /* Hot count */ 1501 s->io_buffer[0x19] = 0x00; /* Hot count */ 1502 s->io_buffer[0x1a] = 0x01; /* Hot count */ 1503 1504 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1505 ide_set_irq(s->bus); 1506 1507 return false; 1508 } 1509 1510 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd) 1511 { 1512 switch (s->feature) { 1513 case 0x02: /* Inquiry Metadata Storage */ 1514 ide_cfata_metadata_inquiry(s); 1515 break; 1516 case 0x03: /* Read Metadata Storage */ 1517 ide_cfata_metadata_read(s); 1518 break; 1519 case 0x04: /* Write Metadata Storage */ 1520 ide_cfata_metadata_write(s); 1521 break; 1522 default: 1523 ide_abort_command(s); 1524 return true; 1525 } 1526 1527 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1528 s->status = 0x00; /* NOTE: READY is _not_ set */ 1529 ide_set_irq(s->bus); 1530 1531 return false; 1532 } 1533 1534 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd) 1535 { 1536 switch (s->feature) { 1537 case 0x01: /* sense temperature in device */ 1538 s->nsector = 0x50; /* +20 C */ 1539 break; 1540 default: 1541 ide_abort_command(s); 1542 return true; 1543 } 1544 1545 return true; 1546 } 1547 1548 1549 /*** SMART commands ***/ 1550 1551 static bool cmd_smart(IDEState *s, uint8_t cmd) 1552 { 1553 int n; 1554 1555 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) { 1556 goto abort_cmd; 1557 } 1558 1559 if (!s->smart_enabled && s->feature != SMART_ENABLE) { 1560 goto abort_cmd; 1561 } 1562 1563 switch (s->feature) { 1564 case SMART_DISABLE: 1565 s->smart_enabled = 0; 1566 return true; 1567 1568 case SMART_ENABLE: 1569 s->smart_enabled = 1; 1570 return true; 1571 1572 case SMART_ATTR_AUTOSAVE: 1573 switch (s->sector) { 1574 case 0x00: 1575 s->smart_autosave = 0; 1576 break; 1577 case 0xf1: 1578 s->smart_autosave = 1; 1579 break; 1580 default: 1581 goto abort_cmd; 1582 } 1583 return true; 1584 1585 case SMART_STATUS: 1586 if (!s->smart_errors) { 1587 s->hcyl = 0xc2; 1588 s->lcyl = 0x4f; 1589 } else { 1590 s->hcyl = 0x2c; 1591 s->lcyl = 0xf4; 1592 } 1593 return true; 1594 1595 case SMART_READ_THRESH: 1596 memset(s->io_buffer, 0, 0x200); 1597 s->io_buffer[0] = 0x01; /* smart struct version */ 1598 1599 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) { 1600 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0]; 1601 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11]; 1602 } 1603 1604 /* checksum */ 1605 for (n = 0; n < 511; n++) { 1606 s->io_buffer[511] += s->io_buffer[n]; 1607 } 1608 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1609 1610 s->status = READY_STAT | SEEK_STAT; 1611 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1612 ide_set_irq(s->bus); 1613 return false; 1614 1615 case SMART_READ_DATA: 1616 memset(s->io_buffer, 0, 0x200); 1617 s->io_buffer[0] = 0x01; /* smart struct version */ 1618 1619 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) { 1620 int i; 1621 for (i = 0; i < 11; i++) { 1622 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i]; 1623 } 1624 } 1625 1626 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00); 1627 if (s->smart_selftest_count == 0) { 1628 s->io_buffer[363] = 0; 1629 } else { 1630 s->io_buffer[363] = 1631 s->smart_selftest_data[3 + 1632 (s->smart_selftest_count - 1) * 1633 24]; 1634 } 1635 s->io_buffer[364] = 0x20; 1636 s->io_buffer[365] = 0x01; 1637 /* offline data collection capacity: execute + self-test*/ 1638 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1); 1639 s->io_buffer[368] = 0x03; /* smart capability (1) */ 1640 s->io_buffer[369] = 0x00; /* smart capability (2) */ 1641 s->io_buffer[370] = 0x01; /* error logging supported */ 1642 s->io_buffer[372] = 0x02; /* minutes for poll short test */ 1643 s->io_buffer[373] = 0x36; /* minutes for poll ext test */ 1644 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */ 1645 1646 for (n = 0; n < 511; n++) { 1647 s->io_buffer[511] += s->io_buffer[n]; 1648 } 1649 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1650 1651 s->status = READY_STAT | SEEK_STAT; 1652 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1653 ide_set_irq(s->bus); 1654 return false; 1655 1656 case SMART_READ_LOG: 1657 switch (s->sector) { 1658 case 0x01: /* summary smart error log */ 1659 memset(s->io_buffer, 0, 0x200); 1660 s->io_buffer[0] = 0x01; 1661 s->io_buffer[1] = 0x00; /* no error entries */ 1662 s->io_buffer[452] = s->smart_errors & 0xff; 1663 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8; 1664 1665 for (n = 0; n < 511; n++) { 1666 s->io_buffer[511] += s->io_buffer[n]; 1667 } 1668 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1669 break; 1670 case 0x06: /* smart self test log */ 1671 memset(s->io_buffer, 0, 0x200); 1672 s->io_buffer[0] = 0x01; 1673 if (s->smart_selftest_count == 0) { 1674 s->io_buffer[508] = 0; 1675 } else { 1676 s->io_buffer[508] = s->smart_selftest_count; 1677 for (n = 2; n < 506; n++) { 1678 s->io_buffer[n] = s->smart_selftest_data[n]; 1679 } 1680 } 1681 1682 for (n = 0; n < 511; n++) { 1683 s->io_buffer[511] += s->io_buffer[n]; 1684 } 1685 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1686 break; 1687 default: 1688 goto abort_cmd; 1689 } 1690 s->status = READY_STAT | SEEK_STAT; 1691 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1692 ide_set_irq(s->bus); 1693 return false; 1694 1695 case SMART_EXECUTE_OFFLINE: 1696 switch (s->sector) { 1697 case 0: /* off-line routine */ 1698 case 1: /* short self test */ 1699 case 2: /* extended self test */ 1700 s->smart_selftest_count++; 1701 if (s->smart_selftest_count > 21) { 1702 s->smart_selftest_count = 1; 1703 } 1704 n = 2 + (s->smart_selftest_count - 1) * 24; 1705 s->smart_selftest_data[n] = s->sector; 1706 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */ 1707 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */ 1708 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */ 1709 break; 1710 default: 1711 goto abort_cmd; 1712 } 1713 return true; 1714 } 1715 1716 abort_cmd: 1717 ide_abort_command(s); 1718 return true; 1719 } 1720 1721 #define HD_OK (1u << IDE_HD) 1722 #define CD_OK (1u << IDE_CD) 1723 #define CFA_OK (1u << IDE_CFATA) 1724 #define HD_CFA_OK (HD_OK | CFA_OK) 1725 #define ALL_OK (HD_OK | CD_OK | CFA_OK) 1726 1727 /* Set the Disk Seek Completed status bit during completion */ 1728 #define SET_DSC (1u << 8) 1729 1730 /* See ACS-2 T13/2015-D Table B.2 Command codes */ 1731 static const struct { 1732 /* Returns true if the completion code should be run */ 1733 bool (*handler)(IDEState *s, uint8_t cmd); 1734 int flags; 1735 } ide_cmd_table[0x100] = { 1736 /* NOP not implemented, mandatory for CD */ 1737 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK }, 1738 [WIN_DSM] = { cmd_data_set_management, ALL_OK }, 1739 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK }, 1740 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC}, 1741 [WIN_READ] = { cmd_read_pio, ALL_OK }, 1742 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK }, 1743 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK }, 1744 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK }, 1745 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC }, 1746 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK }, 1747 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK }, 1748 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK }, 1749 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK }, 1750 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK }, 1751 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK }, 1752 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK }, 1753 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK }, 1754 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1755 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1756 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1757 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC }, 1758 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK }, 1759 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK }, 1760 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC }, 1761 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK }, 1762 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK }, 1763 [WIN_STANDBY2] = { cmd_nop, ALL_OK }, 1764 [WIN_SETIDLE2] = { cmd_nop, ALL_OK }, 1765 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC }, 1766 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK }, 1767 [WIN_PACKETCMD] = { cmd_packet, CD_OK }, 1768 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK }, 1769 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC }, 1770 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK }, 1771 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC }, 1772 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK }, 1773 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK }, 1774 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC }, 1775 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK }, 1776 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK }, 1777 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK }, 1778 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK }, 1779 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK }, 1780 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK }, 1781 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK }, 1782 [WIN_STANDBY] = { cmd_nop, ALL_OK }, 1783 [WIN_SETIDLE1] = { cmd_nop, ALL_OK }, 1784 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC }, 1785 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK }, 1786 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK }, 1787 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK }, 1788 [WIN_IDENTIFY] = { cmd_identify, ALL_OK }, 1789 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC }, 1790 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC }, 1791 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC }, 1792 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC }, 1793 }; 1794 1795 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd) 1796 { 1797 return cmd < ARRAY_SIZE(ide_cmd_table) 1798 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind)); 1799 } 1800 1801 void ide_exec_cmd(IDEBus *bus, uint32_t val) 1802 { 1803 IDEState *s; 1804 bool complete; 1805 1806 #if defined(DEBUG_IDE) 1807 printf("ide: CMD=%02x\n", val); 1808 #endif 1809 s = idebus_active_if(bus); 1810 /* ignore commands to non existent slave */ 1811 if (s != bus->ifs && !s->blk) { 1812 return; 1813 } 1814 1815 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */ 1816 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET) 1817 return; 1818 1819 if (!ide_cmd_permitted(s, val)) { 1820 ide_abort_command(s); 1821 ide_set_irq(s->bus); 1822 return; 1823 } 1824 1825 s->status = READY_STAT | BUSY_STAT; 1826 s->error = 0; 1827 1828 complete = ide_cmd_table[val].handler(s, val); 1829 if (complete) { 1830 s->status &= ~BUSY_STAT; 1831 assert(!!s->error == !!(s->status & ERR_STAT)); 1832 1833 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) { 1834 s->status |= SEEK_STAT; 1835 } 1836 1837 ide_cmd_done(s); 1838 ide_set_irq(s->bus); 1839 } 1840 } 1841 1842 uint32_t ide_ioport_read(void *opaque, uint32_t addr1) 1843 { 1844 IDEBus *bus = opaque; 1845 IDEState *s = idebus_active_if(bus); 1846 uint32_t addr; 1847 int ret, hob; 1848 1849 addr = addr1 & 7; 1850 /* FIXME: HOB readback uses bit 7, but it's always set right now */ 1851 //hob = s->select & (1 << 7); 1852 hob = 0; 1853 switch(addr) { 1854 case 0: 1855 ret = 0xff; 1856 break; 1857 case 1: 1858 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) || 1859 (s != bus->ifs && !s->blk)) { 1860 ret = 0; 1861 } else if (!hob) { 1862 ret = s->error; 1863 } else { 1864 ret = s->hob_feature; 1865 } 1866 break; 1867 case 2: 1868 if (!bus->ifs[0].blk && !bus->ifs[1].blk) { 1869 ret = 0; 1870 } else if (!hob) { 1871 ret = s->nsector & 0xff; 1872 } else { 1873 ret = s->hob_nsector; 1874 } 1875 break; 1876 case 3: 1877 if (!bus->ifs[0].blk && !bus->ifs[1].blk) { 1878 ret = 0; 1879 } else if (!hob) { 1880 ret = s->sector; 1881 } else { 1882 ret = s->hob_sector; 1883 } 1884 break; 1885 case 4: 1886 if (!bus->ifs[0].blk && !bus->ifs[1].blk) { 1887 ret = 0; 1888 } else if (!hob) { 1889 ret = s->lcyl; 1890 } else { 1891 ret = s->hob_lcyl; 1892 } 1893 break; 1894 case 5: 1895 if (!bus->ifs[0].blk && !bus->ifs[1].blk) { 1896 ret = 0; 1897 } else if (!hob) { 1898 ret = s->hcyl; 1899 } else { 1900 ret = s->hob_hcyl; 1901 } 1902 break; 1903 case 6: 1904 if (!bus->ifs[0].blk && !bus->ifs[1].blk) { 1905 ret = 0; 1906 } else { 1907 ret = s->select; 1908 } 1909 break; 1910 default: 1911 case 7: 1912 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) || 1913 (s != bus->ifs && !s->blk)) { 1914 ret = 0; 1915 } else { 1916 ret = s->status; 1917 } 1918 qemu_irq_lower(bus->irq); 1919 break; 1920 } 1921 #ifdef DEBUG_IDE 1922 printf("ide: read addr=0x%x val=%02x\n", addr1, ret); 1923 #endif 1924 return ret; 1925 } 1926 1927 uint32_t ide_status_read(void *opaque, uint32_t addr) 1928 { 1929 IDEBus *bus = opaque; 1930 IDEState *s = idebus_active_if(bus); 1931 int ret; 1932 1933 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) || 1934 (s != bus->ifs && !s->blk)) { 1935 ret = 0; 1936 } else { 1937 ret = s->status; 1938 } 1939 #ifdef DEBUG_IDE 1940 printf("ide: read status addr=0x%x val=%02x\n", addr, ret); 1941 #endif 1942 return ret; 1943 } 1944 1945 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) 1946 { 1947 IDEBus *bus = opaque; 1948 IDEState *s; 1949 int i; 1950 1951 #ifdef DEBUG_IDE 1952 printf("ide: write control addr=0x%x val=%02x\n", addr, val); 1953 #endif 1954 /* common for both drives */ 1955 if (!(bus->cmd & IDE_CMD_RESET) && 1956 (val & IDE_CMD_RESET)) { 1957 /* reset low to high */ 1958 for(i = 0;i < 2; i++) { 1959 s = &bus->ifs[i]; 1960 s->status = BUSY_STAT | SEEK_STAT; 1961 s->error = 0x01; 1962 } 1963 } else if ((bus->cmd & IDE_CMD_RESET) && 1964 !(val & IDE_CMD_RESET)) { 1965 /* high to low */ 1966 for(i = 0;i < 2; i++) { 1967 s = &bus->ifs[i]; 1968 if (s->drive_kind == IDE_CD) 1969 s->status = 0x00; /* NOTE: READY is _not_ set */ 1970 else 1971 s->status = READY_STAT | SEEK_STAT; 1972 ide_set_signature(s); 1973 } 1974 } 1975 1976 bus->cmd = val; 1977 } 1978 1979 /* 1980 * Returns true if the running PIO transfer is a PIO out (i.e. data is 1981 * transferred from the device to the guest), false if it's a PIO in 1982 */ 1983 static bool ide_is_pio_out(IDEState *s) 1984 { 1985 if (s->end_transfer_func == ide_sector_write || 1986 s->end_transfer_func == ide_atapi_cmd) { 1987 return false; 1988 } else if (s->end_transfer_func == ide_sector_read || 1989 s->end_transfer_func == ide_transfer_stop || 1990 s->end_transfer_func == ide_atapi_cmd_reply_end || 1991 s->end_transfer_func == ide_dummy_transfer_stop) { 1992 return true; 1993 } 1994 1995 abort(); 1996 } 1997 1998 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val) 1999 { 2000 IDEBus *bus = opaque; 2001 IDEState *s = idebus_active_if(bus); 2002 uint8_t *p; 2003 2004 /* PIO data access allowed only when DRQ bit is set. The result of a write 2005 * during PIO out is indeterminate, just ignore it. */ 2006 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { 2007 return; 2008 } 2009 2010 p = s->data_ptr; 2011 *(uint16_t *)p = le16_to_cpu(val); 2012 p += 2; 2013 s->data_ptr = p; 2014 if (p >= s->data_end) 2015 s->end_transfer_func(s); 2016 } 2017 2018 uint32_t ide_data_readw(void *opaque, uint32_t addr) 2019 { 2020 IDEBus *bus = opaque; 2021 IDEState *s = idebus_active_if(bus); 2022 uint8_t *p; 2023 int ret; 2024 2025 /* PIO data access allowed only when DRQ bit is set. The result of a read 2026 * during PIO in is indeterminate, return 0 and don't move forward. */ 2027 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { 2028 return 0; 2029 } 2030 2031 p = s->data_ptr; 2032 ret = cpu_to_le16(*(uint16_t *)p); 2033 p += 2; 2034 s->data_ptr = p; 2035 if (p >= s->data_end) 2036 s->end_transfer_func(s); 2037 return ret; 2038 } 2039 2040 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val) 2041 { 2042 IDEBus *bus = opaque; 2043 IDEState *s = idebus_active_if(bus); 2044 uint8_t *p; 2045 2046 /* PIO data access allowed only when DRQ bit is set. The result of a write 2047 * during PIO out is indeterminate, just ignore it. */ 2048 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { 2049 return; 2050 } 2051 2052 p = s->data_ptr; 2053 *(uint32_t *)p = le32_to_cpu(val); 2054 p += 4; 2055 s->data_ptr = p; 2056 if (p >= s->data_end) 2057 s->end_transfer_func(s); 2058 } 2059 2060 uint32_t ide_data_readl(void *opaque, uint32_t addr) 2061 { 2062 IDEBus *bus = opaque; 2063 IDEState *s = idebus_active_if(bus); 2064 uint8_t *p; 2065 int ret; 2066 2067 /* PIO data access allowed only when DRQ bit is set. The result of a read 2068 * during PIO in is indeterminate, return 0 and don't move forward. */ 2069 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { 2070 return 0; 2071 } 2072 2073 p = s->data_ptr; 2074 ret = cpu_to_le32(*(uint32_t *)p); 2075 p += 4; 2076 s->data_ptr = p; 2077 if (p >= s->data_end) 2078 s->end_transfer_func(s); 2079 return ret; 2080 } 2081 2082 static void ide_dummy_transfer_stop(IDEState *s) 2083 { 2084 s->data_ptr = s->io_buffer; 2085 s->data_end = s->io_buffer; 2086 s->io_buffer[0] = 0xff; 2087 s->io_buffer[1] = 0xff; 2088 s->io_buffer[2] = 0xff; 2089 s->io_buffer[3] = 0xff; 2090 } 2091 2092 static void ide_reset(IDEState *s) 2093 { 2094 #ifdef DEBUG_IDE 2095 printf("ide: reset\n"); 2096 #endif 2097 2098 if (s->pio_aiocb) { 2099 blk_aio_cancel(s->pio_aiocb); 2100 s->pio_aiocb = NULL; 2101 } 2102 2103 if (s->drive_kind == IDE_CFATA) 2104 s->mult_sectors = 0; 2105 else 2106 s->mult_sectors = MAX_MULT_SECTORS; 2107 /* ide regs */ 2108 s->feature = 0; 2109 s->error = 0; 2110 s->nsector = 0; 2111 s->sector = 0; 2112 s->lcyl = 0; 2113 s->hcyl = 0; 2114 2115 /* lba48 */ 2116 s->hob_feature = 0; 2117 s->hob_sector = 0; 2118 s->hob_nsector = 0; 2119 s->hob_lcyl = 0; 2120 s->hob_hcyl = 0; 2121 2122 s->select = 0xa0; 2123 s->status = READY_STAT | SEEK_STAT; 2124 2125 s->lba48 = 0; 2126 2127 /* ATAPI specific */ 2128 s->sense_key = 0; 2129 s->asc = 0; 2130 s->cdrom_changed = 0; 2131 s->packet_transfer_size = 0; 2132 s->elementary_transfer_size = 0; 2133 s->io_buffer_index = 0; 2134 s->cd_sector_size = 0; 2135 s->atapi_dma = 0; 2136 s->tray_locked = 0; 2137 s->tray_open = 0; 2138 /* ATA DMA state */ 2139 s->io_buffer_size = 0; 2140 s->req_nb_sectors = 0; 2141 2142 ide_set_signature(s); 2143 /* init the transfer handler so that 0xffff is returned on data 2144 accesses */ 2145 s->end_transfer_func = ide_dummy_transfer_stop; 2146 ide_dummy_transfer_stop(s); 2147 s->media_changed = 0; 2148 } 2149 2150 void ide_bus_reset(IDEBus *bus) 2151 { 2152 bus->unit = 0; 2153 bus->cmd = 0; 2154 ide_reset(&bus->ifs[0]); 2155 ide_reset(&bus->ifs[1]); 2156 ide_clear_hob(bus); 2157 2158 /* pending async DMA */ 2159 if (bus->dma->aiocb) { 2160 #ifdef DEBUG_AIO 2161 printf("aio_cancel\n"); 2162 #endif 2163 blk_aio_cancel(bus->dma->aiocb); 2164 bus->dma->aiocb = NULL; 2165 } 2166 2167 /* reset dma provider too */ 2168 if (bus->dma->ops->reset) { 2169 bus->dma->ops->reset(bus->dma); 2170 } 2171 } 2172 2173 static bool ide_cd_is_tray_open(void *opaque) 2174 { 2175 return ((IDEState *)opaque)->tray_open; 2176 } 2177 2178 static bool ide_cd_is_medium_locked(void *opaque) 2179 { 2180 return ((IDEState *)opaque)->tray_locked; 2181 } 2182 2183 static void ide_resize_cb(void *opaque) 2184 { 2185 IDEState *s = opaque; 2186 uint64_t nb_sectors; 2187 2188 if (!s->identify_set) { 2189 return; 2190 } 2191 2192 blk_get_geometry(s->blk, &nb_sectors); 2193 s->nb_sectors = nb_sectors; 2194 2195 /* Update the identify data buffer. */ 2196 if (s->drive_kind == IDE_CFATA) { 2197 ide_cfata_identify_size(s); 2198 } else { 2199 /* IDE_CD uses a different set of callbacks entirely. */ 2200 assert(s->drive_kind != IDE_CD); 2201 ide_identify_size(s); 2202 } 2203 } 2204 2205 static const BlockDevOps ide_cd_block_ops = { 2206 .change_media_cb = ide_cd_change_cb, 2207 .eject_request_cb = ide_cd_eject_request_cb, 2208 .is_tray_open = ide_cd_is_tray_open, 2209 .is_medium_locked = ide_cd_is_medium_locked, 2210 }; 2211 2212 static const BlockDevOps ide_hd_block_ops = { 2213 .resize_cb = ide_resize_cb, 2214 }; 2215 2216 int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind, 2217 const char *version, const char *serial, const char *model, 2218 uint64_t wwn, 2219 uint32_t cylinders, uint32_t heads, uint32_t secs, 2220 int chs_trans) 2221 { 2222 uint64_t nb_sectors; 2223 2224 s->blk = blk; 2225 s->drive_kind = kind; 2226 2227 blk_get_geometry(blk, &nb_sectors); 2228 s->cylinders = cylinders; 2229 s->heads = heads; 2230 s->sectors = secs; 2231 s->chs_trans = chs_trans; 2232 s->nb_sectors = nb_sectors; 2233 s->wwn = wwn; 2234 /* The SMART values should be preserved across power cycles 2235 but they aren't. */ 2236 s->smart_enabled = 1; 2237 s->smart_autosave = 1; 2238 s->smart_errors = 0; 2239 s->smart_selftest_count = 0; 2240 if (kind == IDE_CD) { 2241 blk_set_dev_ops(blk, &ide_cd_block_ops, s); 2242 blk_set_guest_block_size(blk, 2048); 2243 } else { 2244 if (!blk_is_inserted(s->blk)) { 2245 error_report("Device needs media, but drive is empty"); 2246 return -1; 2247 } 2248 if (blk_is_read_only(blk)) { 2249 error_report("Can't use a read-only drive"); 2250 return -1; 2251 } 2252 blk_set_dev_ops(blk, &ide_hd_block_ops, s); 2253 } 2254 if (serial) { 2255 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial); 2256 } else { 2257 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str), 2258 "QM%05d", s->drive_serial); 2259 } 2260 if (model) { 2261 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model); 2262 } else { 2263 switch (kind) { 2264 case IDE_CD: 2265 strcpy(s->drive_model_str, "QEMU DVD-ROM"); 2266 break; 2267 case IDE_CFATA: 2268 strcpy(s->drive_model_str, "QEMU MICRODRIVE"); 2269 break; 2270 default: 2271 strcpy(s->drive_model_str, "QEMU HARDDISK"); 2272 break; 2273 } 2274 } 2275 2276 if (version) { 2277 pstrcpy(s->version, sizeof(s->version), version); 2278 } else { 2279 pstrcpy(s->version, sizeof(s->version), qemu_get_version()); 2280 } 2281 2282 ide_reset(s); 2283 blk_iostatus_enable(blk); 2284 return 0; 2285 } 2286 2287 static void ide_init1(IDEBus *bus, int unit) 2288 { 2289 static int drive_serial = 1; 2290 IDEState *s = &bus->ifs[unit]; 2291 2292 s->bus = bus; 2293 s->unit = unit; 2294 s->drive_serial = drive_serial++; 2295 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */ 2296 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; 2297 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len); 2298 memset(s->io_buffer, 0, s->io_buffer_total_len); 2299 2300 s->smart_selftest_data = blk_blockalign(s->blk, 512); 2301 memset(s->smart_selftest_data, 0, 512); 2302 2303 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2304 ide_sector_write_timer_cb, s); 2305 } 2306 2307 static int ide_nop_int(IDEDMA *dma, int x) 2308 { 2309 return 0; 2310 } 2311 2312 static void ide_nop_restart(void *opaque, int x, RunState y) 2313 { 2314 } 2315 2316 static const IDEDMAOps ide_dma_nop_ops = { 2317 .prepare_buf = ide_nop_int, 2318 .rw_buf = ide_nop_int, 2319 .set_unit = ide_nop_int, 2320 .restart_cb = ide_nop_restart, 2321 }; 2322 2323 static IDEDMA ide_dma_nop = { 2324 .ops = &ide_dma_nop_ops, 2325 .aiocb = NULL, 2326 }; 2327 2328 void ide_init2(IDEBus *bus, qemu_irq irq) 2329 { 2330 int i; 2331 2332 for(i = 0; i < 2; i++) { 2333 ide_init1(bus, i); 2334 ide_reset(&bus->ifs[i]); 2335 } 2336 bus->irq = irq; 2337 bus->dma = &ide_dma_nop; 2338 } 2339 2340 static const MemoryRegionPortio ide_portio_list[] = { 2341 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write }, 2342 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew }, 2343 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel }, 2344 PORTIO_END_OF_LIST(), 2345 }; 2346 2347 static const MemoryRegionPortio ide_portio2_list[] = { 2348 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write }, 2349 PORTIO_END_OF_LIST(), 2350 }; 2351 2352 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2) 2353 { 2354 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA 2355 bridge has been setup properly to always register with ISA. */ 2356 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide"); 2357 2358 if (iobase2) { 2359 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide"); 2360 } 2361 } 2362 2363 static bool is_identify_set(void *opaque, int version_id) 2364 { 2365 IDEState *s = opaque; 2366 2367 return s->identify_set != 0; 2368 } 2369 2370 static EndTransferFunc* transfer_end_table[] = { 2371 ide_sector_read, 2372 ide_sector_write, 2373 ide_transfer_stop, 2374 ide_atapi_cmd_reply_end, 2375 ide_atapi_cmd, 2376 ide_dummy_transfer_stop, 2377 }; 2378 2379 static int transfer_end_table_idx(EndTransferFunc *fn) 2380 { 2381 int i; 2382 2383 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++) 2384 if (transfer_end_table[i] == fn) 2385 return i; 2386 2387 return -1; 2388 } 2389 2390 static int ide_drive_post_load(void *opaque, int version_id) 2391 { 2392 IDEState *s = opaque; 2393 2394 if (s->identify_set) { 2395 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5))); 2396 } 2397 return 0; 2398 } 2399 2400 static int ide_drive_pio_post_load(void *opaque, int version_id) 2401 { 2402 IDEState *s = opaque; 2403 2404 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) { 2405 return -EINVAL; 2406 } 2407 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx]; 2408 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset; 2409 s->data_end = s->data_ptr + s->cur_io_buffer_len; 2410 2411 return 0; 2412 } 2413 2414 static void ide_drive_pio_pre_save(void *opaque) 2415 { 2416 IDEState *s = opaque; 2417 int idx; 2418 2419 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer; 2420 s->cur_io_buffer_len = s->data_end - s->data_ptr; 2421 2422 idx = transfer_end_table_idx(s->end_transfer_func); 2423 if (idx == -1) { 2424 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n", 2425 __func__); 2426 s->end_transfer_fn_idx = 2; 2427 } else { 2428 s->end_transfer_fn_idx = idx; 2429 } 2430 } 2431 2432 static bool ide_drive_pio_state_needed(void *opaque) 2433 { 2434 IDEState *s = opaque; 2435 2436 return ((s->status & DRQ_STAT) != 0) 2437 || (s->bus->error_status & IDE_RETRY_PIO); 2438 } 2439 2440 static bool ide_tray_state_needed(void *opaque) 2441 { 2442 IDEState *s = opaque; 2443 2444 return s->tray_open || s->tray_locked; 2445 } 2446 2447 static bool ide_atapi_gesn_needed(void *opaque) 2448 { 2449 IDEState *s = opaque; 2450 2451 return s->events.new_media || s->events.eject_request; 2452 } 2453 2454 static bool ide_error_needed(void *opaque) 2455 { 2456 IDEBus *bus = opaque; 2457 2458 return (bus->error_status != 0); 2459 } 2460 2461 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */ 2462 static const VMStateDescription vmstate_ide_atapi_gesn_state = { 2463 .name ="ide_drive/atapi/gesn_state", 2464 .version_id = 1, 2465 .minimum_version_id = 1, 2466 .fields = (VMStateField[]) { 2467 VMSTATE_BOOL(events.new_media, IDEState), 2468 VMSTATE_BOOL(events.eject_request, IDEState), 2469 VMSTATE_END_OF_LIST() 2470 } 2471 }; 2472 2473 static const VMStateDescription vmstate_ide_tray_state = { 2474 .name = "ide_drive/tray_state", 2475 .version_id = 1, 2476 .minimum_version_id = 1, 2477 .fields = (VMStateField[]) { 2478 VMSTATE_BOOL(tray_open, IDEState), 2479 VMSTATE_BOOL(tray_locked, IDEState), 2480 VMSTATE_END_OF_LIST() 2481 } 2482 }; 2483 2484 static const VMStateDescription vmstate_ide_drive_pio_state = { 2485 .name = "ide_drive/pio_state", 2486 .version_id = 1, 2487 .minimum_version_id = 1, 2488 .pre_save = ide_drive_pio_pre_save, 2489 .post_load = ide_drive_pio_post_load, 2490 .fields = (VMStateField[]) { 2491 VMSTATE_INT32(req_nb_sectors, IDEState), 2492 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1, 2493 vmstate_info_uint8, uint8_t), 2494 VMSTATE_INT32(cur_io_buffer_offset, IDEState), 2495 VMSTATE_INT32(cur_io_buffer_len, IDEState), 2496 VMSTATE_UINT8(end_transfer_fn_idx, IDEState), 2497 VMSTATE_INT32(elementary_transfer_size, IDEState), 2498 VMSTATE_INT32(packet_transfer_size, IDEState), 2499 VMSTATE_END_OF_LIST() 2500 } 2501 }; 2502 2503 const VMStateDescription vmstate_ide_drive = { 2504 .name = "ide_drive", 2505 .version_id = 3, 2506 .minimum_version_id = 0, 2507 .post_load = ide_drive_post_load, 2508 .fields = (VMStateField[]) { 2509 VMSTATE_INT32(mult_sectors, IDEState), 2510 VMSTATE_INT32(identify_set, IDEState), 2511 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set), 2512 VMSTATE_UINT8(feature, IDEState), 2513 VMSTATE_UINT8(error, IDEState), 2514 VMSTATE_UINT32(nsector, IDEState), 2515 VMSTATE_UINT8(sector, IDEState), 2516 VMSTATE_UINT8(lcyl, IDEState), 2517 VMSTATE_UINT8(hcyl, IDEState), 2518 VMSTATE_UINT8(hob_feature, IDEState), 2519 VMSTATE_UINT8(hob_sector, IDEState), 2520 VMSTATE_UINT8(hob_nsector, IDEState), 2521 VMSTATE_UINT8(hob_lcyl, IDEState), 2522 VMSTATE_UINT8(hob_hcyl, IDEState), 2523 VMSTATE_UINT8(select, IDEState), 2524 VMSTATE_UINT8(status, IDEState), 2525 VMSTATE_UINT8(lba48, IDEState), 2526 VMSTATE_UINT8(sense_key, IDEState), 2527 VMSTATE_UINT8(asc, IDEState), 2528 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3), 2529 VMSTATE_END_OF_LIST() 2530 }, 2531 .subsections = (VMStateSubsection []) { 2532 { 2533 .vmsd = &vmstate_ide_drive_pio_state, 2534 .needed = ide_drive_pio_state_needed, 2535 }, { 2536 .vmsd = &vmstate_ide_tray_state, 2537 .needed = ide_tray_state_needed, 2538 }, { 2539 .vmsd = &vmstate_ide_atapi_gesn_state, 2540 .needed = ide_atapi_gesn_needed, 2541 }, { 2542 /* empty */ 2543 } 2544 } 2545 }; 2546 2547 static const VMStateDescription vmstate_ide_error_status = { 2548 .name ="ide_bus/error", 2549 .version_id = 1, 2550 .minimum_version_id = 1, 2551 .fields = (VMStateField[]) { 2552 VMSTATE_INT32(error_status, IDEBus), 2553 VMSTATE_END_OF_LIST() 2554 } 2555 }; 2556 2557 const VMStateDescription vmstate_ide_bus = { 2558 .name = "ide_bus", 2559 .version_id = 1, 2560 .minimum_version_id = 1, 2561 .fields = (VMStateField[]) { 2562 VMSTATE_UINT8(cmd, IDEBus), 2563 VMSTATE_UINT8(unit, IDEBus), 2564 VMSTATE_END_OF_LIST() 2565 }, 2566 .subsections = (VMStateSubsection []) { 2567 { 2568 .vmsd = &vmstate_ide_error_status, 2569 .needed = ide_error_needed, 2570 }, { 2571 /* empty */ 2572 } 2573 } 2574 }; 2575 2576 void ide_drive_get(DriveInfo **hd, int n) 2577 { 2578 int i; 2579 int highest_bus = drive_get_max_bus(IF_IDE) + 1; 2580 int max_devs = drive_get_max_devs(IF_IDE); 2581 int n_buses = max_devs ? (n / max_devs) : n; 2582 2583 /* 2584 * Note: The number of actual buses available is not known. 2585 * We compute this based on the size of the DriveInfo* array, n. 2586 * If it is less than max_devs * <num_real_buses>, 2587 * We will stop looking for drives prematurely instead of overfilling 2588 * the array. 2589 */ 2590 2591 if (highest_bus > n_buses) { 2592 error_report("Too many IDE buses defined (%d > %d)", 2593 highest_bus, n_buses); 2594 exit(1); 2595 } 2596 2597 for (i = 0; i < n; i++) { 2598 hd[i] = drive_get_by_index(IF_IDE, i); 2599 } 2600 } 2601