1 /* 2 * QEMU IDE disk and CD/DVD-ROM Emulator 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include <hw/hw.h> 26 #include <hw/i386/pc.h> 27 #include <hw/pci/pci.h> 28 #include <hw/isa/isa.h> 29 #include "qemu/error-report.h" 30 #include "qemu/timer.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/dma.h" 33 #include "hw/block/block.h" 34 #include "sysemu/blockdev.h" 35 36 #include <hw/ide/internal.h> 37 38 /* These values were based on a Seagate ST3500418AS but have been modified 39 to make more sense in QEMU */ 40 static const int smart_attributes[][12] = { 41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */ 42 /* raw read error rate*/ 43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06}, 44 /* spin up */ 45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 46 /* start stop count */ 47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14}, 48 /* remapped sectors */ 49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24}, 50 /* power on hours */ 51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 52 /* power cycle count */ 53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 54 /* airflow-temperature-celsius */ 55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32}, 56 }; 57 58 static int ide_handle_rw_error(IDEState *s, int error, int op); 59 static void ide_dummy_transfer_stop(IDEState *s); 60 61 static void padstr(char *str, const char *src, int len) 62 { 63 int i, v; 64 for(i = 0; i < len; i++) { 65 if (*src) 66 v = *src++; 67 else 68 v = ' '; 69 str[i^1] = v; 70 } 71 } 72 73 static void put_le16(uint16_t *p, unsigned int v) 74 { 75 *p = cpu_to_le16(v); 76 } 77 78 static void ide_identify_size(IDEState *s) 79 { 80 uint16_t *p = (uint16_t *)s->identify_data; 81 put_le16(p + 60, s->nb_sectors); 82 put_le16(p + 61, s->nb_sectors >> 16); 83 put_le16(p + 100, s->nb_sectors); 84 put_le16(p + 101, s->nb_sectors >> 16); 85 put_le16(p + 102, s->nb_sectors >> 32); 86 put_le16(p + 103, s->nb_sectors >> 48); 87 } 88 89 static void ide_identify(IDEState *s) 90 { 91 uint16_t *p; 92 unsigned int oldsize; 93 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master; 94 95 p = (uint16_t *)s->identify_data; 96 if (s->identify_set) { 97 goto fill_buffer; 98 } 99 memset(p, 0, sizeof(s->identify_data)); 100 101 put_le16(p + 0, 0x0040); 102 put_le16(p + 1, s->cylinders); 103 put_le16(p + 3, s->heads); 104 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */ 105 put_le16(p + 5, 512); /* XXX: retired, remove ? */ 106 put_le16(p + 6, s->sectors); 107 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 108 put_le16(p + 20, 3); /* XXX: retired, remove ? */ 109 put_le16(p + 21, 512); /* cache size in sectors */ 110 put_le16(p + 22, 4); /* ecc bytes */ 111 padstr((char *)(p + 23), s->version, 8); /* firmware version */ 112 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */ 113 #if MAX_MULT_SECTORS > 1 114 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); 115 #endif 116 put_le16(p + 48, 1); /* dword I/O */ 117 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */ 118 put_le16(p + 51, 0x200); /* PIO transfer cycle */ 119 put_le16(p + 52, 0x200); /* DMA transfer cycle */ 120 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */ 121 put_le16(p + 54, s->cylinders); 122 put_le16(p + 55, s->heads); 123 put_le16(p + 56, s->sectors); 124 oldsize = s->cylinders * s->heads * s->sectors; 125 put_le16(p + 57, oldsize); 126 put_le16(p + 58, oldsize >> 16); 127 if (s->mult_sectors) 128 put_le16(p + 59, 0x100 | s->mult_sectors); 129 /* *(p + 60) := nb_sectors -- see ide_identify_size */ 130 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */ 131 put_le16(p + 62, 0x07); /* single word dma0-2 supported */ 132 put_le16(p + 63, 0x07); /* mdma0-2 supported */ 133 put_le16(p + 64, 0x03); /* pio3-4 supported */ 134 put_le16(p + 65, 120); 135 put_le16(p + 66, 120); 136 put_le16(p + 67, 120); 137 put_le16(p + 68, 120); 138 if (dev && dev->conf.discard_granularity) { 139 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */ 140 } 141 142 if (s->ncq_queues) { 143 put_le16(p + 75, s->ncq_queues - 1); 144 /* NCQ supported */ 145 put_le16(p + 76, (1 << 8)); 146 } 147 148 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */ 149 put_le16(p + 81, 0x16); /* conforms to ata5 */ 150 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */ 151 put_le16(p + 82, (1 << 14) | (1 << 5) | 1); 152 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ 153 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); 154 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */ 155 if (s->wwn) { 156 put_le16(p + 84, (1 << 14) | (1 << 8) | 0); 157 } else { 158 put_le16(p + 84, (1 << 14) | 0); 159 } 160 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */ 161 if (bdrv_enable_write_cache(s->bs)) 162 put_le16(p + 85, (1 << 14) | (1 << 5) | 1); 163 else 164 put_le16(p + 85, (1 << 14) | 1); 165 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ 166 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10)); 167 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */ 168 if (s->wwn) { 169 put_le16(p + 87, (1 << 14) | (1 << 8) | 0); 170 } else { 171 put_le16(p + 87, (1 << 14) | 0); 172 } 173 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ 174 put_le16(p + 93, 1 | (1 << 14) | 0x2000); 175 /* *(p + 100) := nb_sectors -- see ide_identify_size */ 176 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */ 177 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */ 178 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */ 179 180 if (dev && dev->conf.physical_block_size) 181 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf)); 182 if (s->wwn) { 183 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */ 184 put_le16(p + 108, s->wwn >> 48); 185 put_le16(p + 109, s->wwn >> 32); 186 put_le16(p + 110, s->wwn >> 16); 187 put_le16(p + 111, s->wwn); 188 } 189 if (dev && dev->conf.discard_granularity) { 190 put_le16(p + 169, 1); /* TRIM support */ 191 } 192 193 ide_identify_size(s); 194 s->identify_set = 1; 195 196 fill_buffer: 197 memcpy(s->io_buffer, p, sizeof(s->identify_data)); 198 } 199 200 static void ide_atapi_identify(IDEState *s) 201 { 202 uint16_t *p; 203 204 p = (uint16_t *)s->identify_data; 205 if (s->identify_set) { 206 goto fill_buffer; 207 } 208 memset(p, 0, sizeof(s->identify_data)); 209 210 /* Removable CDROM, 50us response, 12 byte packets */ 211 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0)); 212 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 213 put_le16(p + 20, 3); /* buffer type */ 214 put_le16(p + 21, 512); /* cache size in sectors */ 215 put_le16(p + 22, 4); /* ecc bytes */ 216 padstr((char *)(p + 23), s->version, 8); /* firmware version */ 217 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */ 218 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */ 219 #ifdef USE_DMA_CDROM 220 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */ 221 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */ 222 put_le16(p + 62, 7); /* single word dma0-2 supported */ 223 put_le16(p + 63, 7); /* mdma0-2 supported */ 224 #else 225 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */ 226 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */ 227 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */ 228 #endif 229 put_le16(p + 64, 3); /* pio3-4 supported */ 230 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */ 231 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */ 232 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */ 233 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */ 234 235 put_le16(p + 71, 30); /* in ns */ 236 put_le16(p + 72, 30); /* in ns */ 237 238 if (s->ncq_queues) { 239 put_le16(p + 75, s->ncq_queues - 1); 240 /* NCQ supported */ 241 put_le16(p + 76, (1 << 8)); 242 } 243 244 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */ 245 if (s->wwn) { 246 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */ 247 put_le16(p + 87, (1 << 8)); /* WWN enabled */ 248 } 249 250 #ifdef USE_DMA_CDROM 251 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ 252 #endif 253 254 if (s->wwn) { 255 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */ 256 put_le16(p + 108, s->wwn >> 48); 257 put_le16(p + 109, s->wwn >> 32); 258 put_le16(p + 110, s->wwn >> 16); 259 put_le16(p + 111, s->wwn); 260 } 261 262 s->identify_set = 1; 263 264 fill_buffer: 265 memcpy(s->io_buffer, p, sizeof(s->identify_data)); 266 } 267 268 static void ide_cfata_identify_size(IDEState *s) 269 { 270 uint16_t *p = (uint16_t *)s->identify_data; 271 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */ 272 put_le16(p + 8, s->nb_sectors); /* Sectors per card */ 273 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */ 274 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */ 275 } 276 277 static void ide_cfata_identify(IDEState *s) 278 { 279 uint16_t *p; 280 uint32_t cur_sec; 281 282 p = (uint16_t *)s->identify_data; 283 if (s->identify_set) { 284 goto fill_buffer; 285 } 286 memset(p, 0, sizeof(s->identify_data)); 287 288 cur_sec = s->cylinders * s->heads * s->sectors; 289 290 put_le16(p + 0, 0x848a); /* CF Storage Card signature */ 291 put_le16(p + 1, s->cylinders); /* Default cylinders */ 292 put_le16(p + 3, s->heads); /* Default heads */ 293 put_le16(p + 6, s->sectors); /* Default sectors per track */ 294 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */ 295 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */ 296 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 297 put_le16(p + 22, 0x0004); /* ECC bytes */ 298 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */ 299 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */ 300 #if MAX_MULT_SECTORS > 1 301 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); 302 #else 303 put_le16(p + 47, 0x0000); 304 #endif 305 put_le16(p + 49, 0x0f00); /* Capabilities */ 306 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */ 307 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */ 308 put_le16(p + 53, 0x0003); /* Translation params valid */ 309 put_le16(p + 54, s->cylinders); /* Current cylinders */ 310 put_le16(p + 55, s->heads); /* Current heads */ 311 put_le16(p + 56, s->sectors); /* Current sectors */ 312 put_le16(p + 57, cur_sec); /* Current capacity */ 313 put_le16(p + 58, cur_sec >> 16); /* Current capacity */ 314 if (s->mult_sectors) /* Multiple sector setting */ 315 put_le16(p + 59, 0x100 | s->mult_sectors); 316 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */ 317 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */ 318 put_le16(p + 63, 0x0203); /* Multiword DMA capability */ 319 put_le16(p + 64, 0x0001); /* Flow Control PIO support */ 320 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */ 321 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */ 322 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */ 323 put_le16(p + 82, 0x400c); /* Command Set supported */ 324 put_le16(p + 83, 0x7068); /* Command Set supported */ 325 put_le16(p + 84, 0x4000); /* Features supported */ 326 put_le16(p + 85, 0x000c); /* Command Set enabled */ 327 put_le16(p + 86, 0x7044); /* Command Set enabled */ 328 put_le16(p + 87, 0x4000); /* Features enabled */ 329 put_le16(p + 91, 0x4060); /* Current APM level */ 330 put_le16(p + 129, 0x0002); /* Current features option */ 331 put_le16(p + 130, 0x0005); /* Reassigned sectors */ 332 put_le16(p + 131, 0x0001); /* Initial power mode */ 333 put_le16(p + 132, 0x0000); /* User signature */ 334 put_le16(p + 160, 0x8100); /* Power requirement */ 335 put_le16(p + 161, 0x8001); /* CF command set */ 336 337 ide_cfata_identify_size(s); 338 s->identify_set = 1; 339 340 fill_buffer: 341 memcpy(s->io_buffer, p, sizeof(s->identify_data)); 342 } 343 344 static void ide_set_signature(IDEState *s) 345 { 346 s->select &= 0xf0; /* clear head */ 347 /* put signature */ 348 s->nsector = 1; 349 s->sector = 1; 350 if (s->drive_kind == IDE_CD) { 351 s->lcyl = 0x14; 352 s->hcyl = 0xeb; 353 } else if (s->bs) { 354 s->lcyl = 0; 355 s->hcyl = 0; 356 } else { 357 s->lcyl = 0xff; 358 s->hcyl = 0xff; 359 } 360 } 361 362 typedef struct TrimAIOCB { 363 BlockDriverAIOCB common; 364 QEMUBH *bh; 365 int ret; 366 QEMUIOVector *qiov; 367 BlockDriverAIOCB *aiocb; 368 int i, j; 369 } TrimAIOCB; 370 371 static void trim_aio_cancel(BlockDriverAIOCB *acb) 372 { 373 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common); 374 375 /* Exit the loop in case bdrv_aio_cancel calls ide_issue_trim_cb again. */ 376 iocb->j = iocb->qiov->niov - 1; 377 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1; 378 379 /* Tell ide_issue_trim_cb not to trigger the completion, too. */ 380 qemu_bh_delete(iocb->bh); 381 iocb->bh = NULL; 382 383 if (iocb->aiocb) { 384 bdrv_aio_cancel(iocb->aiocb); 385 } 386 qemu_aio_release(iocb); 387 } 388 389 static const AIOCBInfo trim_aiocb_info = { 390 .aiocb_size = sizeof(TrimAIOCB), 391 .cancel = trim_aio_cancel, 392 }; 393 394 static void ide_trim_bh_cb(void *opaque) 395 { 396 TrimAIOCB *iocb = opaque; 397 398 iocb->common.cb(iocb->common.opaque, iocb->ret); 399 400 qemu_bh_delete(iocb->bh); 401 iocb->bh = NULL; 402 qemu_aio_release(iocb); 403 } 404 405 static void ide_issue_trim_cb(void *opaque, int ret) 406 { 407 TrimAIOCB *iocb = opaque; 408 if (ret >= 0) { 409 while (iocb->j < iocb->qiov->niov) { 410 int j = iocb->j; 411 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) { 412 int i = iocb->i; 413 uint64_t *buffer = iocb->qiov->iov[j].iov_base; 414 415 /* 6-byte LBA + 2-byte range per entry */ 416 uint64_t entry = le64_to_cpu(buffer[i]); 417 uint64_t sector = entry & 0x0000ffffffffffffULL; 418 uint16_t count = entry >> 48; 419 420 if (count == 0) { 421 continue; 422 } 423 424 /* Got an entry! Submit and exit. */ 425 iocb->aiocb = bdrv_aio_discard(iocb->common.bs, sector, count, 426 ide_issue_trim_cb, opaque); 427 return; 428 } 429 430 iocb->j++; 431 iocb->i = -1; 432 } 433 } else { 434 iocb->ret = ret; 435 } 436 437 iocb->aiocb = NULL; 438 if (iocb->bh) { 439 qemu_bh_schedule(iocb->bh); 440 } 441 } 442 443 BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs, 444 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, 445 BlockDriverCompletionFunc *cb, void *opaque) 446 { 447 TrimAIOCB *iocb; 448 449 iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque); 450 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb); 451 iocb->ret = 0; 452 iocb->qiov = qiov; 453 iocb->i = -1; 454 iocb->j = 0; 455 ide_issue_trim_cb(iocb, 0); 456 return &iocb->common; 457 } 458 459 static inline void ide_abort_command(IDEState *s) 460 { 461 ide_transfer_stop(s); 462 s->status = READY_STAT | ERR_STAT; 463 s->error = ABRT_ERR; 464 } 465 466 /* prepare data transfer and tell what to do after */ 467 void ide_transfer_start(IDEState *s, uint8_t *buf, int size, 468 EndTransferFunc *end_transfer_func) 469 { 470 s->end_transfer_func = end_transfer_func; 471 s->data_ptr = buf; 472 s->data_end = buf + size; 473 if (!(s->status & ERR_STAT)) { 474 s->status |= DRQ_STAT; 475 } 476 if (s->bus->dma->ops->start_transfer) { 477 s->bus->dma->ops->start_transfer(s->bus->dma); 478 } 479 } 480 481 static void ide_cmd_done(IDEState *s) 482 { 483 if (s->bus->dma->ops->cmd_done) { 484 s->bus->dma->ops->cmd_done(s->bus->dma); 485 } 486 } 487 488 void ide_transfer_stop(IDEState *s) 489 { 490 s->end_transfer_func = ide_transfer_stop; 491 s->data_ptr = s->io_buffer; 492 s->data_end = s->io_buffer; 493 s->status &= ~DRQ_STAT; 494 ide_cmd_done(s); 495 } 496 497 int64_t ide_get_sector(IDEState *s) 498 { 499 int64_t sector_num; 500 if (s->select & 0x40) { 501 /* lba */ 502 if (!s->lba48) { 503 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | 504 (s->lcyl << 8) | s->sector; 505 } else { 506 sector_num = ((int64_t)s->hob_hcyl << 40) | 507 ((int64_t) s->hob_lcyl << 32) | 508 ((int64_t) s->hob_sector << 24) | 509 ((int64_t) s->hcyl << 16) | 510 ((int64_t) s->lcyl << 8) | s->sector; 511 } 512 } else { 513 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors + 514 (s->select & 0x0f) * s->sectors + (s->sector - 1); 515 } 516 return sector_num; 517 } 518 519 void ide_set_sector(IDEState *s, int64_t sector_num) 520 { 521 unsigned int cyl, r; 522 if (s->select & 0x40) { 523 if (!s->lba48) { 524 s->select = (s->select & 0xf0) | (sector_num >> 24); 525 s->hcyl = (sector_num >> 16); 526 s->lcyl = (sector_num >> 8); 527 s->sector = (sector_num); 528 } else { 529 s->sector = sector_num; 530 s->lcyl = sector_num >> 8; 531 s->hcyl = sector_num >> 16; 532 s->hob_sector = sector_num >> 24; 533 s->hob_lcyl = sector_num >> 32; 534 s->hob_hcyl = sector_num >> 40; 535 } 536 } else { 537 cyl = sector_num / (s->heads * s->sectors); 538 r = sector_num % (s->heads * s->sectors); 539 s->hcyl = cyl >> 8; 540 s->lcyl = cyl; 541 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f); 542 s->sector = (r % s->sectors) + 1; 543 } 544 } 545 546 static void ide_rw_error(IDEState *s) { 547 ide_abort_command(s); 548 ide_set_irq(s->bus); 549 } 550 551 static bool ide_sect_range_ok(IDEState *s, 552 uint64_t sector, uint64_t nb_sectors) 553 { 554 uint64_t total_sectors; 555 556 bdrv_get_geometry(s->bs, &total_sectors); 557 if (sector > total_sectors || nb_sectors > total_sectors - sector) { 558 return false; 559 } 560 return true; 561 } 562 563 static void ide_sector_read_cb(void *opaque, int ret) 564 { 565 IDEState *s = opaque; 566 int n; 567 568 s->pio_aiocb = NULL; 569 s->status &= ~BUSY_STAT; 570 571 block_acct_done(bdrv_get_stats(s->bs), &s->acct); 572 if (ret != 0) { 573 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO | 574 IDE_RETRY_READ)) { 575 return; 576 } 577 } 578 579 n = s->nsector; 580 if (n > s->req_nb_sectors) { 581 n = s->req_nb_sectors; 582 } 583 584 /* Allow the guest to read the io_buffer */ 585 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read); 586 587 ide_set_irq(s->bus); 588 589 ide_set_sector(s, ide_get_sector(s) + n); 590 s->nsector -= n; 591 } 592 593 void ide_sector_read(IDEState *s) 594 { 595 int64_t sector_num; 596 int n; 597 598 s->status = READY_STAT | SEEK_STAT; 599 s->error = 0; /* not needed by IDE spec, but needed by Windows */ 600 sector_num = ide_get_sector(s); 601 n = s->nsector; 602 603 if (n == 0) { 604 ide_transfer_stop(s); 605 return; 606 } 607 608 s->status |= BUSY_STAT; 609 610 if (n > s->req_nb_sectors) { 611 n = s->req_nb_sectors; 612 } 613 614 #if defined(DEBUG_IDE) 615 printf("sector=%" PRId64 "\n", sector_num); 616 #endif 617 618 if (!ide_sect_range_ok(s, sector_num, n)) { 619 ide_rw_error(s); 620 return; 621 } 622 623 s->iov.iov_base = s->io_buffer; 624 s->iov.iov_len = n * BDRV_SECTOR_SIZE; 625 qemu_iovec_init_external(&s->qiov, &s->iov, 1); 626 627 block_acct_start(bdrv_get_stats(s->bs), &s->acct, 628 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ); 629 s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n, 630 ide_sector_read_cb, s); 631 } 632 633 static void dma_buf_commit(IDEState *s) 634 { 635 qemu_sglist_destroy(&s->sg); 636 } 637 638 void ide_set_inactive(IDEState *s, bool more) 639 { 640 s->bus->dma->aiocb = NULL; 641 if (s->bus->dma->ops->set_inactive) { 642 s->bus->dma->ops->set_inactive(s->bus->dma, more); 643 } 644 ide_cmd_done(s); 645 } 646 647 void ide_dma_error(IDEState *s) 648 { 649 ide_abort_command(s); 650 ide_set_inactive(s, false); 651 ide_set_irq(s->bus); 652 } 653 654 static int ide_handle_rw_error(IDEState *s, int error, int op) 655 { 656 bool is_read = (op & IDE_RETRY_READ) != 0; 657 BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error); 658 659 if (action == BLOCK_ERROR_ACTION_STOP) { 660 s->bus->dma->ops->set_unit(s->bus->dma, s->unit); 661 s->bus->error_status = op; 662 } else if (action == BLOCK_ERROR_ACTION_REPORT) { 663 if (op & IDE_RETRY_DMA) { 664 dma_buf_commit(s); 665 ide_dma_error(s); 666 } else { 667 ide_rw_error(s); 668 } 669 } 670 bdrv_error_action(s->bs, action, is_read, error); 671 return action != BLOCK_ERROR_ACTION_IGNORE; 672 } 673 674 void ide_dma_cb(void *opaque, int ret) 675 { 676 IDEState *s = opaque; 677 int n; 678 int64_t sector_num; 679 bool stay_active = false; 680 681 if (ret < 0) { 682 int op = IDE_RETRY_DMA; 683 684 if (s->dma_cmd == IDE_DMA_READ) 685 op |= IDE_RETRY_READ; 686 else if (s->dma_cmd == IDE_DMA_TRIM) 687 op |= IDE_RETRY_TRIM; 688 689 if (ide_handle_rw_error(s, -ret, op)) { 690 return; 691 } 692 } 693 694 n = s->io_buffer_size >> 9; 695 if (n > s->nsector) { 696 /* The PRDs were longer than needed for this request. Shorten them so 697 * we don't get a negative remainder. The Active bit must remain set 698 * after the request completes. */ 699 n = s->nsector; 700 stay_active = true; 701 } 702 703 sector_num = ide_get_sector(s); 704 if (n > 0) { 705 dma_buf_commit(s); 706 sector_num += n; 707 ide_set_sector(s, sector_num); 708 s->nsector -= n; 709 } 710 711 /* end of transfer ? */ 712 if (s->nsector == 0) { 713 s->status = READY_STAT | SEEK_STAT; 714 ide_set_irq(s->bus); 715 goto eot; 716 } 717 718 /* launch next transfer */ 719 n = s->nsector; 720 s->io_buffer_index = 0; 721 s->io_buffer_size = n * 512; 722 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) { 723 /* The PRDs were too short. Reset the Active bit, but don't raise an 724 * interrupt. */ 725 s->status = READY_STAT | SEEK_STAT; 726 goto eot; 727 } 728 729 #ifdef DEBUG_AIO 730 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n", 731 sector_num, n, s->dma_cmd); 732 #endif 733 734 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) && 735 !ide_sect_range_ok(s, sector_num, n)) { 736 dma_buf_commit(s); 737 ide_dma_error(s); 738 return; 739 } 740 741 switch (s->dma_cmd) { 742 case IDE_DMA_READ: 743 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num, 744 ide_dma_cb, s); 745 break; 746 case IDE_DMA_WRITE: 747 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num, 748 ide_dma_cb, s); 749 break; 750 case IDE_DMA_TRIM: 751 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num, 752 ide_issue_trim, ide_dma_cb, s, 753 DMA_DIRECTION_TO_DEVICE); 754 break; 755 } 756 return; 757 758 eot: 759 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { 760 block_acct_done(bdrv_get_stats(s->bs), &s->acct); 761 } 762 ide_set_inactive(s, stay_active); 763 } 764 765 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd) 766 { 767 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; 768 s->io_buffer_index = 0; 769 s->io_buffer_size = 0; 770 s->dma_cmd = dma_cmd; 771 772 switch (dma_cmd) { 773 case IDE_DMA_READ: 774 block_acct_start(bdrv_get_stats(s->bs), &s->acct, 775 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ); 776 break; 777 case IDE_DMA_WRITE: 778 block_acct_start(bdrv_get_stats(s->bs), &s->acct, 779 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE); 780 break; 781 default: 782 break; 783 } 784 785 ide_start_dma(s, ide_dma_cb); 786 } 787 788 void ide_start_dma(IDEState *s, BlockDriverCompletionFunc *cb) 789 { 790 if (s->bus->dma->ops->start_dma) { 791 s->bus->dma->ops->start_dma(s->bus->dma, s, cb); 792 } 793 } 794 795 static void ide_sector_write_timer_cb(void *opaque) 796 { 797 IDEState *s = opaque; 798 ide_set_irq(s->bus); 799 } 800 801 static void ide_sector_write_cb(void *opaque, int ret) 802 { 803 IDEState *s = opaque; 804 int n; 805 806 block_acct_done(bdrv_get_stats(s->bs), &s->acct); 807 808 s->pio_aiocb = NULL; 809 s->status &= ~BUSY_STAT; 810 811 if (ret != 0) { 812 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) { 813 return; 814 } 815 } 816 817 n = s->nsector; 818 if (n > s->req_nb_sectors) { 819 n = s->req_nb_sectors; 820 } 821 s->nsector -= n; 822 if (s->nsector == 0) { 823 /* no more sectors to write */ 824 ide_transfer_stop(s); 825 } else { 826 int n1 = s->nsector; 827 if (n1 > s->req_nb_sectors) { 828 n1 = s->req_nb_sectors; 829 } 830 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE, 831 ide_sector_write); 832 } 833 ide_set_sector(s, ide_get_sector(s) + n); 834 835 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) { 836 /* It seems there is a bug in the Windows 2000 installer HDD 837 IDE driver which fills the disk with empty logs when the 838 IDE write IRQ comes too early. This hack tries to correct 839 that at the expense of slower write performances. Use this 840 option _only_ to install Windows 2000. You must disable it 841 for normal use. */ 842 timer_mod(s->sector_write_timer, 843 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000)); 844 } else { 845 ide_set_irq(s->bus); 846 } 847 } 848 849 void ide_sector_write(IDEState *s) 850 { 851 int64_t sector_num; 852 int n; 853 854 s->status = READY_STAT | SEEK_STAT | BUSY_STAT; 855 sector_num = ide_get_sector(s); 856 #if defined(DEBUG_IDE) 857 printf("sector=%" PRId64 "\n", sector_num); 858 #endif 859 n = s->nsector; 860 if (n > s->req_nb_sectors) { 861 n = s->req_nb_sectors; 862 } 863 864 if (!ide_sect_range_ok(s, sector_num, n)) { 865 ide_rw_error(s); 866 return; 867 } 868 869 s->iov.iov_base = s->io_buffer; 870 s->iov.iov_len = n * BDRV_SECTOR_SIZE; 871 qemu_iovec_init_external(&s->qiov, &s->iov, 1); 872 873 block_acct_start(bdrv_get_stats(s->bs), &s->acct, 874 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ); 875 s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n, 876 ide_sector_write_cb, s); 877 } 878 879 static void ide_flush_cb(void *opaque, int ret) 880 { 881 IDEState *s = opaque; 882 883 s->pio_aiocb = NULL; 884 885 if (ret < 0) { 886 /* XXX: What sector number to set here? */ 887 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) { 888 return; 889 } 890 } 891 892 if (s->bs) { 893 block_acct_done(bdrv_get_stats(s->bs), &s->acct); 894 } 895 s->status = READY_STAT | SEEK_STAT; 896 ide_cmd_done(s); 897 ide_set_irq(s->bus); 898 } 899 900 void ide_flush_cache(IDEState *s) 901 { 902 if (s->bs == NULL) { 903 ide_flush_cb(s, 0); 904 return; 905 } 906 907 s->status |= BUSY_STAT; 908 block_acct_start(bdrv_get_stats(s->bs), &s->acct, 0, BLOCK_ACCT_FLUSH); 909 s->pio_aiocb = bdrv_aio_flush(s->bs, ide_flush_cb, s); 910 } 911 912 static void ide_cfata_metadata_inquiry(IDEState *s) 913 { 914 uint16_t *p; 915 uint32_t spd; 916 917 p = (uint16_t *) s->io_buffer; 918 memset(p, 0, 0x200); 919 spd = ((s->mdata_size - 1) >> 9) + 1; 920 921 put_le16(p + 0, 0x0001); /* Data format revision */ 922 put_le16(p + 1, 0x0000); /* Media property: silicon */ 923 put_le16(p + 2, s->media_changed); /* Media status */ 924 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */ 925 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */ 926 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */ 927 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */ 928 } 929 930 static void ide_cfata_metadata_read(IDEState *s) 931 { 932 uint16_t *p; 933 934 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { 935 s->status = ERR_STAT; 936 s->error = ABRT_ERR; 937 return; 938 } 939 940 p = (uint16_t *) s->io_buffer; 941 memset(p, 0, 0x200); 942 943 put_le16(p + 0, s->media_changed); /* Media status */ 944 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), 945 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), 946 s->nsector << 9), 0x200 - 2)); 947 } 948 949 static void ide_cfata_metadata_write(IDEState *s) 950 { 951 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { 952 s->status = ERR_STAT; 953 s->error = ABRT_ERR; 954 return; 955 } 956 957 s->media_changed = 0; 958 959 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), 960 s->io_buffer + 2, 961 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), 962 s->nsector << 9), 0x200 - 2)); 963 } 964 965 /* called when the inserted state of the media has changed */ 966 static void ide_cd_change_cb(void *opaque, bool load) 967 { 968 IDEState *s = opaque; 969 uint64_t nb_sectors; 970 971 s->tray_open = !load; 972 bdrv_get_geometry(s->bs, &nb_sectors); 973 s->nb_sectors = nb_sectors; 974 975 /* 976 * First indicate to the guest that a CD has been removed. That's 977 * done on the next command the guest sends us. 978 * 979 * Then we set UNIT_ATTENTION, by which the guest will 980 * detect a new CD in the drive. See ide_atapi_cmd() for details. 981 */ 982 s->cdrom_changed = 1; 983 s->events.new_media = true; 984 s->events.eject_request = false; 985 ide_set_irq(s->bus); 986 } 987 988 static void ide_cd_eject_request_cb(void *opaque, bool force) 989 { 990 IDEState *s = opaque; 991 992 s->events.eject_request = true; 993 if (force) { 994 s->tray_locked = false; 995 } 996 ide_set_irq(s->bus); 997 } 998 999 static void ide_cmd_lba48_transform(IDEState *s, int lba48) 1000 { 1001 s->lba48 = lba48; 1002 1003 /* handle the 'magic' 0 nsector count conversion here. to avoid 1004 * fiddling with the rest of the read logic, we just store the 1005 * full sector count in ->nsector and ignore ->hob_nsector from now 1006 */ 1007 if (!s->lba48) { 1008 if (!s->nsector) 1009 s->nsector = 256; 1010 } else { 1011 if (!s->nsector && !s->hob_nsector) 1012 s->nsector = 65536; 1013 else { 1014 int lo = s->nsector; 1015 int hi = s->hob_nsector; 1016 1017 s->nsector = (hi << 8) | lo; 1018 } 1019 } 1020 } 1021 1022 static void ide_clear_hob(IDEBus *bus) 1023 { 1024 /* any write clears HOB high bit of device control register */ 1025 bus->ifs[0].select &= ~(1 << 7); 1026 bus->ifs[1].select &= ~(1 << 7); 1027 } 1028 1029 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1030 { 1031 IDEBus *bus = opaque; 1032 1033 #ifdef DEBUG_IDE 1034 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val); 1035 #endif 1036 1037 addr &= 7; 1038 1039 /* ignore writes to command block while busy with previous command */ 1040 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT))) 1041 return; 1042 1043 switch(addr) { 1044 case 0: 1045 break; 1046 case 1: 1047 ide_clear_hob(bus); 1048 /* NOTE: data is written to the two drives */ 1049 bus->ifs[0].hob_feature = bus->ifs[0].feature; 1050 bus->ifs[1].hob_feature = bus->ifs[1].feature; 1051 bus->ifs[0].feature = val; 1052 bus->ifs[1].feature = val; 1053 break; 1054 case 2: 1055 ide_clear_hob(bus); 1056 bus->ifs[0].hob_nsector = bus->ifs[0].nsector; 1057 bus->ifs[1].hob_nsector = bus->ifs[1].nsector; 1058 bus->ifs[0].nsector = val; 1059 bus->ifs[1].nsector = val; 1060 break; 1061 case 3: 1062 ide_clear_hob(bus); 1063 bus->ifs[0].hob_sector = bus->ifs[0].sector; 1064 bus->ifs[1].hob_sector = bus->ifs[1].sector; 1065 bus->ifs[0].sector = val; 1066 bus->ifs[1].sector = val; 1067 break; 1068 case 4: 1069 ide_clear_hob(bus); 1070 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl; 1071 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl; 1072 bus->ifs[0].lcyl = val; 1073 bus->ifs[1].lcyl = val; 1074 break; 1075 case 5: 1076 ide_clear_hob(bus); 1077 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl; 1078 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl; 1079 bus->ifs[0].hcyl = val; 1080 bus->ifs[1].hcyl = val; 1081 break; 1082 case 6: 1083 /* FIXME: HOB readback uses bit 7 */ 1084 bus->ifs[0].select = (val & ~0x10) | 0xa0; 1085 bus->ifs[1].select = (val | 0x10) | 0xa0; 1086 /* select drive */ 1087 bus->unit = (val >> 4) & 1; 1088 break; 1089 default: 1090 case 7: 1091 /* command */ 1092 ide_exec_cmd(bus, val); 1093 break; 1094 } 1095 } 1096 1097 static bool cmd_nop(IDEState *s, uint8_t cmd) 1098 { 1099 return true; 1100 } 1101 1102 static bool cmd_data_set_management(IDEState *s, uint8_t cmd) 1103 { 1104 switch (s->feature) { 1105 case DSM_TRIM: 1106 if (s->bs) { 1107 ide_sector_start_dma(s, IDE_DMA_TRIM); 1108 return false; 1109 } 1110 break; 1111 } 1112 1113 ide_abort_command(s); 1114 return true; 1115 } 1116 1117 static bool cmd_identify(IDEState *s, uint8_t cmd) 1118 { 1119 if (s->bs && s->drive_kind != IDE_CD) { 1120 if (s->drive_kind != IDE_CFATA) { 1121 ide_identify(s); 1122 } else { 1123 ide_cfata_identify(s); 1124 } 1125 s->status = READY_STAT | SEEK_STAT; 1126 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); 1127 ide_set_irq(s->bus); 1128 return false; 1129 } else { 1130 if (s->drive_kind == IDE_CD) { 1131 ide_set_signature(s); 1132 } 1133 ide_abort_command(s); 1134 } 1135 1136 return true; 1137 } 1138 1139 static bool cmd_verify(IDEState *s, uint8_t cmd) 1140 { 1141 bool lba48 = (cmd == WIN_VERIFY_EXT); 1142 1143 /* do sector number check ? */ 1144 ide_cmd_lba48_transform(s, lba48); 1145 1146 return true; 1147 } 1148 1149 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd) 1150 { 1151 if (s->drive_kind == IDE_CFATA && s->nsector == 0) { 1152 /* Disable Read and Write Multiple */ 1153 s->mult_sectors = 0; 1154 } else if ((s->nsector & 0xff) != 0 && 1155 ((s->nsector & 0xff) > MAX_MULT_SECTORS || 1156 (s->nsector & (s->nsector - 1)) != 0)) { 1157 ide_abort_command(s); 1158 } else { 1159 s->mult_sectors = s->nsector & 0xff; 1160 } 1161 1162 return true; 1163 } 1164 1165 static bool cmd_read_multiple(IDEState *s, uint8_t cmd) 1166 { 1167 bool lba48 = (cmd == WIN_MULTREAD_EXT); 1168 1169 if (!s->bs || !s->mult_sectors) { 1170 ide_abort_command(s); 1171 return true; 1172 } 1173 1174 ide_cmd_lba48_transform(s, lba48); 1175 s->req_nb_sectors = s->mult_sectors; 1176 ide_sector_read(s); 1177 return false; 1178 } 1179 1180 static bool cmd_write_multiple(IDEState *s, uint8_t cmd) 1181 { 1182 bool lba48 = (cmd == WIN_MULTWRITE_EXT); 1183 int n; 1184 1185 if (!s->bs || !s->mult_sectors) { 1186 ide_abort_command(s); 1187 return true; 1188 } 1189 1190 ide_cmd_lba48_transform(s, lba48); 1191 1192 s->req_nb_sectors = s->mult_sectors; 1193 n = MIN(s->nsector, s->req_nb_sectors); 1194 1195 s->status = SEEK_STAT | READY_STAT; 1196 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write); 1197 1198 s->media_changed = 1; 1199 1200 return false; 1201 } 1202 1203 static bool cmd_read_pio(IDEState *s, uint8_t cmd) 1204 { 1205 bool lba48 = (cmd == WIN_READ_EXT); 1206 1207 if (s->drive_kind == IDE_CD) { 1208 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */ 1209 ide_abort_command(s); 1210 return true; 1211 } 1212 1213 if (!s->bs) { 1214 ide_abort_command(s); 1215 return true; 1216 } 1217 1218 ide_cmd_lba48_transform(s, lba48); 1219 s->req_nb_sectors = 1; 1220 ide_sector_read(s); 1221 1222 return false; 1223 } 1224 1225 static bool cmd_write_pio(IDEState *s, uint8_t cmd) 1226 { 1227 bool lba48 = (cmd == WIN_WRITE_EXT); 1228 1229 if (!s->bs) { 1230 ide_abort_command(s); 1231 return true; 1232 } 1233 1234 ide_cmd_lba48_transform(s, lba48); 1235 1236 s->req_nb_sectors = 1; 1237 s->status = SEEK_STAT | READY_STAT; 1238 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write); 1239 1240 s->media_changed = 1; 1241 1242 return false; 1243 } 1244 1245 static bool cmd_read_dma(IDEState *s, uint8_t cmd) 1246 { 1247 bool lba48 = (cmd == WIN_READDMA_EXT); 1248 1249 if (!s->bs) { 1250 ide_abort_command(s); 1251 return true; 1252 } 1253 1254 ide_cmd_lba48_transform(s, lba48); 1255 ide_sector_start_dma(s, IDE_DMA_READ); 1256 1257 return false; 1258 } 1259 1260 static bool cmd_write_dma(IDEState *s, uint8_t cmd) 1261 { 1262 bool lba48 = (cmd == WIN_WRITEDMA_EXT); 1263 1264 if (!s->bs) { 1265 ide_abort_command(s); 1266 return true; 1267 } 1268 1269 ide_cmd_lba48_transform(s, lba48); 1270 ide_sector_start_dma(s, IDE_DMA_WRITE); 1271 1272 s->media_changed = 1; 1273 1274 return false; 1275 } 1276 1277 static bool cmd_flush_cache(IDEState *s, uint8_t cmd) 1278 { 1279 ide_flush_cache(s); 1280 return false; 1281 } 1282 1283 static bool cmd_seek(IDEState *s, uint8_t cmd) 1284 { 1285 /* XXX: Check that seek is within bounds */ 1286 return true; 1287 } 1288 1289 static bool cmd_read_native_max(IDEState *s, uint8_t cmd) 1290 { 1291 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT); 1292 1293 /* Refuse if no sectors are addressable (e.g. medium not inserted) */ 1294 if (s->nb_sectors == 0) { 1295 ide_abort_command(s); 1296 return true; 1297 } 1298 1299 ide_cmd_lba48_transform(s, lba48); 1300 ide_set_sector(s, s->nb_sectors - 1); 1301 1302 return true; 1303 } 1304 1305 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd) 1306 { 1307 s->nsector = 0xff; /* device active or idle */ 1308 return true; 1309 } 1310 1311 static bool cmd_set_features(IDEState *s, uint8_t cmd) 1312 { 1313 uint16_t *identify_data; 1314 1315 if (!s->bs) { 1316 ide_abort_command(s); 1317 return true; 1318 } 1319 1320 /* XXX: valid for CDROM ? */ 1321 switch (s->feature) { 1322 case 0x02: /* write cache enable */ 1323 bdrv_set_enable_write_cache(s->bs, true); 1324 identify_data = (uint16_t *)s->identify_data; 1325 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1); 1326 return true; 1327 case 0x82: /* write cache disable */ 1328 bdrv_set_enable_write_cache(s->bs, false); 1329 identify_data = (uint16_t *)s->identify_data; 1330 put_le16(identify_data + 85, (1 << 14) | 1); 1331 ide_flush_cache(s); 1332 return false; 1333 case 0xcc: /* reverting to power-on defaults enable */ 1334 case 0x66: /* reverting to power-on defaults disable */ 1335 case 0xaa: /* read look-ahead enable */ 1336 case 0x55: /* read look-ahead disable */ 1337 case 0x05: /* set advanced power management mode */ 1338 case 0x85: /* disable advanced power management mode */ 1339 case 0x69: /* NOP */ 1340 case 0x67: /* NOP */ 1341 case 0x96: /* NOP */ 1342 case 0x9a: /* NOP */ 1343 case 0x42: /* enable Automatic Acoustic Mode */ 1344 case 0xc2: /* disable Automatic Acoustic Mode */ 1345 return true; 1346 case 0x03: /* set transfer mode */ 1347 { 1348 uint8_t val = s->nsector & 0x07; 1349 identify_data = (uint16_t *)s->identify_data; 1350 1351 switch (s->nsector >> 3) { 1352 case 0x00: /* pio default */ 1353 case 0x01: /* pio mode */ 1354 put_le16(identify_data + 62, 0x07); 1355 put_le16(identify_data + 63, 0x07); 1356 put_le16(identify_data + 88, 0x3f); 1357 break; 1358 case 0x02: /* sigle word dma mode*/ 1359 put_le16(identify_data + 62, 0x07 | (1 << (val + 8))); 1360 put_le16(identify_data + 63, 0x07); 1361 put_le16(identify_data + 88, 0x3f); 1362 break; 1363 case 0x04: /* mdma mode */ 1364 put_le16(identify_data + 62, 0x07); 1365 put_le16(identify_data + 63, 0x07 | (1 << (val + 8))); 1366 put_le16(identify_data + 88, 0x3f); 1367 break; 1368 case 0x08: /* udma mode */ 1369 put_le16(identify_data + 62, 0x07); 1370 put_le16(identify_data + 63, 0x07); 1371 put_le16(identify_data + 88, 0x3f | (1 << (val + 8))); 1372 break; 1373 default: 1374 goto abort_cmd; 1375 } 1376 return true; 1377 } 1378 } 1379 1380 abort_cmd: 1381 ide_abort_command(s); 1382 return true; 1383 } 1384 1385 1386 /*** ATAPI commands ***/ 1387 1388 static bool cmd_identify_packet(IDEState *s, uint8_t cmd) 1389 { 1390 ide_atapi_identify(s); 1391 s->status = READY_STAT | SEEK_STAT; 1392 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); 1393 ide_set_irq(s->bus); 1394 return false; 1395 } 1396 1397 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd) 1398 { 1399 ide_set_signature(s); 1400 1401 if (s->drive_kind == IDE_CD) { 1402 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet 1403 * devices to return a clear status register 1404 * with READY_STAT *not* set. */ 1405 s->error = 0x01; 1406 } else { 1407 s->status = READY_STAT | SEEK_STAT; 1408 /* The bits of the error register are not as usual for this command! 1409 * They are part of the regular output (this is why ERR_STAT isn't set) 1410 * Device 0 passed, Device 1 passed or not present. */ 1411 s->error = 0x01; 1412 ide_set_irq(s->bus); 1413 } 1414 1415 return false; 1416 } 1417 1418 static bool cmd_device_reset(IDEState *s, uint8_t cmd) 1419 { 1420 ide_set_signature(s); 1421 s->status = 0x00; /* NOTE: READY is _not_ set */ 1422 s->error = 0x01; 1423 1424 return false; 1425 } 1426 1427 static bool cmd_packet(IDEState *s, uint8_t cmd) 1428 { 1429 /* overlapping commands not supported */ 1430 if (s->feature & 0x02) { 1431 ide_abort_command(s); 1432 return true; 1433 } 1434 1435 s->status = READY_STAT | SEEK_STAT; 1436 s->atapi_dma = s->feature & 1; 1437 s->nsector = 1; 1438 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, 1439 ide_atapi_cmd); 1440 return false; 1441 } 1442 1443 1444 /*** CF-ATA commands ***/ 1445 1446 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd) 1447 { 1448 s->error = 0x09; /* miscellaneous error */ 1449 s->status = READY_STAT | SEEK_STAT; 1450 ide_set_irq(s->bus); 1451 1452 return false; 1453 } 1454 1455 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd) 1456 { 1457 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is 1458 * required for Windows 8 to work with AHCI */ 1459 1460 if (cmd == CFA_WEAR_LEVEL) { 1461 s->nsector = 0; 1462 } 1463 1464 if (cmd == CFA_ERASE_SECTORS) { 1465 s->media_changed = 1; 1466 } 1467 1468 return true; 1469 } 1470 1471 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd) 1472 { 1473 s->status = READY_STAT | SEEK_STAT; 1474 1475 memset(s->io_buffer, 0, 0x200); 1476 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */ 1477 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */ 1478 s->io_buffer[0x02] = s->select; /* Head */ 1479 s->io_buffer[0x03] = s->sector; /* Sector */ 1480 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */ 1481 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */ 1482 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */ 1483 s->io_buffer[0x13] = 0x00; /* Erase flag */ 1484 s->io_buffer[0x18] = 0x00; /* Hot count */ 1485 s->io_buffer[0x19] = 0x00; /* Hot count */ 1486 s->io_buffer[0x1a] = 0x01; /* Hot count */ 1487 1488 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1489 ide_set_irq(s->bus); 1490 1491 return false; 1492 } 1493 1494 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd) 1495 { 1496 switch (s->feature) { 1497 case 0x02: /* Inquiry Metadata Storage */ 1498 ide_cfata_metadata_inquiry(s); 1499 break; 1500 case 0x03: /* Read Metadata Storage */ 1501 ide_cfata_metadata_read(s); 1502 break; 1503 case 0x04: /* Write Metadata Storage */ 1504 ide_cfata_metadata_write(s); 1505 break; 1506 default: 1507 ide_abort_command(s); 1508 return true; 1509 } 1510 1511 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1512 s->status = 0x00; /* NOTE: READY is _not_ set */ 1513 ide_set_irq(s->bus); 1514 1515 return false; 1516 } 1517 1518 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd) 1519 { 1520 switch (s->feature) { 1521 case 0x01: /* sense temperature in device */ 1522 s->nsector = 0x50; /* +20 C */ 1523 break; 1524 default: 1525 ide_abort_command(s); 1526 return true; 1527 } 1528 1529 return true; 1530 } 1531 1532 1533 /*** SMART commands ***/ 1534 1535 static bool cmd_smart(IDEState *s, uint8_t cmd) 1536 { 1537 int n; 1538 1539 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) { 1540 goto abort_cmd; 1541 } 1542 1543 if (!s->smart_enabled && s->feature != SMART_ENABLE) { 1544 goto abort_cmd; 1545 } 1546 1547 switch (s->feature) { 1548 case SMART_DISABLE: 1549 s->smart_enabled = 0; 1550 return true; 1551 1552 case SMART_ENABLE: 1553 s->smart_enabled = 1; 1554 return true; 1555 1556 case SMART_ATTR_AUTOSAVE: 1557 switch (s->sector) { 1558 case 0x00: 1559 s->smart_autosave = 0; 1560 break; 1561 case 0xf1: 1562 s->smart_autosave = 1; 1563 break; 1564 default: 1565 goto abort_cmd; 1566 } 1567 return true; 1568 1569 case SMART_STATUS: 1570 if (!s->smart_errors) { 1571 s->hcyl = 0xc2; 1572 s->lcyl = 0x4f; 1573 } else { 1574 s->hcyl = 0x2c; 1575 s->lcyl = 0xf4; 1576 } 1577 return true; 1578 1579 case SMART_READ_THRESH: 1580 memset(s->io_buffer, 0, 0x200); 1581 s->io_buffer[0] = 0x01; /* smart struct version */ 1582 1583 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) { 1584 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0]; 1585 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11]; 1586 } 1587 1588 /* checksum */ 1589 for (n = 0; n < 511; n++) { 1590 s->io_buffer[511] += s->io_buffer[n]; 1591 } 1592 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1593 1594 s->status = READY_STAT | SEEK_STAT; 1595 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1596 ide_set_irq(s->bus); 1597 return false; 1598 1599 case SMART_READ_DATA: 1600 memset(s->io_buffer, 0, 0x200); 1601 s->io_buffer[0] = 0x01; /* smart struct version */ 1602 1603 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) { 1604 int i; 1605 for (i = 0; i < 11; i++) { 1606 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i]; 1607 } 1608 } 1609 1610 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00); 1611 if (s->smart_selftest_count == 0) { 1612 s->io_buffer[363] = 0; 1613 } else { 1614 s->io_buffer[363] = 1615 s->smart_selftest_data[3 + 1616 (s->smart_selftest_count - 1) * 1617 24]; 1618 } 1619 s->io_buffer[364] = 0x20; 1620 s->io_buffer[365] = 0x01; 1621 /* offline data collection capacity: execute + self-test*/ 1622 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1); 1623 s->io_buffer[368] = 0x03; /* smart capability (1) */ 1624 s->io_buffer[369] = 0x00; /* smart capability (2) */ 1625 s->io_buffer[370] = 0x01; /* error logging supported */ 1626 s->io_buffer[372] = 0x02; /* minutes for poll short test */ 1627 s->io_buffer[373] = 0x36; /* minutes for poll ext test */ 1628 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */ 1629 1630 for (n = 0; n < 511; n++) { 1631 s->io_buffer[511] += s->io_buffer[n]; 1632 } 1633 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1634 1635 s->status = READY_STAT | SEEK_STAT; 1636 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1637 ide_set_irq(s->bus); 1638 return false; 1639 1640 case SMART_READ_LOG: 1641 switch (s->sector) { 1642 case 0x01: /* summary smart error log */ 1643 memset(s->io_buffer, 0, 0x200); 1644 s->io_buffer[0] = 0x01; 1645 s->io_buffer[1] = 0x00; /* no error entries */ 1646 s->io_buffer[452] = s->smart_errors & 0xff; 1647 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8; 1648 1649 for (n = 0; n < 511; n++) { 1650 s->io_buffer[511] += s->io_buffer[n]; 1651 } 1652 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1653 break; 1654 case 0x06: /* smart self test log */ 1655 memset(s->io_buffer, 0, 0x200); 1656 s->io_buffer[0] = 0x01; 1657 if (s->smart_selftest_count == 0) { 1658 s->io_buffer[508] = 0; 1659 } else { 1660 s->io_buffer[508] = s->smart_selftest_count; 1661 for (n = 2; n < 506; n++) { 1662 s->io_buffer[n] = s->smart_selftest_data[n]; 1663 } 1664 } 1665 1666 for (n = 0; n < 511; n++) { 1667 s->io_buffer[511] += s->io_buffer[n]; 1668 } 1669 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1670 break; 1671 default: 1672 goto abort_cmd; 1673 } 1674 s->status = READY_STAT | SEEK_STAT; 1675 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1676 ide_set_irq(s->bus); 1677 return false; 1678 1679 case SMART_EXECUTE_OFFLINE: 1680 switch (s->sector) { 1681 case 0: /* off-line routine */ 1682 case 1: /* short self test */ 1683 case 2: /* extended self test */ 1684 s->smart_selftest_count++; 1685 if (s->smart_selftest_count > 21) { 1686 s->smart_selftest_count = 1; 1687 } 1688 n = 2 + (s->smart_selftest_count - 1) * 24; 1689 s->smart_selftest_data[n] = s->sector; 1690 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */ 1691 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */ 1692 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */ 1693 break; 1694 default: 1695 goto abort_cmd; 1696 } 1697 return true; 1698 } 1699 1700 abort_cmd: 1701 ide_abort_command(s); 1702 return true; 1703 } 1704 1705 #define HD_OK (1u << IDE_HD) 1706 #define CD_OK (1u << IDE_CD) 1707 #define CFA_OK (1u << IDE_CFATA) 1708 #define HD_CFA_OK (HD_OK | CFA_OK) 1709 #define ALL_OK (HD_OK | CD_OK | CFA_OK) 1710 1711 /* Set the Disk Seek Completed status bit during completion */ 1712 #define SET_DSC (1u << 8) 1713 1714 /* See ACS-2 T13/2015-D Table B.2 Command codes */ 1715 static const struct { 1716 /* Returns true if the completion code should be run */ 1717 bool (*handler)(IDEState *s, uint8_t cmd); 1718 int flags; 1719 } ide_cmd_table[0x100] = { 1720 /* NOP not implemented, mandatory for CD */ 1721 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK }, 1722 [WIN_DSM] = { cmd_data_set_management, ALL_OK }, 1723 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK }, 1724 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC}, 1725 [WIN_READ] = { cmd_read_pio, ALL_OK }, 1726 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK }, 1727 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK }, 1728 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK }, 1729 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC }, 1730 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK }, 1731 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK }, 1732 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK }, 1733 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK }, 1734 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK }, 1735 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK }, 1736 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK }, 1737 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK }, 1738 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1739 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1740 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1741 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC }, 1742 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK }, 1743 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK }, 1744 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC }, 1745 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK }, 1746 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK }, 1747 [WIN_STANDBY2] = { cmd_nop, ALL_OK }, 1748 [WIN_SETIDLE2] = { cmd_nop, ALL_OK }, 1749 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC }, 1750 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK }, 1751 [WIN_PACKETCMD] = { cmd_packet, CD_OK }, 1752 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK }, 1753 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC }, 1754 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK }, 1755 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC }, 1756 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK }, 1757 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK }, 1758 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC }, 1759 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK }, 1760 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK }, 1761 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK }, 1762 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK }, 1763 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK }, 1764 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK }, 1765 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK }, 1766 [WIN_STANDBY] = { cmd_nop, ALL_OK }, 1767 [WIN_SETIDLE1] = { cmd_nop, ALL_OK }, 1768 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC }, 1769 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK }, 1770 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK }, 1771 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK }, 1772 [WIN_IDENTIFY] = { cmd_identify, ALL_OK }, 1773 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC }, 1774 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC }, 1775 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC }, 1776 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC }, 1777 }; 1778 1779 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd) 1780 { 1781 return cmd < ARRAY_SIZE(ide_cmd_table) 1782 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind)); 1783 } 1784 1785 void ide_exec_cmd(IDEBus *bus, uint32_t val) 1786 { 1787 IDEState *s; 1788 bool complete; 1789 1790 #if defined(DEBUG_IDE) 1791 printf("ide: CMD=%02x\n", val); 1792 #endif 1793 s = idebus_active_if(bus); 1794 /* ignore commands to non existent slave */ 1795 if (s != bus->ifs && !s->bs) 1796 return; 1797 1798 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */ 1799 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET) 1800 return; 1801 1802 if (!ide_cmd_permitted(s, val)) { 1803 ide_abort_command(s); 1804 ide_set_irq(s->bus); 1805 return; 1806 } 1807 1808 s->status = READY_STAT | BUSY_STAT; 1809 s->error = 0; 1810 1811 complete = ide_cmd_table[val].handler(s, val); 1812 if (complete) { 1813 s->status &= ~BUSY_STAT; 1814 assert(!!s->error == !!(s->status & ERR_STAT)); 1815 1816 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) { 1817 s->status |= SEEK_STAT; 1818 } 1819 1820 ide_cmd_done(s); 1821 ide_set_irq(s->bus); 1822 } 1823 } 1824 1825 uint32_t ide_ioport_read(void *opaque, uint32_t addr1) 1826 { 1827 IDEBus *bus = opaque; 1828 IDEState *s = idebus_active_if(bus); 1829 uint32_t addr; 1830 int ret, hob; 1831 1832 addr = addr1 & 7; 1833 /* FIXME: HOB readback uses bit 7, but it's always set right now */ 1834 //hob = s->select & (1 << 7); 1835 hob = 0; 1836 switch(addr) { 1837 case 0: 1838 ret = 0xff; 1839 break; 1840 case 1: 1841 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || 1842 (s != bus->ifs && !s->bs)) 1843 ret = 0; 1844 else if (!hob) 1845 ret = s->error; 1846 else 1847 ret = s->hob_feature; 1848 break; 1849 case 2: 1850 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1851 ret = 0; 1852 else if (!hob) 1853 ret = s->nsector & 0xff; 1854 else 1855 ret = s->hob_nsector; 1856 break; 1857 case 3: 1858 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1859 ret = 0; 1860 else if (!hob) 1861 ret = s->sector; 1862 else 1863 ret = s->hob_sector; 1864 break; 1865 case 4: 1866 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1867 ret = 0; 1868 else if (!hob) 1869 ret = s->lcyl; 1870 else 1871 ret = s->hob_lcyl; 1872 break; 1873 case 5: 1874 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1875 ret = 0; 1876 else if (!hob) 1877 ret = s->hcyl; 1878 else 1879 ret = s->hob_hcyl; 1880 break; 1881 case 6: 1882 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1883 ret = 0; 1884 else 1885 ret = s->select; 1886 break; 1887 default: 1888 case 7: 1889 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || 1890 (s != bus->ifs && !s->bs)) 1891 ret = 0; 1892 else 1893 ret = s->status; 1894 qemu_irq_lower(bus->irq); 1895 break; 1896 } 1897 #ifdef DEBUG_IDE 1898 printf("ide: read addr=0x%x val=%02x\n", addr1, ret); 1899 #endif 1900 return ret; 1901 } 1902 1903 uint32_t ide_status_read(void *opaque, uint32_t addr) 1904 { 1905 IDEBus *bus = opaque; 1906 IDEState *s = idebus_active_if(bus); 1907 int ret; 1908 1909 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || 1910 (s != bus->ifs && !s->bs)) 1911 ret = 0; 1912 else 1913 ret = s->status; 1914 #ifdef DEBUG_IDE 1915 printf("ide: read status addr=0x%x val=%02x\n", addr, ret); 1916 #endif 1917 return ret; 1918 } 1919 1920 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) 1921 { 1922 IDEBus *bus = opaque; 1923 IDEState *s; 1924 int i; 1925 1926 #ifdef DEBUG_IDE 1927 printf("ide: write control addr=0x%x val=%02x\n", addr, val); 1928 #endif 1929 /* common for both drives */ 1930 if (!(bus->cmd & IDE_CMD_RESET) && 1931 (val & IDE_CMD_RESET)) { 1932 /* reset low to high */ 1933 for(i = 0;i < 2; i++) { 1934 s = &bus->ifs[i]; 1935 s->status = BUSY_STAT | SEEK_STAT; 1936 s->error = 0x01; 1937 } 1938 } else if ((bus->cmd & IDE_CMD_RESET) && 1939 !(val & IDE_CMD_RESET)) { 1940 /* high to low */ 1941 for(i = 0;i < 2; i++) { 1942 s = &bus->ifs[i]; 1943 if (s->drive_kind == IDE_CD) 1944 s->status = 0x00; /* NOTE: READY is _not_ set */ 1945 else 1946 s->status = READY_STAT | SEEK_STAT; 1947 ide_set_signature(s); 1948 } 1949 } 1950 1951 bus->cmd = val; 1952 } 1953 1954 /* 1955 * Returns true if the running PIO transfer is a PIO out (i.e. data is 1956 * transferred from the device to the guest), false if it's a PIO in 1957 */ 1958 static bool ide_is_pio_out(IDEState *s) 1959 { 1960 if (s->end_transfer_func == ide_sector_write || 1961 s->end_transfer_func == ide_atapi_cmd) { 1962 return false; 1963 } else if (s->end_transfer_func == ide_sector_read || 1964 s->end_transfer_func == ide_transfer_stop || 1965 s->end_transfer_func == ide_atapi_cmd_reply_end || 1966 s->end_transfer_func == ide_dummy_transfer_stop) { 1967 return true; 1968 } 1969 1970 abort(); 1971 } 1972 1973 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val) 1974 { 1975 IDEBus *bus = opaque; 1976 IDEState *s = idebus_active_if(bus); 1977 uint8_t *p; 1978 1979 /* PIO data access allowed only when DRQ bit is set. The result of a write 1980 * during PIO out is indeterminate, just ignore it. */ 1981 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { 1982 return; 1983 } 1984 1985 p = s->data_ptr; 1986 *(uint16_t *)p = le16_to_cpu(val); 1987 p += 2; 1988 s->data_ptr = p; 1989 if (p >= s->data_end) 1990 s->end_transfer_func(s); 1991 } 1992 1993 uint32_t ide_data_readw(void *opaque, uint32_t addr) 1994 { 1995 IDEBus *bus = opaque; 1996 IDEState *s = idebus_active_if(bus); 1997 uint8_t *p; 1998 int ret; 1999 2000 /* PIO data access allowed only when DRQ bit is set. The result of a read 2001 * during PIO in is indeterminate, return 0 and don't move forward. */ 2002 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { 2003 return 0; 2004 } 2005 2006 p = s->data_ptr; 2007 ret = cpu_to_le16(*(uint16_t *)p); 2008 p += 2; 2009 s->data_ptr = p; 2010 if (p >= s->data_end) 2011 s->end_transfer_func(s); 2012 return ret; 2013 } 2014 2015 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val) 2016 { 2017 IDEBus *bus = opaque; 2018 IDEState *s = idebus_active_if(bus); 2019 uint8_t *p; 2020 2021 /* PIO data access allowed only when DRQ bit is set. The result of a write 2022 * during PIO out is indeterminate, just ignore it. */ 2023 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { 2024 return; 2025 } 2026 2027 p = s->data_ptr; 2028 *(uint32_t *)p = le32_to_cpu(val); 2029 p += 4; 2030 s->data_ptr = p; 2031 if (p >= s->data_end) 2032 s->end_transfer_func(s); 2033 } 2034 2035 uint32_t ide_data_readl(void *opaque, uint32_t addr) 2036 { 2037 IDEBus *bus = opaque; 2038 IDEState *s = idebus_active_if(bus); 2039 uint8_t *p; 2040 int ret; 2041 2042 /* PIO data access allowed only when DRQ bit is set. The result of a read 2043 * during PIO in is indeterminate, return 0 and don't move forward. */ 2044 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { 2045 return 0; 2046 } 2047 2048 p = s->data_ptr; 2049 ret = cpu_to_le32(*(uint32_t *)p); 2050 p += 4; 2051 s->data_ptr = p; 2052 if (p >= s->data_end) 2053 s->end_transfer_func(s); 2054 return ret; 2055 } 2056 2057 static void ide_dummy_transfer_stop(IDEState *s) 2058 { 2059 s->data_ptr = s->io_buffer; 2060 s->data_end = s->io_buffer; 2061 s->io_buffer[0] = 0xff; 2062 s->io_buffer[1] = 0xff; 2063 s->io_buffer[2] = 0xff; 2064 s->io_buffer[3] = 0xff; 2065 } 2066 2067 static void ide_reset(IDEState *s) 2068 { 2069 #ifdef DEBUG_IDE 2070 printf("ide: reset\n"); 2071 #endif 2072 2073 if (s->pio_aiocb) { 2074 bdrv_aio_cancel(s->pio_aiocb); 2075 s->pio_aiocb = NULL; 2076 } 2077 2078 if (s->drive_kind == IDE_CFATA) 2079 s->mult_sectors = 0; 2080 else 2081 s->mult_sectors = MAX_MULT_SECTORS; 2082 /* ide regs */ 2083 s->feature = 0; 2084 s->error = 0; 2085 s->nsector = 0; 2086 s->sector = 0; 2087 s->lcyl = 0; 2088 s->hcyl = 0; 2089 2090 /* lba48 */ 2091 s->hob_feature = 0; 2092 s->hob_sector = 0; 2093 s->hob_nsector = 0; 2094 s->hob_lcyl = 0; 2095 s->hob_hcyl = 0; 2096 2097 s->select = 0xa0; 2098 s->status = READY_STAT | SEEK_STAT; 2099 2100 s->lba48 = 0; 2101 2102 /* ATAPI specific */ 2103 s->sense_key = 0; 2104 s->asc = 0; 2105 s->cdrom_changed = 0; 2106 s->packet_transfer_size = 0; 2107 s->elementary_transfer_size = 0; 2108 s->io_buffer_index = 0; 2109 s->cd_sector_size = 0; 2110 s->atapi_dma = 0; 2111 s->tray_locked = 0; 2112 s->tray_open = 0; 2113 /* ATA DMA state */ 2114 s->io_buffer_size = 0; 2115 s->req_nb_sectors = 0; 2116 2117 ide_set_signature(s); 2118 /* init the transfer handler so that 0xffff is returned on data 2119 accesses */ 2120 s->end_transfer_func = ide_dummy_transfer_stop; 2121 ide_dummy_transfer_stop(s); 2122 s->media_changed = 0; 2123 } 2124 2125 void ide_bus_reset(IDEBus *bus) 2126 { 2127 bus->unit = 0; 2128 bus->cmd = 0; 2129 ide_reset(&bus->ifs[0]); 2130 ide_reset(&bus->ifs[1]); 2131 ide_clear_hob(bus); 2132 2133 /* pending async DMA */ 2134 if (bus->dma->aiocb) { 2135 #ifdef DEBUG_AIO 2136 printf("aio_cancel\n"); 2137 #endif 2138 bdrv_aio_cancel(bus->dma->aiocb); 2139 bus->dma->aiocb = NULL; 2140 } 2141 2142 /* reset dma provider too */ 2143 if (bus->dma->ops->reset) { 2144 bus->dma->ops->reset(bus->dma); 2145 } 2146 } 2147 2148 static bool ide_cd_is_tray_open(void *opaque) 2149 { 2150 return ((IDEState *)opaque)->tray_open; 2151 } 2152 2153 static bool ide_cd_is_medium_locked(void *opaque) 2154 { 2155 return ((IDEState *)opaque)->tray_locked; 2156 } 2157 2158 static void ide_resize_cb(void *opaque) 2159 { 2160 IDEState *s = opaque; 2161 uint64_t nb_sectors; 2162 2163 if (!s->identify_set) { 2164 return; 2165 } 2166 2167 bdrv_get_geometry(s->bs, &nb_sectors); 2168 s->nb_sectors = nb_sectors; 2169 2170 /* Update the identify data buffer. */ 2171 if (s->drive_kind == IDE_CFATA) { 2172 ide_cfata_identify_size(s); 2173 } else { 2174 /* IDE_CD uses a different set of callbacks entirely. */ 2175 assert(s->drive_kind != IDE_CD); 2176 ide_identify_size(s); 2177 } 2178 } 2179 2180 static const BlockDevOps ide_cd_block_ops = { 2181 .change_media_cb = ide_cd_change_cb, 2182 .eject_request_cb = ide_cd_eject_request_cb, 2183 .is_tray_open = ide_cd_is_tray_open, 2184 .is_medium_locked = ide_cd_is_medium_locked, 2185 }; 2186 2187 static const BlockDevOps ide_hd_block_ops = { 2188 .resize_cb = ide_resize_cb, 2189 }; 2190 2191 int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind, 2192 const char *version, const char *serial, const char *model, 2193 uint64_t wwn, 2194 uint32_t cylinders, uint32_t heads, uint32_t secs, 2195 int chs_trans) 2196 { 2197 uint64_t nb_sectors; 2198 2199 s->bs = bs; 2200 s->drive_kind = kind; 2201 2202 bdrv_get_geometry(bs, &nb_sectors); 2203 s->cylinders = cylinders; 2204 s->heads = heads; 2205 s->sectors = secs; 2206 s->chs_trans = chs_trans; 2207 s->nb_sectors = nb_sectors; 2208 s->wwn = wwn; 2209 /* The SMART values should be preserved across power cycles 2210 but they aren't. */ 2211 s->smart_enabled = 1; 2212 s->smart_autosave = 1; 2213 s->smart_errors = 0; 2214 s->smart_selftest_count = 0; 2215 if (kind == IDE_CD) { 2216 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s); 2217 bdrv_set_guest_block_size(bs, 2048); 2218 } else { 2219 if (!bdrv_is_inserted(s->bs)) { 2220 error_report("Device needs media, but drive is empty"); 2221 return -1; 2222 } 2223 if (bdrv_is_read_only(bs)) { 2224 error_report("Can't use a read-only drive"); 2225 return -1; 2226 } 2227 bdrv_set_dev_ops(bs, &ide_hd_block_ops, s); 2228 } 2229 if (serial) { 2230 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial); 2231 } else { 2232 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str), 2233 "QM%05d", s->drive_serial); 2234 } 2235 if (model) { 2236 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model); 2237 } else { 2238 switch (kind) { 2239 case IDE_CD: 2240 strcpy(s->drive_model_str, "QEMU DVD-ROM"); 2241 break; 2242 case IDE_CFATA: 2243 strcpy(s->drive_model_str, "QEMU MICRODRIVE"); 2244 break; 2245 default: 2246 strcpy(s->drive_model_str, "QEMU HARDDISK"); 2247 break; 2248 } 2249 } 2250 2251 if (version) { 2252 pstrcpy(s->version, sizeof(s->version), version); 2253 } else { 2254 pstrcpy(s->version, sizeof(s->version), qemu_get_version()); 2255 } 2256 2257 ide_reset(s); 2258 bdrv_iostatus_enable(bs); 2259 return 0; 2260 } 2261 2262 static void ide_init1(IDEBus *bus, int unit) 2263 { 2264 static int drive_serial = 1; 2265 IDEState *s = &bus->ifs[unit]; 2266 2267 s->bus = bus; 2268 s->unit = unit; 2269 s->drive_serial = drive_serial++; 2270 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */ 2271 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; 2272 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len); 2273 memset(s->io_buffer, 0, s->io_buffer_total_len); 2274 2275 s->smart_selftest_data = qemu_blockalign(s->bs, 512); 2276 memset(s->smart_selftest_data, 0, 512); 2277 2278 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2279 ide_sector_write_timer_cb, s); 2280 } 2281 2282 static int ide_nop_int(IDEDMA *dma, int x) 2283 { 2284 return 0; 2285 } 2286 2287 static void ide_nop_restart(void *opaque, int x, RunState y) 2288 { 2289 } 2290 2291 static const IDEDMAOps ide_dma_nop_ops = { 2292 .prepare_buf = ide_nop_int, 2293 .rw_buf = ide_nop_int, 2294 .set_unit = ide_nop_int, 2295 .restart_cb = ide_nop_restart, 2296 }; 2297 2298 static IDEDMA ide_dma_nop = { 2299 .ops = &ide_dma_nop_ops, 2300 .aiocb = NULL, 2301 }; 2302 2303 void ide_init2(IDEBus *bus, qemu_irq irq) 2304 { 2305 int i; 2306 2307 for(i = 0; i < 2; i++) { 2308 ide_init1(bus, i); 2309 ide_reset(&bus->ifs[i]); 2310 } 2311 bus->irq = irq; 2312 bus->dma = &ide_dma_nop; 2313 } 2314 2315 static const MemoryRegionPortio ide_portio_list[] = { 2316 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write }, 2317 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew }, 2318 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel }, 2319 PORTIO_END_OF_LIST(), 2320 }; 2321 2322 static const MemoryRegionPortio ide_portio2_list[] = { 2323 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write }, 2324 PORTIO_END_OF_LIST(), 2325 }; 2326 2327 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2) 2328 { 2329 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA 2330 bridge has been setup properly to always register with ISA. */ 2331 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide"); 2332 2333 if (iobase2) { 2334 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide"); 2335 } 2336 } 2337 2338 static bool is_identify_set(void *opaque, int version_id) 2339 { 2340 IDEState *s = opaque; 2341 2342 return s->identify_set != 0; 2343 } 2344 2345 static EndTransferFunc* transfer_end_table[] = { 2346 ide_sector_read, 2347 ide_sector_write, 2348 ide_transfer_stop, 2349 ide_atapi_cmd_reply_end, 2350 ide_atapi_cmd, 2351 ide_dummy_transfer_stop, 2352 }; 2353 2354 static int transfer_end_table_idx(EndTransferFunc *fn) 2355 { 2356 int i; 2357 2358 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++) 2359 if (transfer_end_table[i] == fn) 2360 return i; 2361 2362 return -1; 2363 } 2364 2365 static int ide_drive_post_load(void *opaque, int version_id) 2366 { 2367 IDEState *s = opaque; 2368 2369 if (s->identify_set) { 2370 bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5))); 2371 } 2372 return 0; 2373 } 2374 2375 static int ide_drive_pio_post_load(void *opaque, int version_id) 2376 { 2377 IDEState *s = opaque; 2378 2379 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) { 2380 return -EINVAL; 2381 } 2382 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx]; 2383 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset; 2384 s->data_end = s->data_ptr + s->cur_io_buffer_len; 2385 2386 return 0; 2387 } 2388 2389 static void ide_drive_pio_pre_save(void *opaque) 2390 { 2391 IDEState *s = opaque; 2392 int idx; 2393 2394 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer; 2395 s->cur_io_buffer_len = s->data_end - s->data_ptr; 2396 2397 idx = transfer_end_table_idx(s->end_transfer_func); 2398 if (idx == -1) { 2399 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n", 2400 __func__); 2401 s->end_transfer_fn_idx = 2; 2402 } else { 2403 s->end_transfer_fn_idx = idx; 2404 } 2405 } 2406 2407 static bool ide_drive_pio_state_needed(void *opaque) 2408 { 2409 IDEState *s = opaque; 2410 2411 return ((s->status & DRQ_STAT) != 0) 2412 || (s->bus->error_status & IDE_RETRY_PIO); 2413 } 2414 2415 static bool ide_tray_state_needed(void *opaque) 2416 { 2417 IDEState *s = opaque; 2418 2419 return s->tray_open || s->tray_locked; 2420 } 2421 2422 static bool ide_atapi_gesn_needed(void *opaque) 2423 { 2424 IDEState *s = opaque; 2425 2426 return s->events.new_media || s->events.eject_request; 2427 } 2428 2429 static bool ide_error_needed(void *opaque) 2430 { 2431 IDEBus *bus = opaque; 2432 2433 return (bus->error_status != 0); 2434 } 2435 2436 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */ 2437 static const VMStateDescription vmstate_ide_atapi_gesn_state = { 2438 .name ="ide_drive/atapi/gesn_state", 2439 .version_id = 1, 2440 .minimum_version_id = 1, 2441 .fields = (VMStateField[]) { 2442 VMSTATE_BOOL(events.new_media, IDEState), 2443 VMSTATE_BOOL(events.eject_request, IDEState), 2444 VMSTATE_END_OF_LIST() 2445 } 2446 }; 2447 2448 static const VMStateDescription vmstate_ide_tray_state = { 2449 .name = "ide_drive/tray_state", 2450 .version_id = 1, 2451 .minimum_version_id = 1, 2452 .fields = (VMStateField[]) { 2453 VMSTATE_BOOL(tray_open, IDEState), 2454 VMSTATE_BOOL(tray_locked, IDEState), 2455 VMSTATE_END_OF_LIST() 2456 } 2457 }; 2458 2459 static const VMStateDescription vmstate_ide_drive_pio_state = { 2460 .name = "ide_drive/pio_state", 2461 .version_id = 1, 2462 .minimum_version_id = 1, 2463 .pre_save = ide_drive_pio_pre_save, 2464 .post_load = ide_drive_pio_post_load, 2465 .fields = (VMStateField[]) { 2466 VMSTATE_INT32(req_nb_sectors, IDEState), 2467 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1, 2468 vmstate_info_uint8, uint8_t), 2469 VMSTATE_INT32(cur_io_buffer_offset, IDEState), 2470 VMSTATE_INT32(cur_io_buffer_len, IDEState), 2471 VMSTATE_UINT8(end_transfer_fn_idx, IDEState), 2472 VMSTATE_INT32(elementary_transfer_size, IDEState), 2473 VMSTATE_INT32(packet_transfer_size, IDEState), 2474 VMSTATE_END_OF_LIST() 2475 } 2476 }; 2477 2478 const VMStateDescription vmstate_ide_drive = { 2479 .name = "ide_drive", 2480 .version_id = 3, 2481 .minimum_version_id = 0, 2482 .post_load = ide_drive_post_load, 2483 .fields = (VMStateField[]) { 2484 VMSTATE_INT32(mult_sectors, IDEState), 2485 VMSTATE_INT32(identify_set, IDEState), 2486 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set), 2487 VMSTATE_UINT8(feature, IDEState), 2488 VMSTATE_UINT8(error, IDEState), 2489 VMSTATE_UINT32(nsector, IDEState), 2490 VMSTATE_UINT8(sector, IDEState), 2491 VMSTATE_UINT8(lcyl, IDEState), 2492 VMSTATE_UINT8(hcyl, IDEState), 2493 VMSTATE_UINT8(hob_feature, IDEState), 2494 VMSTATE_UINT8(hob_sector, IDEState), 2495 VMSTATE_UINT8(hob_nsector, IDEState), 2496 VMSTATE_UINT8(hob_lcyl, IDEState), 2497 VMSTATE_UINT8(hob_hcyl, IDEState), 2498 VMSTATE_UINT8(select, IDEState), 2499 VMSTATE_UINT8(status, IDEState), 2500 VMSTATE_UINT8(lba48, IDEState), 2501 VMSTATE_UINT8(sense_key, IDEState), 2502 VMSTATE_UINT8(asc, IDEState), 2503 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3), 2504 VMSTATE_END_OF_LIST() 2505 }, 2506 .subsections = (VMStateSubsection []) { 2507 { 2508 .vmsd = &vmstate_ide_drive_pio_state, 2509 .needed = ide_drive_pio_state_needed, 2510 }, { 2511 .vmsd = &vmstate_ide_tray_state, 2512 .needed = ide_tray_state_needed, 2513 }, { 2514 .vmsd = &vmstate_ide_atapi_gesn_state, 2515 .needed = ide_atapi_gesn_needed, 2516 }, { 2517 /* empty */ 2518 } 2519 } 2520 }; 2521 2522 static const VMStateDescription vmstate_ide_error_status = { 2523 .name ="ide_bus/error", 2524 .version_id = 1, 2525 .minimum_version_id = 1, 2526 .fields = (VMStateField[]) { 2527 VMSTATE_INT32(error_status, IDEBus), 2528 VMSTATE_END_OF_LIST() 2529 } 2530 }; 2531 2532 const VMStateDescription vmstate_ide_bus = { 2533 .name = "ide_bus", 2534 .version_id = 1, 2535 .minimum_version_id = 1, 2536 .fields = (VMStateField[]) { 2537 VMSTATE_UINT8(cmd, IDEBus), 2538 VMSTATE_UINT8(unit, IDEBus), 2539 VMSTATE_END_OF_LIST() 2540 }, 2541 .subsections = (VMStateSubsection []) { 2542 { 2543 .vmsd = &vmstate_ide_error_status, 2544 .needed = ide_error_needed, 2545 }, { 2546 /* empty */ 2547 } 2548 } 2549 }; 2550 2551 void ide_drive_get(DriveInfo **hd, int max_bus) 2552 { 2553 int i; 2554 2555 if (drive_get_max_bus(IF_IDE) >= max_bus) { 2556 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus); 2557 exit(1); 2558 } 2559 2560 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) { 2561 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); 2562 } 2563 } 2564