1 /* 2 * QEMU IDE disk and CD/DVD-ROM Emulator 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include <hw/hw.h> 26 #include <hw/pc.h> 27 #include <hw/pci.h> 28 #include "qemu-error.h" 29 #include "qemu-timer.h" 30 #include "sysemu.h" 31 #include "dma.h" 32 #include "blockdev.h" 33 #include "block_int.h" 34 35 #include <hw/ide/internal.h> 36 37 /* These values were based on a Seagate ST3500418AS but have been modified 38 to make more sense in QEMU */ 39 static const int smart_attributes[][12] = { 40 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */ 41 /* raw read error rate*/ 42 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06}, 43 /* spin up */ 44 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 45 /* start stop count */ 46 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14}, 47 /* remapped sectors */ 48 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24}, 49 /* power on hours */ 50 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 51 /* power cycle count */ 52 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 53 /* airflow-temperature-celsius */ 54 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32}, 55 /* end of list */ 56 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} 57 }; 58 59 static int ide_handle_rw_error(IDEState *s, int error, int op); 60 static void ide_dummy_transfer_stop(IDEState *s); 61 62 static void padstr(char *str, const char *src, int len) 63 { 64 int i, v; 65 for(i = 0; i < len; i++) { 66 if (*src) 67 v = *src++; 68 else 69 v = ' '; 70 str[i^1] = v; 71 } 72 } 73 74 static void put_le16(uint16_t *p, unsigned int v) 75 { 76 *p = cpu_to_le16(v); 77 } 78 79 static void ide_identify(IDEState *s) 80 { 81 uint16_t *p; 82 unsigned int oldsize; 83 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master; 84 85 if (s->identify_set) { 86 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data)); 87 return; 88 } 89 90 memset(s->io_buffer, 0, 512); 91 p = (uint16_t *)s->io_buffer; 92 put_le16(p + 0, 0x0040); 93 put_le16(p + 1, s->cylinders); 94 put_le16(p + 3, s->heads); 95 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */ 96 put_le16(p + 5, 512); /* XXX: retired, remove ? */ 97 put_le16(p + 6, s->sectors); 98 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 99 put_le16(p + 20, 3); /* XXX: retired, remove ? */ 100 put_le16(p + 21, 512); /* cache size in sectors */ 101 put_le16(p + 22, 4); /* ecc bytes */ 102 padstr((char *)(p + 23), s->version, 8); /* firmware version */ 103 padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */ 104 #if MAX_MULT_SECTORS > 1 105 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); 106 #endif 107 put_le16(p + 48, 1); /* dword I/O */ 108 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */ 109 put_le16(p + 51, 0x200); /* PIO transfer cycle */ 110 put_le16(p + 52, 0x200); /* DMA transfer cycle */ 111 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */ 112 put_le16(p + 54, s->cylinders); 113 put_le16(p + 55, s->heads); 114 put_le16(p + 56, s->sectors); 115 oldsize = s->cylinders * s->heads * s->sectors; 116 put_le16(p + 57, oldsize); 117 put_le16(p + 58, oldsize >> 16); 118 if (s->mult_sectors) 119 put_le16(p + 59, 0x100 | s->mult_sectors); 120 put_le16(p + 60, s->nb_sectors); 121 put_le16(p + 61, s->nb_sectors >> 16); 122 put_le16(p + 62, 0x07); /* single word dma0-2 supported */ 123 put_le16(p + 63, 0x07); /* mdma0-2 supported */ 124 put_le16(p + 64, 0x03); /* pio3-4 supported */ 125 put_le16(p + 65, 120); 126 put_le16(p + 66, 120); 127 put_le16(p + 67, 120); 128 put_le16(p + 68, 120); 129 if (dev && dev->conf.discard_granularity) { 130 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */ 131 } 132 133 if (s->ncq_queues) { 134 put_le16(p + 75, s->ncq_queues - 1); 135 /* NCQ supported */ 136 put_le16(p + 76, (1 << 8)); 137 } 138 139 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */ 140 put_le16(p + 81, 0x16); /* conforms to ata5 */ 141 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */ 142 put_le16(p + 82, (1 << 14) | (1 << 5) | 1); 143 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ 144 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); 145 /* 14=set to 1, 1=SMART self test, 0=SMART error logging */ 146 put_le16(p + 84, (1 << 14) | 0); 147 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */ 148 if (bdrv_enable_write_cache(s->bs)) 149 put_le16(p + 85, (1 << 14) | (1 << 5) | 1); 150 else 151 put_le16(p + 85, (1 << 14) | 1); 152 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ 153 put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); 154 /* 14=set to 1, 1=smart self test, 0=smart error logging */ 155 put_le16(p + 87, (1 << 14) | 0); 156 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ 157 put_le16(p + 93, 1 | (1 << 14) | 0x2000); 158 put_le16(p + 100, s->nb_sectors); 159 put_le16(p + 101, s->nb_sectors >> 16); 160 put_le16(p + 102, s->nb_sectors >> 32); 161 put_le16(p + 103, s->nb_sectors >> 48); 162 163 if (dev && dev->conf.physical_block_size) 164 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf)); 165 if (dev && dev->conf.discard_granularity) { 166 put_le16(p + 169, 1); /* TRIM support */ 167 } 168 169 memcpy(s->identify_data, p, sizeof(s->identify_data)); 170 s->identify_set = 1; 171 } 172 173 static void ide_atapi_identify(IDEState *s) 174 { 175 uint16_t *p; 176 177 if (s->identify_set) { 178 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data)); 179 return; 180 } 181 182 memset(s->io_buffer, 0, 512); 183 p = (uint16_t *)s->io_buffer; 184 /* Removable CDROM, 50us response, 12 byte packets */ 185 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0)); 186 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 187 put_le16(p + 20, 3); /* buffer type */ 188 put_le16(p + 21, 512); /* cache size in sectors */ 189 put_le16(p + 22, 4); /* ecc bytes */ 190 padstr((char *)(p + 23), s->version, 8); /* firmware version */ 191 padstr((char *)(p + 27), "QEMU DVD-ROM", 40); /* model */ 192 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */ 193 #ifdef USE_DMA_CDROM 194 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */ 195 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */ 196 put_le16(p + 62, 7); /* single word dma0-2 supported */ 197 put_le16(p + 63, 7); /* mdma0-2 supported */ 198 #else 199 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */ 200 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */ 201 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */ 202 #endif 203 put_le16(p + 64, 3); /* pio3-4 supported */ 204 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */ 205 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */ 206 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */ 207 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */ 208 209 put_le16(p + 71, 30); /* in ns */ 210 put_le16(p + 72, 30); /* in ns */ 211 212 if (s->ncq_queues) { 213 put_le16(p + 75, s->ncq_queues - 1); 214 /* NCQ supported */ 215 put_le16(p + 76, (1 << 8)); 216 } 217 218 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */ 219 #ifdef USE_DMA_CDROM 220 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ 221 #endif 222 memcpy(s->identify_data, p, sizeof(s->identify_data)); 223 s->identify_set = 1; 224 } 225 226 static void ide_cfata_identify(IDEState *s) 227 { 228 uint16_t *p; 229 uint32_t cur_sec; 230 231 p = (uint16_t *) s->identify_data; 232 if (s->identify_set) 233 goto fill_buffer; 234 235 memset(p, 0, sizeof(s->identify_data)); 236 237 cur_sec = s->cylinders * s->heads * s->sectors; 238 239 put_le16(p + 0, 0x848a); /* CF Storage Card signature */ 240 put_le16(p + 1, s->cylinders); /* Default cylinders */ 241 put_le16(p + 3, s->heads); /* Default heads */ 242 put_le16(p + 6, s->sectors); /* Default sectors per track */ 243 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */ 244 put_le16(p + 8, s->nb_sectors); /* Sectors per card */ 245 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 246 put_le16(p + 22, 0x0004); /* ECC bytes */ 247 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */ 248 padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */ 249 #if MAX_MULT_SECTORS > 1 250 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); 251 #else 252 put_le16(p + 47, 0x0000); 253 #endif 254 put_le16(p + 49, 0x0f00); /* Capabilities */ 255 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */ 256 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */ 257 put_le16(p + 53, 0x0003); /* Translation params valid */ 258 put_le16(p + 54, s->cylinders); /* Current cylinders */ 259 put_le16(p + 55, s->heads); /* Current heads */ 260 put_le16(p + 56, s->sectors); /* Current sectors */ 261 put_le16(p + 57, cur_sec); /* Current capacity */ 262 put_le16(p + 58, cur_sec >> 16); /* Current capacity */ 263 if (s->mult_sectors) /* Multiple sector setting */ 264 put_le16(p + 59, 0x100 | s->mult_sectors); 265 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */ 266 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */ 267 put_le16(p + 63, 0x0203); /* Multiword DMA capability */ 268 put_le16(p + 64, 0x0001); /* Flow Control PIO support */ 269 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */ 270 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */ 271 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */ 272 put_le16(p + 82, 0x400c); /* Command Set supported */ 273 put_le16(p + 83, 0x7068); /* Command Set supported */ 274 put_le16(p + 84, 0x4000); /* Features supported */ 275 put_le16(p + 85, 0x000c); /* Command Set enabled */ 276 put_le16(p + 86, 0x7044); /* Command Set enabled */ 277 put_le16(p + 87, 0x4000); /* Features enabled */ 278 put_le16(p + 91, 0x4060); /* Current APM level */ 279 put_le16(p + 129, 0x0002); /* Current features option */ 280 put_le16(p + 130, 0x0005); /* Reassigned sectors */ 281 put_le16(p + 131, 0x0001); /* Initial power mode */ 282 put_le16(p + 132, 0x0000); /* User signature */ 283 put_le16(p + 160, 0x8100); /* Power requirement */ 284 put_le16(p + 161, 0x8001); /* CF command set */ 285 286 s->identify_set = 1; 287 288 fill_buffer: 289 memcpy(s->io_buffer, p, sizeof(s->identify_data)); 290 } 291 292 static void ide_set_signature(IDEState *s) 293 { 294 s->select &= 0xf0; /* clear head */ 295 /* put signature */ 296 s->nsector = 1; 297 s->sector = 1; 298 if (s->drive_kind == IDE_CD) { 299 s->lcyl = 0x14; 300 s->hcyl = 0xeb; 301 } else if (s->bs) { 302 s->lcyl = 0; 303 s->hcyl = 0; 304 } else { 305 s->lcyl = 0xff; 306 s->hcyl = 0xff; 307 } 308 } 309 310 typedef struct TrimAIOCB { 311 BlockDriverAIOCB common; 312 QEMUBH *bh; 313 int ret; 314 } TrimAIOCB; 315 316 static void trim_aio_cancel(BlockDriverAIOCB *acb) 317 { 318 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common); 319 320 qemu_bh_delete(iocb->bh); 321 iocb->bh = NULL; 322 qemu_aio_release(iocb); 323 } 324 325 static AIOPool trim_aio_pool = { 326 .aiocb_size = sizeof(TrimAIOCB), 327 .cancel = trim_aio_cancel, 328 }; 329 330 static void ide_trim_bh_cb(void *opaque) 331 { 332 TrimAIOCB *iocb = opaque; 333 334 iocb->common.cb(iocb->common.opaque, iocb->ret); 335 336 qemu_bh_delete(iocb->bh); 337 iocb->bh = NULL; 338 339 qemu_aio_release(iocb); 340 } 341 342 BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs, 343 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, 344 BlockDriverCompletionFunc *cb, void *opaque) 345 { 346 TrimAIOCB *iocb; 347 int i, j, ret; 348 349 iocb = qemu_aio_get(&trim_aio_pool, bs, cb, opaque); 350 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb); 351 iocb->ret = 0; 352 353 for (j = 0; j < qiov->niov; j++) { 354 uint64_t *buffer = qiov->iov[j].iov_base; 355 356 for (i = 0; i < qiov->iov[j].iov_len / 8; i++) { 357 /* 6-byte LBA + 2-byte range per entry */ 358 uint64_t entry = le64_to_cpu(buffer[i]); 359 uint64_t sector = entry & 0x0000ffffffffffffULL; 360 uint16_t count = entry >> 48; 361 362 if (count == 0) { 363 break; 364 } 365 366 ret = bdrv_discard(bs, sector, count); 367 if (!iocb->ret) { 368 iocb->ret = ret; 369 } 370 } 371 } 372 373 qemu_bh_schedule(iocb->bh); 374 375 return &iocb->common; 376 } 377 378 static inline void ide_abort_command(IDEState *s) 379 { 380 s->status = READY_STAT | ERR_STAT; 381 s->error = ABRT_ERR; 382 } 383 384 /* prepare data transfer and tell what to do after */ 385 void ide_transfer_start(IDEState *s, uint8_t *buf, int size, 386 EndTransferFunc *end_transfer_func) 387 { 388 s->end_transfer_func = end_transfer_func; 389 s->data_ptr = buf; 390 s->data_end = buf + size; 391 if (!(s->status & ERR_STAT)) { 392 s->status |= DRQ_STAT; 393 } 394 s->bus->dma->ops->start_transfer(s->bus->dma); 395 } 396 397 void ide_transfer_stop(IDEState *s) 398 { 399 s->end_transfer_func = ide_transfer_stop; 400 s->data_ptr = s->io_buffer; 401 s->data_end = s->io_buffer; 402 s->status &= ~DRQ_STAT; 403 } 404 405 int64_t ide_get_sector(IDEState *s) 406 { 407 int64_t sector_num; 408 if (s->select & 0x40) { 409 /* lba */ 410 if (!s->lba48) { 411 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | 412 (s->lcyl << 8) | s->sector; 413 } else { 414 sector_num = ((int64_t)s->hob_hcyl << 40) | 415 ((int64_t) s->hob_lcyl << 32) | 416 ((int64_t) s->hob_sector << 24) | 417 ((int64_t) s->hcyl << 16) | 418 ((int64_t) s->lcyl << 8) | s->sector; 419 } 420 } else { 421 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors + 422 (s->select & 0x0f) * s->sectors + (s->sector - 1); 423 } 424 return sector_num; 425 } 426 427 void ide_set_sector(IDEState *s, int64_t sector_num) 428 { 429 unsigned int cyl, r; 430 if (s->select & 0x40) { 431 if (!s->lba48) { 432 s->select = (s->select & 0xf0) | (sector_num >> 24); 433 s->hcyl = (sector_num >> 16); 434 s->lcyl = (sector_num >> 8); 435 s->sector = (sector_num); 436 } else { 437 s->sector = sector_num; 438 s->lcyl = sector_num >> 8; 439 s->hcyl = sector_num >> 16; 440 s->hob_sector = sector_num >> 24; 441 s->hob_lcyl = sector_num >> 32; 442 s->hob_hcyl = sector_num >> 40; 443 } 444 } else { 445 cyl = sector_num / (s->heads * s->sectors); 446 r = sector_num % (s->heads * s->sectors); 447 s->hcyl = cyl >> 8; 448 s->lcyl = cyl; 449 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f); 450 s->sector = (r % s->sectors) + 1; 451 } 452 } 453 454 static void ide_rw_error(IDEState *s) { 455 ide_abort_command(s); 456 ide_set_irq(s->bus); 457 } 458 459 void ide_sector_read(IDEState *s) 460 { 461 int64_t sector_num; 462 int ret, n; 463 464 s->status = READY_STAT | SEEK_STAT; 465 s->error = 0; /* not needed by IDE spec, but needed by Windows */ 466 sector_num = ide_get_sector(s); 467 n = s->nsector; 468 if (n == 0) { 469 /* no more sector to read from disk */ 470 ide_transfer_stop(s); 471 } else { 472 #if defined(DEBUG_IDE) 473 printf("read sector=%" PRId64 "\n", sector_num); 474 #endif 475 if (n > s->req_nb_sectors) 476 n = s->req_nb_sectors; 477 478 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ); 479 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n); 480 bdrv_acct_done(s->bs, &s->acct); 481 if (ret != 0) { 482 if (ide_handle_rw_error(s, -ret, 483 BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ)) 484 { 485 return; 486 } 487 } 488 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read); 489 ide_set_irq(s->bus); 490 ide_set_sector(s, sector_num + n); 491 s->nsector -= n; 492 } 493 } 494 495 static void dma_buf_commit(IDEState *s, int is_write) 496 { 497 qemu_sglist_destroy(&s->sg); 498 } 499 500 void ide_set_inactive(IDEState *s) 501 { 502 s->bus->dma->aiocb = NULL; 503 s->bus->dma->ops->set_inactive(s->bus->dma); 504 } 505 506 void ide_dma_error(IDEState *s) 507 { 508 ide_transfer_stop(s); 509 s->error = ABRT_ERR; 510 s->status = READY_STAT | ERR_STAT; 511 ide_set_inactive(s); 512 ide_set_irq(s->bus); 513 } 514 515 static int ide_handle_rw_error(IDEState *s, int error, int op) 516 { 517 int is_read = (op & BM_STATUS_RETRY_READ); 518 BlockErrorAction action = bdrv_get_on_error(s->bs, is_read); 519 520 if (action == BLOCK_ERR_IGNORE) { 521 bdrv_mon_event(s->bs, BDRV_ACTION_IGNORE, is_read); 522 return 0; 523 } 524 525 if ((error == ENOSPC && action == BLOCK_ERR_STOP_ENOSPC) 526 || action == BLOCK_ERR_STOP_ANY) { 527 s->bus->dma->ops->set_unit(s->bus->dma, s->unit); 528 s->bus->error_status = op; 529 bdrv_mon_event(s->bs, BDRV_ACTION_STOP, is_read); 530 vm_stop(RSTATE_IO_ERROR); 531 } else { 532 if (op & BM_STATUS_DMA_RETRY) { 533 dma_buf_commit(s, 0); 534 ide_dma_error(s); 535 } else { 536 ide_rw_error(s); 537 } 538 bdrv_mon_event(s->bs, BDRV_ACTION_REPORT, is_read); 539 } 540 541 return 1; 542 } 543 544 void ide_dma_cb(void *opaque, int ret) 545 { 546 IDEState *s = opaque; 547 int n; 548 int64_t sector_num; 549 550 handle_rw_error: 551 if (ret < 0) { 552 int op = BM_STATUS_DMA_RETRY; 553 554 if (s->dma_cmd == IDE_DMA_READ) 555 op |= BM_STATUS_RETRY_READ; 556 else if (s->dma_cmd == IDE_DMA_TRIM) 557 op |= BM_STATUS_RETRY_TRIM; 558 559 if (ide_handle_rw_error(s, -ret, op)) { 560 return; 561 } 562 } 563 564 n = s->io_buffer_size >> 9; 565 sector_num = ide_get_sector(s); 566 if (n > 0) { 567 dma_buf_commit(s, ide_cmd_is_read(s)); 568 sector_num += n; 569 ide_set_sector(s, sector_num); 570 s->nsector -= n; 571 } 572 573 /* end of transfer ? */ 574 if (s->nsector == 0) { 575 s->status = READY_STAT | SEEK_STAT; 576 ide_set_irq(s->bus); 577 goto eot; 578 } 579 580 /* launch next transfer */ 581 n = s->nsector; 582 s->io_buffer_index = 0; 583 s->io_buffer_size = n * 512; 584 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) { 585 /* The PRDs were too short. Reset the Active bit, but don't raise an 586 * interrupt. */ 587 goto eot; 588 } 589 590 #ifdef DEBUG_AIO 591 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n", 592 sector_num, n, s->dma_cmd); 593 #endif 594 595 switch (s->dma_cmd) { 596 case IDE_DMA_READ: 597 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num, 598 ide_dma_cb, s); 599 break; 600 case IDE_DMA_WRITE: 601 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num, 602 ide_dma_cb, s); 603 break; 604 case IDE_DMA_TRIM: 605 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num, 606 ide_issue_trim, ide_dma_cb, s, true); 607 break; 608 } 609 610 if (!s->bus->dma->aiocb) { 611 ret = -1; 612 goto handle_rw_error; 613 } 614 return; 615 616 eot: 617 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { 618 bdrv_acct_done(s->bs, &s->acct); 619 } 620 ide_set_inactive(s); 621 } 622 623 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd) 624 { 625 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; 626 s->io_buffer_index = 0; 627 s->io_buffer_size = 0; 628 s->dma_cmd = dma_cmd; 629 630 switch (dma_cmd) { 631 case IDE_DMA_READ: 632 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE, 633 BDRV_ACCT_READ); 634 break; 635 case IDE_DMA_WRITE: 636 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE, 637 BDRV_ACCT_WRITE); 638 break; 639 default: 640 break; 641 } 642 643 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb); 644 } 645 646 static void ide_sector_write_timer_cb(void *opaque) 647 { 648 IDEState *s = opaque; 649 ide_set_irq(s->bus); 650 } 651 652 void ide_sector_write(IDEState *s) 653 { 654 int64_t sector_num; 655 int ret, n, n1; 656 657 s->status = READY_STAT | SEEK_STAT; 658 sector_num = ide_get_sector(s); 659 #if defined(DEBUG_IDE) 660 printf("write sector=%" PRId64 "\n", sector_num); 661 #endif 662 n = s->nsector; 663 if (n > s->req_nb_sectors) 664 n = s->req_nb_sectors; 665 666 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ); 667 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n); 668 bdrv_acct_done(s->bs, &s->acct); 669 670 if (ret != 0) { 671 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) 672 return; 673 } 674 675 s->nsector -= n; 676 if (s->nsector == 0) { 677 /* no more sectors to write */ 678 ide_transfer_stop(s); 679 } else { 680 n1 = s->nsector; 681 if (n1 > s->req_nb_sectors) 682 n1 = s->req_nb_sectors; 683 ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write); 684 } 685 ide_set_sector(s, sector_num + n); 686 687 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) { 688 /* It seems there is a bug in the Windows 2000 installer HDD 689 IDE driver which fills the disk with empty logs when the 690 IDE write IRQ comes too early. This hack tries to correct 691 that at the expense of slower write performances. Use this 692 option _only_ to install Windows 2000. You must disable it 693 for normal use. */ 694 qemu_mod_timer(s->sector_write_timer, 695 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000)); 696 } else { 697 ide_set_irq(s->bus); 698 } 699 } 700 701 static void ide_flush_cb(void *opaque, int ret) 702 { 703 IDEState *s = opaque; 704 705 if (ret < 0) { 706 /* XXX: What sector number to set here? */ 707 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) { 708 return; 709 } 710 } 711 712 bdrv_acct_done(s->bs, &s->acct); 713 s->status = READY_STAT | SEEK_STAT; 714 ide_set_irq(s->bus); 715 } 716 717 void ide_flush_cache(IDEState *s) 718 { 719 BlockDriverAIOCB *acb; 720 721 if (s->bs == NULL) { 722 ide_flush_cb(s, 0); 723 return; 724 } 725 726 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH); 727 acb = bdrv_aio_flush(s->bs, ide_flush_cb, s); 728 if (acb == NULL) { 729 ide_flush_cb(s, -EIO); 730 } 731 } 732 733 static void ide_cfata_metadata_inquiry(IDEState *s) 734 { 735 uint16_t *p; 736 uint32_t spd; 737 738 p = (uint16_t *) s->io_buffer; 739 memset(p, 0, 0x200); 740 spd = ((s->mdata_size - 1) >> 9) + 1; 741 742 put_le16(p + 0, 0x0001); /* Data format revision */ 743 put_le16(p + 1, 0x0000); /* Media property: silicon */ 744 put_le16(p + 2, s->media_changed); /* Media status */ 745 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */ 746 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */ 747 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */ 748 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */ 749 } 750 751 static void ide_cfata_metadata_read(IDEState *s) 752 { 753 uint16_t *p; 754 755 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { 756 s->status = ERR_STAT; 757 s->error = ABRT_ERR; 758 return; 759 } 760 761 p = (uint16_t *) s->io_buffer; 762 memset(p, 0, 0x200); 763 764 put_le16(p + 0, s->media_changed); /* Media status */ 765 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), 766 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), 767 s->nsector << 9), 0x200 - 2)); 768 } 769 770 static void ide_cfata_metadata_write(IDEState *s) 771 { 772 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { 773 s->status = ERR_STAT; 774 s->error = ABRT_ERR; 775 return; 776 } 777 778 s->media_changed = 0; 779 780 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), 781 s->io_buffer + 2, 782 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), 783 s->nsector << 9), 0x200 - 2)); 784 } 785 786 /* called when the inserted state of the media has changed */ 787 static void ide_cd_change_cb(void *opaque, bool load) 788 { 789 IDEState *s = opaque; 790 uint64_t nb_sectors; 791 792 s->tray_open = !load; 793 bdrv_get_geometry(s->bs, &nb_sectors); 794 s->nb_sectors = nb_sectors; 795 796 /* 797 * First indicate to the guest that a CD has been removed. That's 798 * done on the next command the guest sends us. 799 * 800 * Then we set SENSE_UNIT_ATTENTION, by which the guest will 801 * detect a new CD in the drive. See ide_atapi_cmd() for details. 802 */ 803 s->cdrom_changed = 1; 804 s->events.new_media = true; 805 ide_set_irq(s->bus); 806 } 807 808 static void ide_cmd_lba48_transform(IDEState *s, int lba48) 809 { 810 s->lba48 = lba48; 811 812 /* handle the 'magic' 0 nsector count conversion here. to avoid 813 * fiddling with the rest of the read logic, we just store the 814 * full sector count in ->nsector and ignore ->hob_nsector from now 815 */ 816 if (!s->lba48) { 817 if (!s->nsector) 818 s->nsector = 256; 819 } else { 820 if (!s->nsector && !s->hob_nsector) 821 s->nsector = 65536; 822 else { 823 int lo = s->nsector; 824 int hi = s->hob_nsector; 825 826 s->nsector = (hi << 8) | lo; 827 } 828 } 829 } 830 831 static void ide_clear_hob(IDEBus *bus) 832 { 833 /* any write clears HOB high bit of device control register */ 834 bus->ifs[0].select &= ~(1 << 7); 835 bus->ifs[1].select &= ~(1 << 7); 836 } 837 838 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) 839 { 840 IDEBus *bus = opaque; 841 842 #ifdef DEBUG_IDE 843 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val); 844 #endif 845 846 addr &= 7; 847 848 /* ignore writes to command block while busy with previous command */ 849 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT))) 850 return; 851 852 switch(addr) { 853 case 0: 854 break; 855 case 1: 856 ide_clear_hob(bus); 857 /* NOTE: data is written to the two drives */ 858 bus->ifs[0].hob_feature = bus->ifs[0].feature; 859 bus->ifs[1].hob_feature = bus->ifs[1].feature; 860 bus->ifs[0].feature = val; 861 bus->ifs[1].feature = val; 862 break; 863 case 2: 864 ide_clear_hob(bus); 865 bus->ifs[0].hob_nsector = bus->ifs[0].nsector; 866 bus->ifs[1].hob_nsector = bus->ifs[1].nsector; 867 bus->ifs[0].nsector = val; 868 bus->ifs[1].nsector = val; 869 break; 870 case 3: 871 ide_clear_hob(bus); 872 bus->ifs[0].hob_sector = bus->ifs[0].sector; 873 bus->ifs[1].hob_sector = bus->ifs[1].sector; 874 bus->ifs[0].sector = val; 875 bus->ifs[1].sector = val; 876 break; 877 case 4: 878 ide_clear_hob(bus); 879 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl; 880 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl; 881 bus->ifs[0].lcyl = val; 882 bus->ifs[1].lcyl = val; 883 break; 884 case 5: 885 ide_clear_hob(bus); 886 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl; 887 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl; 888 bus->ifs[0].hcyl = val; 889 bus->ifs[1].hcyl = val; 890 break; 891 case 6: 892 /* FIXME: HOB readback uses bit 7 */ 893 bus->ifs[0].select = (val & ~0x10) | 0xa0; 894 bus->ifs[1].select = (val | 0x10) | 0xa0; 895 /* select drive */ 896 bus->unit = (val >> 4) & 1; 897 break; 898 default: 899 case 7: 900 /* command */ 901 ide_exec_cmd(bus, val); 902 break; 903 } 904 } 905 906 #define HD_OK (1u << IDE_HD) 907 #define CD_OK (1u << IDE_CD) 908 #define CFA_OK (1u << IDE_CFATA) 909 #define HD_CFA_OK (HD_OK | CFA_OK) 910 #define ALL_OK (HD_OK | CD_OK | CFA_OK) 911 912 /* See ACS-2 T13/2015-D Table B.2 Command codes */ 913 static const uint8_t ide_cmd_table[0x100] = { 914 /* NOP not implemented, mandatory for CD */ 915 [CFA_REQ_EXT_ERROR_CODE] = CFA_OK, 916 [WIN_DSM] = ALL_OK, 917 [WIN_DEVICE_RESET] = CD_OK, 918 [WIN_RECAL] = HD_CFA_OK, 919 [WIN_READ] = ALL_OK, 920 [WIN_READ_ONCE] = ALL_OK, 921 [WIN_READ_EXT] = HD_CFA_OK, 922 [WIN_READDMA_EXT] = HD_CFA_OK, 923 [WIN_READ_NATIVE_MAX_EXT] = HD_CFA_OK, 924 [WIN_MULTREAD_EXT] = HD_CFA_OK, 925 [WIN_WRITE] = HD_CFA_OK, 926 [WIN_WRITE_ONCE] = HD_CFA_OK, 927 [WIN_WRITE_EXT] = HD_CFA_OK, 928 [WIN_WRITEDMA_EXT] = HD_CFA_OK, 929 [CFA_WRITE_SECT_WO_ERASE] = CFA_OK, 930 [WIN_MULTWRITE_EXT] = HD_CFA_OK, 931 [WIN_WRITE_VERIFY] = HD_CFA_OK, 932 [WIN_VERIFY] = HD_CFA_OK, 933 [WIN_VERIFY_ONCE] = HD_CFA_OK, 934 [WIN_VERIFY_EXT] = HD_CFA_OK, 935 [WIN_SEEK] = HD_CFA_OK, 936 [CFA_TRANSLATE_SECTOR] = CFA_OK, 937 [WIN_DIAGNOSE] = ALL_OK, 938 [WIN_SPECIFY] = HD_CFA_OK, 939 [WIN_STANDBYNOW2] = ALL_OK, 940 [WIN_IDLEIMMEDIATE2] = ALL_OK, 941 [WIN_STANDBY2] = ALL_OK, 942 [WIN_SETIDLE2] = ALL_OK, 943 [WIN_CHECKPOWERMODE2] = ALL_OK, 944 [WIN_SLEEPNOW2] = ALL_OK, 945 [WIN_PACKETCMD] = CD_OK, 946 [WIN_PIDENTIFY] = CD_OK, 947 [WIN_SMART] = HD_CFA_OK, 948 [CFA_ACCESS_METADATA_STORAGE] = CFA_OK, 949 [CFA_ERASE_SECTORS] = CFA_OK, 950 [WIN_MULTREAD] = HD_CFA_OK, 951 [WIN_MULTWRITE] = HD_CFA_OK, 952 [WIN_SETMULT] = HD_CFA_OK, 953 [WIN_READDMA] = HD_CFA_OK, 954 [WIN_READDMA_ONCE] = HD_CFA_OK, 955 [WIN_WRITEDMA] = HD_CFA_OK, 956 [WIN_WRITEDMA_ONCE] = HD_CFA_OK, 957 [CFA_WRITE_MULTI_WO_ERASE] = CFA_OK, 958 [WIN_STANDBYNOW1] = ALL_OK, 959 [WIN_IDLEIMMEDIATE] = ALL_OK, 960 [WIN_STANDBY] = ALL_OK, 961 [WIN_SETIDLE1] = ALL_OK, 962 [WIN_CHECKPOWERMODE1] = ALL_OK, 963 [WIN_SLEEPNOW1] = ALL_OK, 964 [WIN_FLUSH_CACHE] = ALL_OK, 965 [WIN_FLUSH_CACHE_EXT] = HD_CFA_OK, 966 [WIN_IDENTIFY] = ALL_OK, 967 [WIN_SETFEATURES] = ALL_OK, 968 [IBM_SENSE_CONDITION] = CFA_OK, 969 [CFA_WEAR_LEVEL] = CFA_OK, 970 [WIN_READ_NATIVE_MAX] = ALL_OK, 971 }; 972 973 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd) 974 { 975 return cmd < ARRAY_SIZE(ide_cmd_table) 976 && (ide_cmd_table[cmd] & (1u << s->drive_kind)); 977 } 978 979 void ide_exec_cmd(IDEBus *bus, uint32_t val) 980 { 981 IDEState *s; 982 int n; 983 int lba48 = 0; 984 985 #if defined(DEBUG_IDE) 986 printf("ide: CMD=%02x\n", val); 987 #endif 988 s = idebus_active_if(bus); 989 /* ignore commands to non existant slave */ 990 if (s != bus->ifs && !s->bs) 991 return; 992 993 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */ 994 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET) 995 return; 996 997 if (!ide_cmd_permitted(s, val)) { 998 goto abort_cmd; 999 } 1000 1001 switch(val) { 1002 case WIN_DSM: 1003 switch (s->feature) { 1004 case DSM_TRIM: 1005 if (!s->bs) { 1006 goto abort_cmd; 1007 } 1008 ide_sector_start_dma(s, IDE_DMA_TRIM); 1009 break; 1010 default: 1011 goto abort_cmd; 1012 } 1013 break; 1014 case WIN_IDENTIFY: 1015 if (s->bs && s->drive_kind != IDE_CD) { 1016 if (s->drive_kind != IDE_CFATA) 1017 ide_identify(s); 1018 else 1019 ide_cfata_identify(s); 1020 s->status = READY_STAT | SEEK_STAT; 1021 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); 1022 } else { 1023 if (s->drive_kind == IDE_CD) { 1024 ide_set_signature(s); 1025 } 1026 ide_abort_command(s); 1027 } 1028 ide_set_irq(s->bus); 1029 break; 1030 case WIN_SPECIFY: 1031 case WIN_RECAL: 1032 s->error = 0; 1033 s->status = READY_STAT | SEEK_STAT; 1034 ide_set_irq(s->bus); 1035 break; 1036 case WIN_SETMULT: 1037 if (s->drive_kind == IDE_CFATA && s->nsector == 0) { 1038 /* Disable Read and Write Multiple */ 1039 s->mult_sectors = 0; 1040 s->status = READY_STAT | SEEK_STAT; 1041 } else if ((s->nsector & 0xff) != 0 && 1042 ((s->nsector & 0xff) > MAX_MULT_SECTORS || 1043 (s->nsector & (s->nsector - 1)) != 0)) { 1044 ide_abort_command(s); 1045 } else { 1046 s->mult_sectors = s->nsector & 0xff; 1047 s->status = READY_STAT | SEEK_STAT; 1048 } 1049 ide_set_irq(s->bus); 1050 break; 1051 case WIN_VERIFY_EXT: 1052 lba48 = 1; 1053 case WIN_VERIFY: 1054 case WIN_VERIFY_ONCE: 1055 /* do sector number check ? */ 1056 ide_cmd_lba48_transform(s, lba48); 1057 s->status = READY_STAT | SEEK_STAT; 1058 ide_set_irq(s->bus); 1059 break; 1060 case WIN_READ_EXT: 1061 lba48 = 1; 1062 case WIN_READ: 1063 case WIN_READ_ONCE: 1064 if (s->drive_kind == IDE_CD) { 1065 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */ 1066 goto abort_cmd; 1067 } 1068 ide_cmd_lba48_transform(s, lba48); 1069 s->req_nb_sectors = 1; 1070 ide_sector_read(s); 1071 break; 1072 case WIN_WRITE_EXT: 1073 lba48 = 1; 1074 case WIN_WRITE: 1075 case WIN_WRITE_ONCE: 1076 case CFA_WRITE_SECT_WO_ERASE: 1077 case WIN_WRITE_VERIFY: 1078 ide_cmd_lba48_transform(s, lba48); 1079 s->error = 0; 1080 s->status = SEEK_STAT | READY_STAT; 1081 s->req_nb_sectors = 1; 1082 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write); 1083 s->media_changed = 1; 1084 break; 1085 case WIN_MULTREAD_EXT: 1086 lba48 = 1; 1087 case WIN_MULTREAD: 1088 if (!s->mult_sectors) 1089 goto abort_cmd; 1090 ide_cmd_lba48_transform(s, lba48); 1091 s->req_nb_sectors = s->mult_sectors; 1092 ide_sector_read(s); 1093 break; 1094 case WIN_MULTWRITE_EXT: 1095 lba48 = 1; 1096 case WIN_MULTWRITE: 1097 case CFA_WRITE_MULTI_WO_ERASE: 1098 if (!s->mult_sectors) 1099 goto abort_cmd; 1100 ide_cmd_lba48_transform(s, lba48); 1101 s->error = 0; 1102 s->status = SEEK_STAT | READY_STAT; 1103 s->req_nb_sectors = s->mult_sectors; 1104 n = s->nsector; 1105 if (n > s->req_nb_sectors) 1106 n = s->req_nb_sectors; 1107 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write); 1108 s->media_changed = 1; 1109 break; 1110 case WIN_READDMA_EXT: 1111 lba48 = 1; 1112 case WIN_READDMA: 1113 case WIN_READDMA_ONCE: 1114 if (!s->bs) 1115 goto abort_cmd; 1116 ide_cmd_lba48_transform(s, lba48); 1117 ide_sector_start_dma(s, IDE_DMA_READ); 1118 break; 1119 case WIN_WRITEDMA_EXT: 1120 lba48 = 1; 1121 case WIN_WRITEDMA: 1122 case WIN_WRITEDMA_ONCE: 1123 if (!s->bs) 1124 goto abort_cmd; 1125 ide_cmd_lba48_transform(s, lba48); 1126 ide_sector_start_dma(s, IDE_DMA_WRITE); 1127 s->media_changed = 1; 1128 break; 1129 case WIN_READ_NATIVE_MAX_EXT: 1130 lba48 = 1; 1131 case WIN_READ_NATIVE_MAX: 1132 ide_cmd_lba48_transform(s, lba48); 1133 ide_set_sector(s, s->nb_sectors - 1); 1134 s->status = READY_STAT | SEEK_STAT; 1135 ide_set_irq(s->bus); 1136 break; 1137 case WIN_CHECKPOWERMODE1: 1138 case WIN_CHECKPOWERMODE2: 1139 s->error = 0; 1140 s->nsector = 0xff; /* device active or idle */ 1141 s->status = READY_STAT | SEEK_STAT; 1142 ide_set_irq(s->bus); 1143 break; 1144 case WIN_SETFEATURES: 1145 if (!s->bs) 1146 goto abort_cmd; 1147 /* XXX: valid for CDROM ? */ 1148 switch(s->feature) { 1149 case 0xcc: /* reverting to power-on defaults enable */ 1150 case 0x66: /* reverting to power-on defaults disable */ 1151 case 0x02: /* write cache enable */ 1152 case 0x82: /* write cache disable */ 1153 case 0xaa: /* read look-ahead enable */ 1154 case 0x55: /* read look-ahead disable */ 1155 case 0x05: /* set advanced power management mode */ 1156 case 0x85: /* disable advanced power management mode */ 1157 case 0x69: /* NOP */ 1158 case 0x67: /* NOP */ 1159 case 0x96: /* NOP */ 1160 case 0x9a: /* NOP */ 1161 case 0x42: /* enable Automatic Acoustic Mode */ 1162 case 0xc2: /* disable Automatic Acoustic Mode */ 1163 s->status = READY_STAT | SEEK_STAT; 1164 ide_set_irq(s->bus); 1165 break; 1166 case 0x03: { /* set transfer mode */ 1167 uint8_t val = s->nsector & 0x07; 1168 uint16_t *identify_data = (uint16_t *)s->identify_data; 1169 1170 switch (s->nsector >> 3) { 1171 case 0x00: /* pio default */ 1172 case 0x01: /* pio mode */ 1173 put_le16(identify_data + 62,0x07); 1174 put_le16(identify_data + 63,0x07); 1175 put_le16(identify_data + 88,0x3f); 1176 break; 1177 case 0x02: /* sigle word dma mode*/ 1178 put_le16(identify_data + 62,0x07 | (1 << (val + 8))); 1179 put_le16(identify_data + 63,0x07); 1180 put_le16(identify_data + 88,0x3f); 1181 break; 1182 case 0x04: /* mdma mode */ 1183 put_le16(identify_data + 62,0x07); 1184 put_le16(identify_data + 63,0x07 | (1 << (val + 8))); 1185 put_le16(identify_data + 88,0x3f); 1186 break; 1187 case 0x08: /* udma mode */ 1188 put_le16(identify_data + 62,0x07); 1189 put_le16(identify_data + 63,0x07); 1190 put_le16(identify_data + 88,0x3f | (1 << (val + 8))); 1191 break; 1192 default: 1193 goto abort_cmd; 1194 } 1195 s->status = READY_STAT | SEEK_STAT; 1196 ide_set_irq(s->bus); 1197 break; 1198 } 1199 default: 1200 goto abort_cmd; 1201 } 1202 break; 1203 case WIN_FLUSH_CACHE: 1204 case WIN_FLUSH_CACHE_EXT: 1205 ide_flush_cache(s); 1206 break; 1207 case WIN_STANDBY: 1208 case WIN_STANDBY2: 1209 case WIN_STANDBYNOW1: 1210 case WIN_STANDBYNOW2: 1211 case WIN_IDLEIMMEDIATE: 1212 case WIN_IDLEIMMEDIATE2: 1213 case WIN_SETIDLE1: 1214 case WIN_SETIDLE2: 1215 case WIN_SLEEPNOW1: 1216 case WIN_SLEEPNOW2: 1217 s->status = READY_STAT; 1218 ide_set_irq(s->bus); 1219 break; 1220 case WIN_SEEK: 1221 /* XXX: Check that seek is within bounds */ 1222 s->status = READY_STAT | SEEK_STAT; 1223 ide_set_irq(s->bus); 1224 break; 1225 /* ATAPI commands */ 1226 case WIN_PIDENTIFY: 1227 ide_atapi_identify(s); 1228 s->status = READY_STAT | SEEK_STAT; 1229 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); 1230 ide_set_irq(s->bus); 1231 break; 1232 case WIN_DIAGNOSE: 1233 ide_set_signature(s); 1234 if (s->drive_kind == IDE_CD) 1235 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet 1236 * devices to return a clear status register 1237 * with READY_STAT *not* set. */ 1238 else 1239 s->status = READY_STAT | SEEK_STAT; 1240 s->error = 0x01; /* Device 0 passed, Device 1 passed or not 1241 * present. 1242 */ 1243 ide_set_irq(s->bus); 1244 break; 1245 case WIN_DEVICE_RESET: 1246 ide_set_signature(s); 1247 s->status = 0x00; /* NOTE: READY is _not_ set */ 1248 s->error = 0x01; 1249 break; 1250 case WIN_PACKETCMD: 1251 /* overlapping commands not supported */ 1252 if (s->feature & 0x02) 1253 goto abort_cmd; 1254 s->status = READY_STAT | SEEK_STAT; 1255 s->atapi_dma = s->feature & 1; 1256 s->nsector = 1; 1257 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, 1258 ide_atapi_cmd); 1259 break; 1260 /* CF-ATA commands */ 1261 case CFA_REQ_EXT_ERROR_CODE: 1262 s->error = 0x09; /* miscellaneous error */ 1263 s->status = READY_STAT | SEEK_STAT; 1264 ide_set_irq(s->bus); 1265 break; 1266 case CFA_ERASE_SECTORS: 1267 case CFA_WEAR_LEVEL: 1268 if (val == CFA_WEAR_LEVEL) 1269 s->nsector = 0; 1270 if (val == CFA_ERASE_SECTORS) 1271 s->media_changed = 1; 1272 s->error = 0x00; 1273 s->status = READY_STAT | SEEK_STAT; 1274 ide_set_irq(s->bus); 1275 break; 1276 case CFA_TRANSLATE_SECTOR: 1277 s->error = 0x00; 1278 s->status = READY_STAT | SEEK_STAT; 1279 memset(s->io_buffer, 0, 0x200); 1280 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */ 1281 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */ 1282 s->io_buffer[0x02] = s->select; /* Head */ 1283 s->io_buffer[0x03] = s->sector; /* Sector */ 1284 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */ 1285 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */ 1286 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */ 1287 s->io_buffer[0x13] = 0x00; /* Erase flag */ 1288 s->io_buffer[0x18] = 0x00; /* Hot count */ 1289 s->io_buffer[0x19] = 0x00; /* Hot count */ 1290 s->io_buffer[0x1a] = 0x01; /* Hot count */ 1291 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1292 ide_set_irq(s->bus); 1293 break; 1294 case CFA_ACCESS_METADATA_STORAGE: 1295 switch (s->feature) { 1296 case 0x02: /* Inquiry Metadata Storage */ 1297 ide_cfata_metadata_inquiry(s); 1298 break; 1299 case 0x03: /* Read Metadata Storage */ 1300 ide_cfata_metadata_read(s); 1301 break; 1302 case 0x04: /* Write Metadata Storage */ 1303 ide_cfata_metadata_write(s); 1304 break; 1305 default: 1306 goto abort_cmd; 1307 } 1308 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1309 s->status = 0x00; /* NOTE: READY is _not_ set */ 1310 ide_set_irq(s->bus); 1311 break; 1312 case IBM_SENSE_CONDITION: 1313 switch (s->feature) { 1314 case 0x01: /* sense temperature in device */ 1315 s->nsector = 0x50; /* +20 C */ 1316 break; 1317 default: 1318 goto abort_cmd; 1319 } 1320 s->status = READY_STAT | SEEK_STAT; 1321 ide_set_irq(s->bus); 1322 break; 1323 1324 case WIN_SMART: 1325 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) 1326 goto abort_cmd; 1327 if (!s->smart_enabled && s->feature != SMART_ENABLE) 1328 goto abort_cmd; 1329 switch (s->feature) { 1330 case SMART_DISABLE: 1331 s->smart_enabled = 0; 1332 s->status = READY_STAT | SEEK_STAT; 1333 ide_set_irq(s->bus); 1334 break; 1335 case SMART_ENABLE: 1336 s->smart_enabled = 1; 1337 s->status = READY_STAT | SEEK_STAT; 1338 ide_set_irq(s->bus); 1339 break; 1340 case SMART_ATTR_AUTOSAVE: 1341 switch (s->sector) { 1342 case 0x00: 1343 s->smart_autosave = 0; 1344 break; 1345 case 0xf1: 1346 s->smart_autosave = 1; 1347 break; 1348 default: 1349 goto abort_cmd; 1350 } 1351 s->status = READY_STAT | SEEK_STAT; 1352 ide_set_irq(s->bus); 1353 break; 1354 case SMART_STATUS: 1355 if (!s->smart_errors) { 1356 s->hcyl = 0xc2; 1357 s->lcyl = 0x4f; 1358 } else { 1359 s->hcyl = 0x2c; 1360 s->lcyl = 0xf4; 1361 } 1362 s->status = READY_STAT | SEEK_STAT; 1363 ide_set_irq(s->bus); 1364 break; 1365 case SMART_READ_THRESH: 1366 memset(s->io_buffer, 0, 0x200); 1367 s->io_buffer[0] = 0x01; /* smart struct version */ 1368 for (n=0; n<30; n++) { 1369 if (smart_attributes[n][0] == 0) 1370 break; 1371 s->io_buffer[2+0+(n*12)] = smart_attributes[n][0]; 1372 s->io_buffer[2+1+(n*12)] = smart_attributes[n][11]; 1373 } 1374 for (n=0; n<511; n++) /* checksum */ 1375 s->io_buffer[511] += s->io_buffer[n]; 1376 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1377 s->status = READY_STAT | SEEK_STAT; 1378 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1379 ide_set_irq(s->bus); 1380 break; 1381 case SMART_READ_DATA: 1382 memset(s->io_buffer, 0, 0x200); 1383 s->io_buffer[0] = 0x01; /* smart struct version */ 1384 for (n=0; n<30; n++) { 1385 if (smart_attributes[n][0] == 0) { 1386 break; 1387 } 1388 int i; 1389 for(i = 0; i < 11; i++) { 1390 s->io_buffer[2+i+(n*12)] = smart_attributes[n][i]; 1391 } 1392 } 1393 s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00); 1394 if (s->smart_selftest_count == 0) { 1395 s->io_buffer[363] = 0; 1396 } else { 1397 s->io_buffer[363] = 1398 s->smart_selftest_data[3 + 1399 (s->smart_selftest_count - 1) * 1400 24]; 1401 } 1402 s->io_buffer[364] = 0x20; 1403 s->io_buffer[365] = 0x01; 1404 /* offline data collection capacity: execute + self-test*/ 1405 s->io_buffer[367] = (1<<4 | 1<<3 | 1); 1406 s->io_buffer[368] = 0x03; /* smart capability (1) */ 1407 s->io_buffer[369] = 0x00; /* smart capability (2) */ 1408 s->io_buffer[370] = 0x01; /* error logging supported */ 1409 s->io_buffer[372] = 0x02; /* minutes for poll short test */ 1410 s->io_buffer[373] = 0x36; /* minutes for poll ext test */ 1411 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */ 1412 1413 for (n=0; n<511; n++) 1414 s->io_buffer[511] += s->io_buffer[n]; 1415 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1416 s->status = READY_STAT | SEEK_STAT; 1417 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1418 ide_set_irq(s->bus); 1419 break; 1420 case SMART_READ_LOG: 1421 switch (s->sector) { 1422 case 0x01: /* summary smart error log */ 1423 memset(s->io_buffer, 0, 0x200); 1424 s->io_buffer[0] = 0x01; 1425 s->io_buffer[1] = 0x00; /* no error entries */ 1426 s->io_buffer[452] = s->smart_errors & 0xff; 1427 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8; 1428 1429 for (n=0; n<511; n++) 1430 s->io_buffer[511] += s->io_buffer[n]; 1431 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1432 break; 1433 case 0x06: /* smart self test log */ 1434 memset(s->io_buffer, 0, 0x200); 1435 s->io_buffer[0] = 0x01; 1436 if (s->smart_selftest_count == 0) { 1437 s->io_buffer[508] = 0; 1438 } else { 1439 s->io_buffer[508] = s->smart_selftest_count; 1440 for (n=2; n<506; n++) 1441 s->io_buffer[n] = s->smart_selftest_data[n]; 1442 } 1443 for (n=0; n<511; n++) 1444 s->io_buffer[511] += s->io_buffer[n]; 1445 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1446 break; 1447 default: 1448 goto abort_cmd; 1449 } 1450 s->status = READY_STAT | SEEK_STAT; 1451 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1452 ide_set_irq(s->bus); 1453 break; 1454 case SMART_EXECUTE_OFFLINE: 1455 switch (s->sector) { 1456 case 0: /* off-line routine */ 1457 case 1: /* short self test */ 1458 case 2: /* extended self test */ 1459 s->smart_selftest_count++; 1460 if(s->smart_selftest_count > 21) 1461 s->smart_selftest_count = 0; 1462 n = 2 + (s->smart_selftest_count - 1) * 24; 1463 s->smart_selftest_data[n] = s->sector; 1464 s->smart_selftest_data[n+1] = 0x00; /* OK and finished */ 1465 s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */ 1466 s->smart_selftest_data[n+3] = 0x12; /* hour count msb */ 1467 s->status = READY_STAT | SEEK_STAT; 1468 ide_set_irq(s->bus); 1469 break; 1470 default: 1471 goto abort_cmd; 1472 } 1473 break; 1474 default: 1475 goto abort_cmd; 1476 } 1477 break; 1478 default: 1479 /* should not be reachable */ 1480 abort_cmd: 1481 ide_abort_command(s); 1482 ide_set_irq(s->bus); 1483 break; 1484 } 1485 } 1486 1487 uint32_t ide_ioport_read(void *opaque, uint32_t addr1) 1488 { 1489 IDEBus *bus = opaque; 1490 IDEState *s = idebus_active_if(bus); 1491 uint32_t addr; 1492 int ret, hob; 1493 1494 addr = addr1 & 7; 1495 /* FIXME: HOB readback uses bit 7, but it's always set right now */ 1496 //hob = s->select & (1 << 7); 1497 hob = 0; 1498 switch(addr) { 1499 case 0: 1500 ret = 0xff; 1501 break; 1502 case 1: 1503 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || 1504 (s != bus->ifs && !s->bs)) 1505 ret = 0; 1506 else if (!hob) 1507 ret = s->error; 1508 else 1509 ret = s->hob_feature; 1510 break; 1511 case 2: 1512 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1513 ret = 0; 1514 else if (!hob) 1515 ret = s->nsector & 0xff; 1516 else 1517 ret = s->hob_nsector; 1518 break; 1519 case 3: 1520 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1521 ret = 0; 1522 else if (!hob) 1523 ret = s->sector; 1524 else 1525 ret = s->hob_sector; 1526 break; 1527 case 4: 1528 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1529 ret = 0; 1530 else if (!hob) 1531 ret = s->lcyl; 1532 else 1533 ret = s->hob_lcyl; 1534 break; 1535 case 5: 1536 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1537 ret = 0; 1538 else if (!hob) 1539 ret = s->hcyl; 1540 else 1541 ret = s->hob_hcyl; 1542 break; 1543 case 6: 1544 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1545 ret = 0; 1546 else 1547 ret = s->select; 1548 break; 1549 default: 1550 case 7: 1551 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || 1552 (s != bus->ifs && !s->bs)) 1553 ret = 0; 1554 else 1555 ret = s->status; 1556 qemu_irq_lower(bus->irq); 1557 break; 1558 } 1559 #ifdef DEBUG_IDE 1560 printf("ide: read addr=0x%x val=%02x\n", addr1, ret); 1561 #endif 1562 return ret; 1563 } 1564 1565 uint32_t ide_status_read(void *opaque, uint32_t addr) 1566 { 1567 IDEBus *bus = opaque; 1568 IDEState *s = idebus_active_if(bus); 1569 int ret; 1570 1571 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || 1572 (s != bus->ifs && !s->bs)) 1573 ret = 0; 1574 else 1575 ret = s->status; 1576 #ifdef DEBUG_IDE 1577 printf("ide: read status addr=0x%x val=%02x\n", addr, ret); 1578 #endif 1579 return ret; 1580 } 1581 1582 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) 1583 { 1584 IDEBus *bus = opaque; 1585 IDEState *s; 1586 int i; 1587 1588 #ifdef DEBUG_IDE 1589 printf("ide: write control addr=0x%x val=%02x\n", addr, val); 1590 #endif 1591 /* common for both drives */ 1592 if (!(bus->cmd & IDE_CMD_RESET) && 1593 (val & IDE_CMD_RESET)) { 1594 /* reset low to high */ 1595 for(i = 0;i < 2; i++) { 1596 s = &bus->ifs[i]; 1597 s->status = BUSY_STAT | SEEK_STAT; 1598 s->error = 0x01; 1599 } 1600 } else if ((bus->cmd & IDE_CMD_RESET) && 1601 !(val & IDE_CMD_RESET)) { 1602 /* high to low */ 1603 for(i = 0;i < 2; i++) { 1604 s = &bus->ifs[i]; 1605 if (s->drive_kind == IDE_CD) 1606 s->status = 0x00; /* NOTE: READY is _not_ set */ 1607 else 1608 s->status = READY_STAT | SEEK_STAT; 1609 ide_set_signature(s); 1610 } 1611 } 1612 1613 bus->cmd = val; 1614 } 1615 1616 /* 1617 * Returns true if the running PIO transfer is a PIO out (i.e. data is 1618 * transferred from the device to the guest), false if it's a PIO in 1619 */ 1620 static bool ide_is_pio_out(IDEState *s) 1621 { 1622 if (s->end_transfer_func == ide_sector_write || 1623 s->end_transfer_func == ide_atapi_cmd) { 1624 return false; 1625 } else if (s->end_transfer_func == ide_sector_read || 1626 s->end_transfer_func == ide_transfer_stop || 1627 s->end_transfer_func == ide_atapi_cmd_reply_end || 1628 s->end_transfer_func == ide_dummy_transfer_stop) { 1629 return true; 1630 } 1631 1632 abort(); 1633 } 1634 1635 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val) 1636 { 1637 IDEBus *bus = opaque; 1638 IDEState *s = idebus_active_if(bus); 1639 uint8_t *p; 1640 1641 /* PIO data access allowed only when DRQ bit is set. The result of a write 1642 * during PIO out is indeterminate, just ignore it. */ 1643 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { 1644 return; 1645 } 1646 1647 p = s->data_ptr; 1648 *(uint16_t *)p = le16_to_cpu(val); 1649 p += 2; 1650 s->data_ptr = p; 1651 if (p >= s->data_end) 1652 s->end_transfer_func(s); 1653 } 1654 1655 uint32_t ide_data_readw(void *opaque, uint32_t addr) 1656 { 1657 IDEBus *bus = opaque; 1658 IDEState *s = idebus_active_if(bus); 1659 uint8_t *p; 1660 int ret; 1661 1662 /* PIO data access allowed only when DRQ bit is set. The result of a read 1663 * during PIO in is indeterminate, return 0 and don't move forward. */ 1664 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { 1665 return 0; 1666 } 1667 1668 p = s->data_ptr; 1669 ret = cpu_to_le16(*(uint16_t *)p); 1670 p += 2; 1671 s->data_ptr = p; 1672 if (p >= s->data_end) 1673 s->end_transfer_func(s); 1674 return ret; 1675 } 1676 1677 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val) 1678 { 1679 IDEBus *bus = opaque; 1680 IDEState *s = idebus_active_if(bus); 1681 uint8_t *p; 1682 1683 /* PIO data access allowed only when DRQ bit is set. The result of a write 1684 * during PIO out is indeterminate, just ignore it. */ 1685 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { 1686 return; 1687 } 1688 1689 p = s->data_ptr; 1690 *(uint32_t *)p = le32_to_cpu(val); 1691 p += 4; 1692 s->data_ptr = p; 1693 if (p >= s->data_end) 1694 s->end_transfer_func(s); 1695 } 1696 1697 uint32_t ide_data_readl(void *opaque, uint32_t addr) 1698 { 1699 IDEBus *bus = opaque; 1700 IDEState *s = idebus_active_if(bus); 1701 uint8_t *p; 1702 int ret; 1703 1704 /* PIO data access allowed only when DRQ bit is set. The result of a read 1705 * during PIO in is indeterminate, return 0 and don't move forward. */ 1706 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { 1707 return 0; 1708 } 1709 1710 p = s->data_ptr; 1711 ret = cpu_to_le32(*(uint32_t *)p); 1712 p += 4; 1713 s->data_ptr = p; 1714 if (p >= s->data_end) 1715 s->end_transfer_func(s); 1716 return ret; 1717 } 1718 1719 static void ide_dummy_transfer_stop(IDEState *s) 1720 { 1721 s->data_ptr = s->io_buffer; 1722 s->data_end = s->io_buffer; 1723 s->io_buffer[0] = 0xff; 1724 s->io_buffer[1] = 0xff; 1725 s->io_buffer[2] = 0xff; 1726 s->io_buffer[3] = 0xff; 1727 } 1728 1729 static void ide_reset(IDEState *s) 1730 { 1731 #ifdef DEBUG_IDE 1732 printf("ide: reset\n"); 1733 #endif 1734 if (s->drive_kind == IDE_CFATA) 1735 s->mult_sectors = 0; 1736 else 1737 s->mult_sectors = MAX_MULT_SECTORS; 1738 /* ide regs */ 1739 s->feature = 0; 1740 s->error = 0; 1741 s->nsector = 0; 1742 s->sector = 0; 1743 s->lcyl = 0; 1744 s->hcyl = 0; 1745 1746 /* lba48 */ 1747 s->hob_feature = 0; 1748 s->hob_sector = 0; 1749 s->hob_nsector = 0; 1750 s->hob_lcyl = 0; 1751 s->hob_hcyl = 0; 1752 1753 s->select = 0xa0; 1754 s->status = READY_STAT | SEEK_STAT; 1755 1756 s->lba48 = 0; 1757 1758 /* ATAPI specific */ 1759 s->sense_key = 0; 1760 s->asc = 0; 1761 s->cdrom_changed = 0; 1762 s->packet_transfer_size = 0; 1763 s->elementary_transfer_size = 0; 1764 s->io_buffer_index = 0; 1765 s->cd_sector_size = 0; 1766 s->atapi_dma = 0; 1767 /* ATA DMA state */ 1768 s->io_buffer_size = 0; 1769 s->req_nb_sectors = 0; 1770 1771 ide_set_signature(s); 1772 /* init the transfer handler so that 0xffff is returned on data 1773 accesses */ 1774 s->end_transfer_func = ide_dummy_transfer_stop; 1775 ide_dummy_transfer_stop(s); 1776 s->media_changed = 0; 1777 } 1778 1779 void ide_bus_reset(IDEBus *bus) 1780 { 1781 bus->unit = 0; 1782 bus->cmd = 0; 1783 ide_reset(&bus->ifs[0]); 1784 ide_reset(&bus->ifs[1]); 1785 ide_clear_hob(bus); 1786 1787 /* pending async DMA */ 1788 if (bus->dma->aiocb) { 1789 #ifdef DEBUG_AIO 1790 printf("aio_cancel\n"); 1791 #endif 1792 bdrv_aio_cancel(bus->dma->aiocb); 1793 bus->dma->aiocb = NULL; 1794 } 1795 1796 /* reset dma provider too */ 1797 bus->dma->ops->reset(bus->dma); 1798 } 1799 1800 static bool ide_cd_is_tray_open(void *opaque) 1801 { 1802 return ((IDEState *)opaque)->tray_open; 1803 } 1804 1805 static bool ide_cd_is_medium_locked(void *opaque) 1806 { 1807 return ((IDEState *)opaque)->tray_locked; 1808 } 1809 1810 static const BlockDevOps ide_cd_block_ops = { 1811 .change_media_cb = ide_cd_change_cb, 1812 .is_tray_open = ide_cd_is_tray_open, 1813 .is_medium_locked = ide_cd_is_medium_locked, 1814 }; 1815 1816 int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind, 1817 const char *version, const char *serial) 1818 { 1819 int cylinders, heads, secs; 1820 uint64_t nb_sectors; 1821 1822 s->bs = bs; 1823 s->drive_kind = kind; 1824 1825 bdrv_get_geometry(bs, &nb_sectors); 1826 bdrv_guess_geometry(bs, &cylinders, &heads, &secs); 1827 if (cylinders < 1 || cylinders > 16383) { 1828 error_report("cyls must be between 1 and 16383"); 1829 return -1; 1830 } 1831 if (heads < 1 || heads > 16) { 1832 error_report("heads must be between 1 and 16"); 1833 return -1; 1834 } 1835 if (secs < 1 || secs > 63) { 1836 error_report("secs must be between 1 and 63"); 1837 return -1; 1838 } 1839 s->cylinders = cylinders; 1840 s->heads = heads; 1841 s->sectors = secs; 1842 s->nb_sectors = nb_sectors; 1843 /* The SMART values should be preserved across power cycles 1844 but they aren't. */ 1845 s->smart_enabled = 1; 1846 s->smart_autosave = 1; 1847 s->smart_errors = 0; 1848 s->smart_selftest_count = 0; 1849 if (kind == IDE_CD) { 1850 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s); 1851 bdrv_set_buffer_alignment(bs, 2048); 1852 } else { 1853 if (!bdrv_is_inserted(s->bs)) { 1854 error_report("Device needs media, but drive is empty"); 1855 return -1; 1856 } 1857 if (bdrv_is_read_only(bs)) { 1858 error_report("Can't use a read-only drive"); 1859 return -1; 1860 } 1861 } 1862 if (serial) { 1863 strncpy(s->drive_serial_str, serial, sizeof(s->drive_serial_str)); 1864 } else { 1865 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str), 1866 "QM%05d", s->drive_serial); 1867 } 1868 if (version) { 1869 pstrcpy(s->version, sizeof(s->version), version); 1870 } else { 1871 pstrcpy(s->version, sizeof(s->version), QEMU_VERSION); 1872 } 1873 1874 ide_reset(s); 1875 return 0; 1876 } 1877 1878 static void ide_init1(IDEBus *bus, int unit) 1879 { 1880 static int drive_serial = 1; 1881 IDEState *s = &bus->ifs[unit]; 1882 1883 s->bus = bus; 1884 s->unit = unit; 1885 s->drive_serial = drive_serial++; 1886 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */ 1887 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; 1888 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len); 1889 memset(s->io_buffer, 0, s->io_buffer_total_len); 1890 1891 s->smart_selftest_data = qemu_blockalign(s->bs, 512); 1892 memset(s->smart_selftest_data, 0, 512); 1893 1894 s->sector_write_timer = qemu_new_timer_ns(vm_clock, 1895 ide_sector_write_timer_cb, s); 1896 } 1897 1898 static void ide_nop_start(IDEDMA *dma, IDEState *s, 1899 BlockDriverCompletionFunc *cb) 1900 { 1901 } 1902 1903 static int ide_nop(IDEDMA *dma) 1904 { 1905 return 0; 1906 } 1907 1908 static int ide_nop_int(IDEDMA *dma, int x) 1909 { 1910 return 0; 1911 } 1912 1913 static void ide_nop_restart(void *opaque, int x, RunState y) 1914 { 1915 } 1916 1917 static const IDEDMAOps ide_dma_nop_ops = { 1918 .start_dma = ide_nop_start, 1919 .start_transfer = ide_nop, 1920 .prepare_buf = ide_nop_int, 1921 .rw_buf = ide_nop_int, 1922 .set_unit = ide_nop_int, 1923 .add_status = ide_nop_int, 1924 .set_inactive = ide_nop, 1925 .restart_cb = ide_nop_restart, 1926 .reset = ide_nop, 1927 }; 1928 1929 static IDEDMA ide_dma_nop = { 1930 .ops = &ide_dma_nop_ops, 1931 .aiocb = NULL, 1932 }; 1933 1934 void ide_init2(IDEBus *bus, qemu_irq irq) 1935 { 1936 int i; 1937 1938 for(i = 0; i < 2; i++) { 1939 ide_init1(bus, i); 1940 ide_reset(&bus->ifs[i]); 1941 } 1942 bus->irq = irq; 1943 bus->dma = &ide_dma_nop; 1944 } 1945 1946 /* TODO convert users to qdev and remove */ 1947 void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0, 1948 DriveInfo *hd1, qemu_irq irq) 1949 { 1950 int i; 1951 DriveInfo *dinfo; 1952 1953 for(i = 0; i < 2; i++) { 1954 dinfo = i == 0 ? hd0 : hd1; 1955 ide_init1(bus, i); 1956 if (dinfo) { 1957 if (ide_init_drive(&bus->ifs[i], dinfo->bdrv, 1958 dinfo->media_cd ? IDE_CD : IDE_HD, NULL, 1959 *dinfo->serial ? dinfo->serial : NULL) < 0) { 1960 error_report("Can't set up IDE drive %s", dinfo->id); 1961 exit(1); 1962 } 1963 bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]); 1964 } else { 1965 ide_reset(&bus->ifs[i]); 1966 } 1967 } 1968 bus->irq = irq; 1969 bus->dma = &ide_dma_nop; 1970 } 1971 1972 void ide_init_ioport(IDEBus *bus, int iobase, int iobase2) 1973 { 1974 register_ioport_write(iobase, 8, 1, ide_ioport_write, bus); 1975 register_ioport_read(iobase, 8, 1, ide_ioport_read, bus); 1976 if (iobase2) { 1977 register_ioport_read(iobase2, 1, 1, ide_status_read, bus); 1978 register_ioport_write(iobase2, 1, 1, ide_cmd_write, bus); 1979 } 1980 1981 /* data ports */ 1982 register_ioport_write(iobase, 2, 2, ide_data_writew, bus); 1983 register_ioport_read(iobase, 2, 2, ide_data_readw, bus); 1984 register_ioport_write(iobase, 4, 4, ide_data_writel, bus); 1985 register_ioport_read(iobase, 4, 4, ide_data_readl, bus); 1986 } 1987 1988 static bool is_identify_set(void *opaque, int version_id) 1989 { 1990 IDEState *s = opaque; 1991 1992 return s->identify_set != 0; 1993 } 1994 1995 static EndTransferFunc* transfer_end_table[] = { 1996 ide_sector_read, 1997 ide_sector_write, 1998 ide_transfer_stop, 1999 ide_atapi_cmd_reply_end, 2000 ide_atapi_cmd, 2001 ide_dummy_transfer_stop, 2002 }; 2003 2004 static int transfer_end_table_idx(EndTransferFunc *fn) 2005 { 2006 int i; 2007 2008 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++) 2009 if (transfer_end_table[i] == fn) 2010 return i; 2011 2012 return -1; 2013 } 2014 2015 static int ide_drive_post_load(void *opaque, int version_id) 2016 { 2017 IDEState *s = opaque; 2018 2019 if (version_id < 3) { 2020 if (s->sense_key == SENSE_UNIT_ATTENTION && 2021 s->asc == ASC_MEDIUM_MAY_HAVE_CHANGED) { 2022 s->cdrom_changed = 1; 2023 } 2024 } 2025 return 0; 2026 } 2027 2028 static int ide_drive_pio_post_load(void *opaque, int version_id) 2029 { 2030 IDEState *s = opaque; 2031 2032 if (s->end_transfer_fn_idx > ARRAY_SIZE(transfer_end_table)) { 2033 return -EINVAL; 2034 } 2035 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx]; 2036 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset; 2037 s->data_end = s->data_ptr + s->cur_io_buffer_len; 2038 2039 return 0; 2040 } 2041 2042 static void ide_drive_pio_pre_save(void *opaque) 2043 { 2044 IDEState *s = opaque; 2045 int idx; 2046 2047 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer; 2048 s->cur_io_buffer_len = s->data_end - s->data_ptr; 2049 2050 idx = transfer_end_table_idx(s->end_transfer_func); 2051 if (idx == -1) { 2052 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n", 2053 __func__); 2054 s->end_transfer_fn_idx = 2; 2055 } else { 2056 s->end_transfer_fn_idx = idx; 2057 } 2058 } 2059 2060 static bool ide_drive_pio_state_needed(void *opaque) 2061 { 2062 IDEState *s = opaque; 2063 2064 return ((s->status & DRQ_STAT) != 0) 2065 || (s->bus->error_status & BM_STATUS_PIO_RETRY); 2066 } 2067 2068 static int ide_tray_state_post_load(void *opaque, int version_id) 2069 { 2070 IDEState *s = opaque; 2071 2072 bdrv_eject(s->bs, s->tray_open); 2073 bdrv_lock_medium(s->bs, s->tray_locked); 2074 return 0; 2075 } 2076 2077 static bool ide_tray_state_needed(void *opaque) 2078 { 2079 IDEState *s = opaque; 2080 2081 return s->tray_open || s->tray_locked; 2082 } 2083 2084 static bool ide_atapi_gesn_needed(void *opaque) 2085 { 2086 IDEState *s = opaque; 2087 2088 return s->events.new_media || s->events.eject_request; 2089 } 2090 2091 static bool ide_error_needed(void *opaque) 2092 { 2093 IDEBus *bus = opaque; 2094 2095 return (bus->error_status != 0); 2096 } 2097 2098 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */ 2099 static const VMStateDescription vmstate_ide_atapi_gesn_state = { 2100 .name ="ide_drive/atapi/gesn_state", 2101 .version_id = 1, 2102 .minimum_version_id = 1, 2103 .minimum_version_id_old = 1, 2104 .fields = (VMStateField []) { 2105 VMSTATE_BOOL(events.new_media, IDEState), 2106 VMSTATE_BOOL(events.eject_request, IDEState), 2107 VMSTATE_END_OF_LIST() 2108 } 2109 }; 2110 2111 static const VMStateDescription vmstate_ide_tray_state = { 2112 .name = "ide_drive/tray_state", 2113 .version_id = 1, 2114 .minimum_version_id = 1, 2115 .minimum_version_id_old = 1, 2116 .post_load = ide_tray_state_post_load, 2117 .fields = (VMStateField[]) { 2118 VMSTATE_BOOL(tray_open, IDEState), 2119 VMSTATE_BOOL(tray_locked, IDEState), 2120 VMSTATE_END_OF_LIST() 2121 } 2122 }; 2123 2124 static const VMStateDescription vmstate_ide_drive_pio_state = { 2125 .name = "ide_drive/pio_state", 2126 .version_id = 1, 2127 .minimum_version_id = 1, 2128 .minimum_version_id_old = 1, 2129 .pre_save = ide_drive_pio_pre_save, 2130 .post_load = ide_drive_pio_post_load, 2131 .fields = (VMStateField []) { 2132 VMSTATE_INT32(req_nb_sectors, IDEState), 2133 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1, 2134 vmstate_info_uint8, uint8_t), 2135 VMSTATE_INT32(cur_io_buffer_offset, IDEState), 2136 VMSTATE_INT32(cur_io_buffer_len, IDEState), 2137 VMSTATE_UINT8(end_transfer_fn_idx, IDEState), 2138 VMSTATE_INT32(elementary_transfer_size, IDEState), 2139 VMSTATE_INT32(packet_transfer_size, IDEState), 2140 VMSTATE_END_OF_LIST() 2141 } 2142 }; 2143 2144 const VMStateDescription vmstate_ide_drive = { 2145 .name = "ide_drive", 2146 .version_id = 3, 2147 .minimum_version_id = 0, 2148 .minimum_version_id_old = 0, 2149 .post_load = ide_drive_post_load, 2150 .fields = (VMStateField []) { 2151 VMSTATE_INT32(mult_sectors, IDEState), 2152 VMSTATE_INT32(identify_set, IDEState), 2153 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set), 2154 VMSTATE_UINT8(feature, IDEState), 2155 VMSTATE_UINT8(error, IDEState), 2156 VMSTATE_UINT32(nsector, IDEState), 2157 VMSTATE_UINT8(sector, IDEState), 2158 VMSTATE_UINT8(lcyl, IDEState), 2159 VMSTATE_UINT8(hcyl, IDEState), 2160 VMSTATE_UINT8(hob_feature, IDEState), 2161 VMSTATE_UINT8(hob_sector, IDEState), 2162 VMSTATE_UINT8(hob_nsector, IDEState), 2163 VMSTATE_UINT8(hob_lcyl, IDEState), 2164 VMSTATE_UINT8(hob_hcyl, IDEState), 2165 VMSTATE_UINT8(select, IDEState), 2166 VMSTATE_UINT8(status, IDEState), 2167 VMSTATE_UINT8(lba48, IDEState), 2168 VMSTATE_UINT8(sense_key, IDEState), 2169 VMSTATE_UINT8(asc, IDEState), 2170 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3), 2171 VMSTATE_END_OF_LIST() 2172 }, 2173 .subsections = (VMStateSubsection []) { 2174 { 2175 .vmsd = &vmstate_ide_drive_pio_state, 2176 .needed = ide_drive_pio_state_needed, 2177 }, { 2178 .vmsd = &vmstate_ide_tray_state, 2179 .needed = ide_tray_state_needed, 2180 }, { 2181 .vmsd = &vmstate_ide_atapi_gesn_state, 2182 .needed = ide_atapi_gesn_needed, 2183 }, { 2184 /* empty */ 2185 } 2186 } 2187 }; 2188 2189 static const VMStateDescription vmstate_ide_error_status = { 2190 .name ="ide_bus/error", 2191 .version_id = 1, 2192 .minimum_version_id = 1, 2193 .minimum_version_id_old = 1, 2194 .fields = (VMStateField []) { 2195 VMSTATE_INT32(error_status, IDEBus), 2196 VMSTATE_END_OF_LIST() 2197 } 2198 }; 2199 2200 const VMStateDescription vmstate_ide_bus = { 2201 .name = "ide_bus", 2202 .version_id = 1, 2203 .minimum_version_id = 1, 2204 .minimum_version_id_old = 1, 2205 .fields = (VMStateField []) { 2206 VMSTATE_UINT8(cmd, IDEBus), 2207 VMSTATE_UINT8(unit, IDEBus), 2208 VMSTATE_END_OF_LIST() 2209 }, 2210 .subsections = (VMStateSubsection []) { 2211 { 2212 .vmsd = &vmstate_ide_error_status, 2213 .needed = ide_error_needed, 2214 }, { 2215 /* empty */ 2216 } 2217 } 2218 }; 2219 2220 void ide_drive_get(DriveInfo **hd, int max_bus) 2221 { 2222 int i; 2223 2224 if (drive_get_max_bus(IF_IDE) >= max_bus) { 2225 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus); 2226 exit(1); 2227 } 2228 2229 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) { 2230 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); 2231 } 2232 } 2233