1 /* 2 * QEMU IDE disk and CD/DVD-ROM Emulator 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include <hw/hw.h> 27 #include <hw/i386/pc.h> 28 #include <hw/pci/pci.h> 29 #include <hw/isa/isa.h> 30 #include "qemu/error-report.h" 31 #include "qemu/timer.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/dma.h" 34 #include "hw/block/block.h" 35 #include "sysemu/block-backend.h" 36 37 #include <hw/ide/internal.h> 38 39 /* These values were based on a Seagate ST3500418AS but have been modified 40 to make more sense in QEMU */ 41 static const int smart_attributes[][12] = { 42 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */ 43 /* raw read error rate*/ 44 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06}, 45 /* spin up */ 46 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 47 /* start stop count */ 48 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14}, 49 /* remapped sectors */ 50 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24}, 51 /* power on hours */ 52 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 53 /* power cycle count */ 54 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 55 /* airflow-temperature-celsius */ 56 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32}, 57 }; 58 59 static int ide_handle_rw_error(IDEState *s, int error, int op); 60 static void ide_dummy_transfer_stop(IDEState *s); 61 62 static void padstr(char *str, const char *src, int len) 63 { 64 int i, v; 65 for(i = 0; i < len; i++) { 66 if (*src) 67 v = *src++; 68 else 69 v = ' '; 70 str[i^1] = v; 71 } 72 } 73 74 static void put_le16(uint16_t *p, unsigned int v) 75 { 76 *p = cpu_to_le16(v); 77 } 78 79 static void ide_identify_size(IDEState *s) 80 { 81 uint16_t *p = (uint16_t *)s->identify_data; 82 put_le16(p + 60, s->nb_sectors); 83 put_le16(p + 61, s->nb_sectors >> 16); 84 put_le16(p + 100, s->nb_sectors); 85 put_le16(p + 101, s->nb_sectors >> 16); 86 put_le16(p + 102, s->nb_sectors >> 32); 87 put_le16(p + 103, s->nb_sectors >> 48); 88 } 89 90 static void ide_identify(IDEState *s) 91 { 92 uint16_t *p; 93 unsigned int oldsize; 94 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master; 95 96 p = (uint16_t *)s->identify_data; 97 if (s->identify_set) { 98 goto fill_buffer; 99 } 100 memset(p, 0, sizeof(s->identify_data)); 101 102 put_le16(p + 0, 0x0040); 103 put_le16(p + 1, s->cylinders); 104 put_le16(p + 3, s->heads); 105 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */ 106 put_le16(p + 5, 512); /* XXX: retired, remove ? */ 107 put_le16(p + 6, s->sectors); 108 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 109 put_le16(p + 20, 3); /* XXX: retired, remove ? */ 110 put_le16(p + 21, 512); /* cache size in sectors */ 111 put_le16(p + 22, 4); /* ecc bytes */ 112 padstr((char *)(p + 23), s->version, 8); /* firmware version */ 113 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */ 114 #if MAX_MULT_SECTORS > 1 115 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); 116 #endif 117 put_le16(p + 48, 1); /* dword I/O */ 118 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */ 119 put_le16(p + 51, 0x200); /* PIO transfer cycle */ 120 put_le16(p + 52, 0x200); /* DMA transfer cycle */ 121 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */ 122 put_le16(p + 54, s->cylinders); 123 put_le16(p + 55, s->heads); 124 put_le16(p + 56, s->sectors); 125 oldsize = s->cylinders * s->heads * s->sectors; 126 put_le16(p + 57, oldsize); 127 put_le16(p + 58, oldsize >> 16); 128 if (s->mult_sectors) 129 put_le16(p + 59, 0x100 | s->mult_sectors); 130 /* *(p + 60) := nb_sectors -- see ide_identify_size */ 131 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */ 132 put_le16(p + 62, 0x07); /* single word dma0-2 supported */ 133 put_le16(p + 63, 0x07); /* mdma0-2 supported */ 134 put_le16(p + 64, 0x03); /* pio3-4 supported */ 135 put_le16(p + 65, 120); 136 put_le16(p + 66, 120); 137 put_le16(p + 67, 120); 138 put_le16(p + 68, 120); 139 if (dev && dev->conf.discard_granularity) { 140 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */ 141 } 142 143 if (s->ncq_queues) { 144 put_le16(p + 75, s->ncq_queues - 1); 145 /* NCQ supported */ 146 put_le16(p + 76, (1 << 8)); 147 } 148 149 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */ 150 put_le16(p + 81, 0x16); /* conforms to ata5 */ 151 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */ 152 put_le16(p + 82, (1 << 14) | (1 << 5) | 1); 153 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ 154 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); 155 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */ 156 if (s->wwn) { 157 put_le16(p + 84, (1 << 14) | (1 << 8) | 0); 158 } else { 159 put_le16(p + 84, (1 << 14) | 0); 160 } 161 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */ 162 if (blk_enable_write_cache(s->blk)) { 163 put_le16(p + 85, (1 << 14) | (1 << 5) | 1); 164 } else { 165 put_le16(p + 85, (1 << 14) | 1); 166 } 167 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ 168 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10)); 169 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */ 170 if (s->wwn) { 171 put_le16(p + 87, (1 << 14) | (1 << 8) | 0); 172 } else { 173 put_le16(p + 87, (1 << 14) | 0); 174 } 175 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ 176 put_le16(p + 93, 1 | (1 << 14) | 0x2000); 177 /* *(p + 100) := nb_sectors -- see ide_identify_size */ 178 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */ 179 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */ 180 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */ 181 182 if (dev && dev->conf.physical_block_size) 183 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf)); 184 if (s->wwn) { 185 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */ 186 put_le16(p + 108, s->wwn >> 48); 187 put_le16(p + 109, s->wwn >> 32); 188 put_le16(p + 110, s->wwn >> 16); 189 put_le16(p + 111, s->wwn); 190 } 191 if (dev && dev->conf.discard_granularity) { 192 put_le16(p + 169, 1); /* TRIM support */ 193 } 194 195 ide_identify_size(s); 196 s->identify_set = 1; 197 198 fill_buffer: 199 memcpy(s->io_buffer, p, sizeof(s->identify_data)); 200 } 201 202 static void ide_atapi_identify(IDEState *s) 203 { 204 uint16_t *p; 205 206 p = (uint16_t *)s->identify_data; 207 if (s->identify_set) { 208 goto fill_buffer; 209 } 210 memset(p, 0, sizeof(s->identify_data)); 211 212 /* Removable CDROM, 50us response, 12 byte packets */ 213 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0)); 214 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 215 put_le16(p + 20, 3); /* buffer type */ 216 put_le16(p + 21, 512); /* cache size in sectors */ 217 put_le16(p + 22, 4); /* ecc bytes */ 218 padstr((char *)(p + 23), s->version, 8); /* firmware version */ 219 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */ 220 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */ 221 #ifdef USE_DMA_CDROM 222 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */ 223 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */ 224 put_le16(p + 62, 7); /* single word dma0-2 supported */ 225 put_le16(p + 63, 7); /* mdma0-2 supported */ 226 #else 227 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */ 228 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */ 229 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */ 230 #endif 231 put_le16(p + 64, 3); /* pio3-4 supported */ 232 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */ 233 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */ 234 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */ 235 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */ 236 237 put_le16(p + 71, 30); /* in ns */ 238 put_le16(p + 72, 30); /* in ns */ 239 240 if (s->ncq_queues) { 241 put_le16(p + 75, s->ncq_queues - 1); 242 /* NCQ supported */ 243 put_le16(p + 76, (1 << 8)); 244 } 245 246 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */ 247 if (s->wwn) { 248 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */ 249 put_le16(p + 87, (1 << 8)); /* WWN enabled */ 250 } 251 252 #ifdef USE_DMA_CDROM 253 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ 254 #endif 255 256 if (s->wwn) { 257 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */ 258 put_le16(p + 108, s->wwn >> 48); 259 put_le16(p + 109, s->wwn >> 32); 260 put_le16(p + 110, s->wwn >> 16); 261 put_le16(p + 111, s->wwn); 262 } 263 264 s->identify_set = 1; 265 266 fill_buffer: 267 memcpy(s->io_buffer, p, sizeof(s->identify_data)); 268 } 269 270 static void ide_cfata_identify_size(IDEState *s) 271 { 272 uint16_t *p = (uint16_t *)s->identify_data; 273 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */ 274 put_le16(p + 8, s->nb_sectors); /* Sectors per card */ 275 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */ 276 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */ 277 } 278 279 static void ide_cfata_identify(IDEState *s) 280 { 281 uint16_t *p; 282 uint32_t cur_sec; 283 284 p = (uint16_t *)s->identify_data; 285 if (s->identify_set) { 286 goto fill_buffer; 287 } 288 memset(p, 0, sizeof(s->identify_data)); 289 290 cur_sec = s->cylinders * s->heads * s->sectors; 291 292 put_le16(p + 0, 0x848a); /* CF Storage Card signature */ 293 put_le16(p + 1, s->cylinders); /* Default cylinders */ 294 put_le16(p + 3, s->heads); /* Default heads */ 295 put_le16(p + 6, s->sectors); /* Default sectors per track */ 296 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */ 297 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */ 298 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 299 put_le16(p + 22, 0x0004); /* ECC bytes */ 300 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */ 301 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */ 302 #if MAX_MULT_SECTORS > 1 303 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); 304 #else 305 put_le16(p + 47, 0x0000); 306 #endif 307 put_le16(p + 49, 0x0f00); /* Capabilities */ 308 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */ 309 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */ 310 put_le16(p + 53, 0x0003); /* Translation params valid */ 311 put_le16(p + 54, s->cylinders); /* Current cylinders */ 312 put_le16(p + 55, s->heads); /* Current heads */ 313 put_le16(p + 56, s->sectors); /* Current sectors */ 314 put_le16(p + 57, cur_sec); /* Current capacity */ 315 put_le16(p + 58, cur_sec >> 16); /* Current capacity */ 316 if (s->mult_sectors) /* Multiple sector setting */ 317 put_le16(p + 59, 0x100 | s->mult_sectors); 318 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */ 319 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */ 320 put_le16(p + 63, 0x0203); /* Multiword DMA capability */ 321 put_le16(p + 64, 0x0001); /* Flow Control PIO support */ 322 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */ 323 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */ 324 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */ 325 put_le16(p + 82, 0x400c); /* Command Set supported */ 326 put_le16(p + 83, 0x7068); /* Command Set supported */ 327 put_le16(p + 84, 0x4000); /* Features supported */ 328 put_le16(p + 85, 0x000c); /* Command Set enabled */ 329 put_le16(p + 86, 0x7044); /* Command Set enabled */ 330 put_le16(p + 87, 0x4000); /* Features enabled */ 331 put_le16(p + 91, 0x4060); /* Current APM level */ 332 put_le16(p + 129, 0x0002); /* Current features option */ 333 put_le16(p + 130, 0x0005); /* Reassigned sectors */ 334 put_le16(p + 131, 0x0001); /* Initial power mode */ 335 put_le16(p + 132, 0x0000); /* User signature */ 336 put_le16(p + 160, 0x8100); /* Power requirement */ 337 put_le16(p + 161, 0x8001); /* CF command set */ 338 339 ide_cfata_identify_size(s); 340 s->identify_set = 1; 341 342 fill_buffer: 343 memcpy(s->io_buffer, p, sizeof(s->identify_data)); 344 } 345 346 static void ide_set_signature(IDEState *s) 347 { 348 s->select &= 0xf0; /* clear head */ 349 /* put signature */ 350 s->nsector = 1; 351 s->sector = 1; 352 if (s->drive_kind == IDE_CD) { 353 s->lcyl = 0x14; 354 s->hcyl = 0xeb; 355 } else if (s->blk) { 356 s->lcyl = 0; 357 s->hcyl = 0; 358 } else { 359 s->lcyl = 0xff; 360 s->hcyl = 0xff; 361 } 362 } 363 364 typedef struct TrimAIOCB { 365 BlockAIOCB common; 366 BlockBackend *blk; 367 QEMUBH *bh; 368 int ret; 369 QEMUIOVector *qiov; 370 BlockAIOCB *aiocb; 371 int i, j; 372 } TrimAIOCB; 373 374 static void trim_aio_cancel(BlockAIOCB *acb) 375 { 376 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common); 377 378 /* Exit the loop so ide_issue_trim_cb will not continue */ 379 iocb->j = iocb->qiov->niov - 1; 380 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1; 381 382 iocb->ret = -ECANCELED; 383 384 if (iocb->aiocb) { 385 blk_aio_cancel_async(iocb->aiocb); 386 iocb->aiocb = NULL; 387 } 388 } 389 390 static const AIOCBInfo trim_aiocb_info = { 391 .aiocb_size = sizeof(TrimAIOCB), 392 .cancel_async = trim_aio_cancel, 393 }; 394 395 static void ide_trim_bh_cb(void *opaque) 396 { 397 TrimAIOCB *iocb = opaque; 398 399 iocb->common.cb(iocb->common.opaque, iocb->ret); 400 401 qemu_bh_delete(iocb->bh); 402 iocb->bh = NULL; 403 qemu_aio_unref(iocb); 404 } 405 406 static void ide_issue_trim_cb(void *opaque, int ret) 407 { 408 TrimAIOCB *iocb = opaque; 409 if (ret >= 0) { 410 while (iocb->j < iocb->qiov->niov) { 411 int j = iocb->j; 412 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) { 413 int i = iocb->i; 414 uint64_t *buffer = iocb->qiov->iov[j].iov_base; 415 416 /* 6-byte LBA + 2-byte range per entry */ 417 uint64_t entry = le64_to_cpu(buffer[i]); 418 uint64_t sector = entry & 0x0000ffffffffffffULL; 419 uint16_t count = entry >> 48; 420 421 if (count == 0) { 422 continue; 423 } 424 425 /* Got an entry! Submit and exit. */ 426 iocb->aiocb = blk_aio_discard(iocb->blk, sector, count, 427 ide_issue_trim_cb, opaque); 428 return; 429 } 430 431 iocb->j++; 432 iocb->i = -1; 433 } 434 } else { 435 iocb->ret = ret; 436 } 437 438 iocb->aiocb = NULL; 439 if (iocb->bh) { 440 qemu_bh_schedule(iocb->bh); 441 } 442 } 443 444 BlockAIOCB *ide_issue_trim(BlockBackend *blk, 445 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, 446 BlockCompletionFunc *cb, void *opaque) 447 { 448 TrimAIOCB *iocb; 449 450 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque); 451 iocb->blk = blk; 452 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb); 453 iocb->ret = 0; 454 iocb->qiov = qiov; 455 iocb->i = -1; 456 iocb->j = 0; 457 ide_issue_trim_cb(iocb, 0); 458 return &iocb->common; 459 } 460 461 void ide_abort_command(IDEState *s) 462 { 463 ide_transfer_stop(s); 464 s->status = READY_STAT | ERR_STAT; 465 s->error = ABRT_ERR; 466 } 467 468 /* prepare data transfer and tell what to do after */ 469 void ide_transfer_start(IDEState *s, uint8_t *buf, int size, 470 EndTransferFunc *end_transfer_func) 471 { 472 s->end_transfer_func = end_transfer_func; 473 s->data_ptr = buf; 474 s->data_end = buf + size; 475 if (!(s->status & ERR_STAT)) { 476 s->status |= DRQ_STAT; 477 } 478 if (s->bus->dma->ops->start_transfer) { 479 s->bus->dma->ops->start_transfer(s->bus->dma); 480 } 481 } 482 483 static void ide_cmd_done(IDEState *s) 484 { 485 if (s->bus->dma->ops->cmd_done) { 486 s->bus->dma->ops->cmd_done(s->bus->dma); 487 } 488 } 489 490 void ide_transfer_stop(IDEState *s) 491 { 492 s->end_transfer_func = ide_transfer_stop; 493 s->data_ptr = s->io_buffer; 494 s->data_end = s->io_buffer; 495 s->status &= ~DRQ_STAT; 496 ide_cmd_done(s); 497 } 498 499 int64_t ide_get_sector(IDEState *s) 500 { 501 int64_t sector_num; 502 if (s->select & 0x40) { 503 /* lba */ 504 if (!s->lba48) { 505 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | 506 (s->lcyl << 8) | s->sector; 507 } else { 508 sector_num = ((int64_t)s->hob_hcyl << 40) | 509 ((int64_t) s->hob_lcyl << 32) | 510 ((int64_t) s->hob_sector << 24) | 511 ((int64_t) s->hcyl << 16) | 512 ((int64_t) s->lcyl << 8) | s->sector; 513 } 514 } else { 515 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors + 516 (s->select & 0x0f) * s->sectors + (s->sector - 1); 517 } 518 return sector_num; 519 } 520 521 void ide_set_sector(IDEState *s, int64_t sector_num) 522 { 523 unsigned int cyl, r; 524 if (s->select & 0x40) { 525 if (!s->lba48) { 526 s->select = (s->select & 0xf0) | (sector_num >> 24); 527 s->hcyl = (sector_num >> 16); 528 s->lcyl = (sector_num >> 8); 529 s->sector = (sector_num); 530 } else { 531 s->sector = sector_num; 532 s->lcyl = sector_num >> 8; 533 s->hcyl = sector_num >> 16; 534 s->hob_sector = sector_num >> 24; 535 s->hob_lcyl = sector_num >> 32; 536 s->hob_hcyl = sector_num >> 40; 537 } 538 } else { 539 cyl = sector_num / (s->heads * s->sectors); 540 r = sector_num % (s->heads * s->sectors); 541 s->hcyl = cyl >> 8; 542 s->lcyl = cyl; 543 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f); 544 s->sector = (r % s->sectors) + 1; 545 } 546 } 547 548 static void ide_rw_error(IDEState *s) { 549 ide_abort_command(s); 550 ide_set_irq(s->bus); 551 } 552 553 static bool ide_sect_range_ok(IDEState *s, 554 uint64_t sector, uint64_t nb_sectors) 555 { 556 uint64_t total_sectors; 557 558 blk_get_geometry(s->blk, &total_sectors); 559 if (sector > total_sectors || nb_sectors > total_sectors - sector) { 560 return false; 561 } 562 return true; 563 } 564 565 static void ide_buffered_readv_cb(void *opaque, int ret) 566 { 567 IDEBufferedRequest *req = opaque; 568 if (!req->orphaned) { 569 if (!ret) { 570 qemu_iovec_from_buf(req->original_qiov, 0, req->iov.iov_base, 571 req->original_qiov->size); 572 } 573 req->original_cb(req->original_opaque, ret); 574 } 575 QLIST_REMOVE(req, list); 576 qemu_vfree(req->iov.iov_base); 577 g_free(req); 578 } 579 580 #define MAX_BUFFERED_REQS 16 581 582 BlockAIOCB *ide_buffered_readv(IDEState *s, int64_t sector_num, 583 QEMUIOVector *iov, int nb_sectors, 584 BlockCompletionFunc *cb, void *opaque) 585 { 586 BlockAIOCB *aioreq; 587 IDEBufferedRequest *req; 588 int c = 0; 589 590 QLIST_FOREACH(req, &s->buffered_requests, list) { 591 c++; 592 } 593 if (c > MAX_BUFFERED_REQS) { 594 return blk_abort_aio_request(s->blk, cb, opaque, -EIO); 595 } 596 597 req = g_new0(IDEBufferedRequest, 1); 598 req->original_qiov = iov; 599 req->original_cb = cb; 600 req->original_opaque = opaque; 601 req->iov.iov_base = qemu_blockalign(blk_bs(s->blk), iov->size); 602 req->iov.iov_len = iov->size; 603 qemu_iovec_init_external(&req->qiov, &req->iov, 1); 604 605 aioreq = blk_aio_readv(s->blk, sector_num, &req->qiov, nb_sectors, 606 ide_buffered_readv_cb, req); 607 608 QLIST_INSERT_HEAD(&s->buffered_requests, req, list); 609 return aioreq; 610 } 611 612 static void ide_sector_read(IDEState *s); 613 614 static void ide_sector_read_cb(void *opaque, int ret) 615 { 616 IDEState *s = opaque; 617 int n; 618 619 s->pio_aiocb = NULL; 620 s->status &= ~BUSY_STAT; 621 622 if (ret == -ECANCELED) { 623 return; 624 } 625 if (ret != 0) { 626 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO | 627 IDE_RETRY_READ)) { 628 return; 629 } 630 } 631 632 block_acct_done(blk_get_stats(s->blk), &s->acct); 633 634 n = s->nsector; 635 if (n > s->req_nb_sectors) { 636 n = s->req_nb_sectors; 637 } 638 639 ide_set_sector(s, ide_get_sector(s) + n); 640 s->nsector -= n; 641 /* Allow the guest to read the io_buffer */ 642 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read); 643 ide_set_irq(s->bus); 644 } 645 646 static void ide_sector_read(IDEState *s) 647 { 648 int64_t sector_num; 649 int n; 650 651 s->status = READY_STAT | SEEK_STAT; 652 s->error = 0; /* not needed by IDE spec, but needed by Windows */ 653 sector_num = ide_get_sector(s); 654 n = s->nsector; 655 656 if (n == 0) { 657 ide_transfer_stop(s); 658 return; 659 } 660 661 s->status |= BUSY_STAT; 662 663 if (n > s->req_nb_sectors) { 664 n = s->req_nb_sectors; 665 } 666 667 #if defined(DEBUG_IDE) 668 printf("sector=%" PRId64 "\n", sector_num); 669 #endif 670 671 if (!ide_sect_range_ok(s, sector_num, n)) { 672 ide_rw_error(s); 673 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_READ); 674 return; 675 } 676 677 s->iov.iov_base = s->io_buffer; 678 s->iov.iov_len = n * BDRV_SECTOR_SIZE; 679 qemu_iovec_init_external(&s->qiov, &s->iov, 1); 680 681 block_acct_start(blk_get_stats(s->blk), &s->acct, 682 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ); 683 s->pio_aiocb = ide_buffered_readv(s, sector_num, &s->qiov, n, 684 ide_sector_read_cb, s); 685 } 686 687 void dma_buf_commit(IDEState *s, uint32_t tx_bytes) 688 { 689 if (s->bus->dma->ops->commit_buf) { 690 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes); 691 } 692 s->io_buffer_offset += tx_bytes; 693 qemu_sglist_destroy(&s->sg); 694 } 695 696 void ide_set_inactive(IDEState *s, bool more) 697 { 698 s->bus->dma->aiocb = NULL; 699 s->bus->retry_unit = -1; 700 s->bus->retry_sector_num = 0; 701 s->bus->retry_nsector = 0; 702 if (s->bus->dma->ops->set_inactive) { 703 s->bus->dma->ops->set_inactive(s->bus->dma, more); 704 } 705 ide_cmd_done(s); 706 } 707 708 void ide_dma_error(IDEState *s) 709 { 710 dma_buf_commit(s, 0); 711 ide_abort_command(s); 712 ide_set_inactive(s, false); 713 ide_set_irq(s->bus); 714 } 715 716 static int ide_handle_rw_error(IDEState *s, int error, int op) 717 { 718 bool is_read = (op & IDE_RETRY_READ) != 0; 719 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error); 720 721 if (action == BLOCK_ERROR_ACTION_STOP) { 722 assert(s->bus->retry_unit == s->unit); 723 s->bus->error_status = op; 724 } else if (action == BLOCK_ERROR_ACTION_REPORT) { 725 block_acct_failed(blk_get_stats(s->blk), &s->acct); 726 if (op & IDE_RETRY_DMA) { 727 ide_dma_error(s); 728 } else { 729 ide_rw_error(s); 730 } 731 } 732 blk_error_action(s->blk, action, is_read, error); 733 return action != BLOCK_ERROR_ACTION_IGNORE; 734 } 735 736 static void ide_dma_cb(void *opaque, int ret) 737 { 738 IDEState *s = opaque; 739 int n; 740 int64_t sector_num; 741 bool stay_active = false; 742 743 if (ret == -ECANCELED) { 744 return; 745 } 746 if (ret < 0) { 747 int op = IDE_RETRY_DMA; 748 749 if (s->dma_cmd == IDE_DMA_READ) 750 op |= IDE_RETRY_READ; 751 else if (s->dma_cmd == IDE_DMA_TRIM) 752 op |= IDE_RETRY_TRIM; 753 754 if (ide_handle_rw_error(s, -ret, op)) { 755 return; 756 } 757 } 758 759 n = s->io_buffer_size >> 9; 760 if (n > s->nsector) { 761 /* The PRDs were longer than needed for this request. Shorten them so 762 * we don't get a negative remainder. The Active bit must remain set 763 * after the request completes. */ 764 n = s->nsector; 765 stay_active = true; 766 } 767 768 sector_num = ide_get_sector(s); 769 if (n > 0) { 770 assert(n * 512 == s->sg.size); 771 dma_buf_commit(s, s->sg.size); 772 sector_num += n; 773 ide_set_sector(s, sector_num); 774 s->nsector -= n; 775 } 776 777 /* end of transfer ? */ 778 if (s->nsector == 0) { 779 s->status = READY_STAT | SEEK_STAT; 780 ide_set_irq(s->bus); 781 goto eot; 782 } 783 784 /* launch next transfer */ 785 n = s->nsector; 786 s->io_buffer_index = 0; 787 s->io_buffer_size = n * 512; 788 if (s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size) < 512) { 789 /* The PRDs were too short. Reset the Active bit, but don't raise an 790 * interrupt. */ 791 s->status = READY_STAT | SEEK_STAT; 792 dma_buf_commit(s, 0); 793 goto eot; 794 } 795 796 #ifdef DEBUG_AIO 797 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n", 798 sector_num, n, s->dma_cmd); 799 #endif 800 801 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) && 802 !ide_sect_range_ok(s, sector_num, n)) { 803 ide_dma_error(s); 804 block_acct_invalid(blk_get_stats(s->blk), s->acct.type); 805 return; 806 } 807 808 switch (s->dma_cmd) { 809 case IDE_DMA_READ: 810 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, sector_num, 811 ide_dma_cb, s); 812 break; 813 case IDE_DMA_WRITE: 814 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, sector_num, 815 ide_dma_cb, s); 816 break; 817 case IDE_DMA_TRIM: 818 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, sector_num, 819 ide_issue_trim, ide_dma_cb, s, 820 DMA_DIRECTION_TO_DEVICE); 821 break; 822 } 823 return; 824 825 eot: 826 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { 827 block_acct_done(blk_get_stats(s->blk), &s->acct); 828 } 829 ide_set_inactive(s, stay_active); 830 } 831 832 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd) 833 { 834 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; 835 s->io_buffer_size = 0; 836 s->dma_cmd = dma_cmd; 837 838 switch (dma_cmd) { 839 case IDE_DMA_READ: 840 block_acct_start(blk_get_stats(s->blk), &s->acct, 841 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ); 842 break; 843 case IDE_DMA_WRITE: 844 block_acct_start(blk_get_stats(s->blk), &s->acct, 845 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE); 846 break; 847 default: 848 break; 849 } 850 851 ide_start_dma(s, ide_dma_cb); 852 } 853 854 void ide_start_dma(IDEState *s, BlockCompletionFunc *cb) 855 { 856 s->io_buffer_index = 0; 857 s->bus->retry_unit = s->unit; 858 s->bus->retry_sector_num = ide_get_sector(s); 859 s->bus->retry_nsector = s->nsector; 860 if (s->bus->dma->ops->start_dma) { 861 s->bus->dma->ops->start_dma(s->bus->dma, s, cb); 862 } 863 } 864 865 static void ide_sector_write(IDEState *s); 866 867 static void ide_sector_write_timer_cb(void *opaque) 868 { 869 IDEState *s = opaque; 870 ide_set_irq(s->bus); 871 } 872 873 static void ide_sector_write_cb(void *opaque, int ret) 874 { 875 IDEState *s = opaque; 876 int n; 877 878 if (ret == -ECANCELED) { 879 return; 880 } 881 882 s->pio_aiocb = NULL; 883 s->status &= ~BUSY_STAT; 884 885 if (ret != 0) { 886 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) { 887 return; 888 } 889 } 890 891 block_acct_done(blk_get_stats(s->blk), &s->acct); 892 893 n = s->nsector; 894 if (n > s->req_nb_sectors) { 895 n = s->req_nb_sectors; 896 } 897 s->nsector -= n; 898 899 ide_set_sector(s, ide_get_sector(s) + n); 900 if (s->nsector == 0) { 901 /* no more sectors to write */ 902 ide_transfer_stop(s); 903 } else { 904 int n1 = s->nsector; 905 if (n1 > s->req_nb_sectors) { 906 n1 = s->req_nb_sectors; 907 } 908 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE, 909 ide_sector_write); 910 } 911 912 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) { 913 /* It seems there is a bug in the Windows 2000 installer HDD 914 IDE driver which fills the disk with empty logs when the 915 IDE write IRQ comes too early. This hack tries to correct 916 that at the expense of slower write performances. Use this 917 option _only_ to install Windows 2000. You must disable it 918 for normal use. */ 919 timer_mod(s->sector_write_timer, 920 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000)); 921 } else { 922 ide_set_irq(s->bus); 923 } 924 } 925 926 static void ide_sector_write(IDEState *s) 927 { 928 int64_t sector_num; 929 int n; 930 931 s->status = READY_STAT | SEEK_STAT | BUSY_STAT; 932 sector_num = ide_get_sector(s); 933 #if defined(DEBUG_IDE) 934 printf("sector=%" PRId64 "\n", sector_num); 935 #endif 936 n = s->nsector; 937 if (n > s->req_nb_sectors) { 938 n = s->req_nb_sectors; 939 } 940 941 if (!ide_sect_range_ok(s, sector_num, n)) { 942 ide_rw_error(s); 943 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE); 944 return; 945 } 946 947 s->iov.iov_base = s->io_buffer; 948 s->iov.iov_len = n * BDRV_SECTOR_SIZE; 949 qemu_iovec_init_external(&s->qiov, &s->iov, 1); 950 951 block_acct_start(blk_get_stats(s->blk), &s->acct, 952 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE); 953 s->pio_aiocb = blk_aio_writev(s->blk, sector_num, &s->qiov, n, 954 ide_sector_write_cb, s); 955 } 956 957 static void ide_flush_cb(void *opaque, int ret) 958 { 959 IDEState *s = opaque; 960 961 s->pio_aiocb = NULL; 962 963 if (ret == -ECANCELED) { 964 return; 965 } 966 if (ret < 0) { 967 /* XXX: What sector number to set here? */ 968 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) { 969 return; 970 } 971 } 972 973 if (s->blk) { 974 block_acct_done(blk_get_stats(s->blk), &s->acct); 975 } 976 s->status = READY_STAT | SEEK_STAT; 977 ide_cmd_done(s); 978 ide_set_irq(s->bus); 979 } 980 981 static void ide_flush_cache(IDEState *s) 982 { 983 if (s->blk == NULL) { 984 ide_flush_cb(s, 0); 985 return; 986 } 987 988 s->status |= BUSY_STAT; 989 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH); 990 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s); 991 } 992 993 static void ide_cfata_metadata_inquiry(IDEState *s) 994 { 995 uint16_t *p; 996 uint32_t spd; 997 998 p = (uint16_t *) s->io_buffer; 999 memset(p, 0, 0x200); 1000 spd = ((s->mdata_size - 1) >> 9) + 1; 1001 1002 put_le16(p + 0, 0x0001); /* Data format revision */ 1003 put_le16(p + 1, 0x0000); /* Media property: silicon */ 1004 put_le16(p + 2, s->media_changed); /* Media status */ 1005 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */ 1006 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */ 1007 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */ 1008 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */ 1009 } 1010 1011 static void ide_cfata_metadata_read(IDEState *s) 1012 { 1013 uint16_t *p; 1014 1015 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { 1016 s->status = ERR_STAT; 1017 s->error = ABRT_ERR; 1018 return; 1019 } 1020 1021 p = (uint16_t *) s->io_buffer; 1022 memset(p, 0, 0x200); 1023 1024 put_le16(p + 0, s->media_changed); /* Media status */ 1025 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), 1026 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), 1027 s->nsector << 9), 0x200 - 2)); 1028 } 1029 1030 static void ide_cfata_metadata_write(IDEState *s) 1031 { 1032 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { 1033 s->status = ERR_STAT; 1034 s->error = ABRT_ERR; 1035 return; 1036 } 1037 1038 s->media_changed = 0; 1039 1040 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), 1041 s->io_buffer + 2, 1042 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), 1043 s->nsector << 9), 0x200 - 2)); 1044 } 1045 1046 /* called when the inserted state of the media has changed */ 1047 static void ide_cd_change_cb(void *opaque, bool load) 1048 { 1049 IDEState *s = opaque; 1050 uint64_t nb_sectors; 1051 1052 s->tray_open = !load; 1053 blk_get_geometry(s->blk, &nb_sectors); 1054 s->nb_sectors = nb_sectors; 1055 1056 /* 1057 * First indicate to the guest that a CD has been removed. That's 1058 * done on the next command the guest sends us. 1059 * 1060 * Then we set UNIT_ATTENTION, by which the guest will 1061 * detect a new CD in the drive. See ide_atapi_cmd() for details. 1062 */ 1063 s->cdrom_changed = 1; 1064 s->events.new_media = true; 1065 s->events.eject_request = false; 1066 ide_set_irq(s->bus); 1067 } 1068 1069 static void ide_cd_eject_request_cb(void *opaque, bool force) 1070 { 1071 IDEState *s = opaque; 1072 1073 s->events.eject_request = true; 1074 if (force) { 1075 s->tray_locked = false; 1076 } 1077 ide_set_irq(s->bus); 1078 } 1079 1080 static void ide_cmd_lba48_transform(IDEState *s, int lba48) 1081 { 1082 s->lba48 = lba48; 1083 1084 /* handle the 'magic' 0 nsector count conversion here. to avoid 1085 * fiddling with the rest of the read logic, we just store the 1086 * full sector count in ->nsector and ignore ->hob_nsector from now 1087 */ 1088 if (!s->lba48) { 1089 if (!s->nsector) 1090 s->nsector = 256; 1091 } else { 1092 if (!s->nsector && !s->hob_nsector) 1093 s->nsector = 65536; 1094 else { 1095 int lo = s->nsector; 1096 int hi = s->hob_nsector; 1097 1098 s->nsector = (hi << 8) | lo; 1099 } 1100 } 1101 } 1102 1103 static void ide_clear_hob(IDEBus *bus) 1104 { 1105 /* any write clears HOB high bit of device control register */ 1106 bus->ifs[0].select &= ~(1 << 7); 1107 bus->ifs[1].select &= ~(1 << 7); 1108 } 1109 1110 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) 1111 { 1112 IDEBus *bus = opaque; 1113 1114 #ifdef DEBUG_IDE 1115 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val); 1116 #endif 1117 1118 addr &= 7; 1119 1120 /* ignore writes to command block while busy with previous command */ 1121 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT))) 1122 return; 1123 1124 switch(addr) { 1125 case 0: 1126 break; 1127 case 1: 1128 ide_clear_hob(bus); 1129 /* NOTE: data is written to the two drives */ 1130 bus->ifs[0].hob_feature = bus->ifs[0].feature; 1131 bus->ifs[1].hob_feature = bus->ifs[1].feature; 1132 bus->ifs[0].feature = val; 1133 bus->ifs[1].feature = val; 1134 break; 1135 case 2: 1136 ide_clear_hob(bus); 1137 bus->ifs[0].hob_nsector = bus->ifs[0].nsector; 1138 bus->ifs[1].hob_nsector = bus->ifs[1].nsector; 1139 bus->ifs[0].nsector = val; 1140 bus->ifs[1].nsector = val; 1141 break; 1142 case 3: 1143 ide_clear_hob(bus); 1144 bus->ifs[0].hob_sector = bus->ifs[0].sector; 1145 bus->ifs[1].hob_sector = bus->ifs[1].sector; 1146 bus->ifs[0].sector = val; 1147 bus->ifs[1].sector = val; 1148 break; 1149 case 4: 1150 ide_clear_hob(bus); 1151 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl; 1152 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl; 1153 bus->ifs[0].lcyl = val; 1154 bus->ifs[1].lcyl = val; 1155 break; 1156 case 5: 1157 ide_clear_hob(bus); 1158 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl; 1159 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl; 1160 bus->ifs[0].hcyl = val; 1161 bus->ifs[1].hcyl = val; 1162 break; 1163 case 6: 1164 /* FIXME: HOB readback uses bit 7 */ 1165 bus->ifs[0].select = (val & ~0x10) | 0xa0; 1166 bus->ifs[1].select = (val | 0x10) | 0xa0; 1167 /* select drive */ 1168 bus->unit = (val >> 4) & 1; 1169 break; 1170 default: 1171 case 7: 1172 /* command */ 1173 ide_exec_cmd(bus, val); 1174 break; 1175 } 1176 } 1177 1178 static bool cmd_nop(IDEState *s, uint8_t cmd) 1179 { 1180 return true; 1181 } 1182 1183 static bool cmd_data_set_management(IDEState *s, uint8_t cmd) 1184 { 1185 switch (s->feature) { 1186 case DSM_TRIM: 1187 if (s->blk) { 1188 ide_sector_start_dma(s, IDE_DMA_TRIM); 1189 return false; 1190 } 1191 break; 1192 } 1193 1194 ide_abort_command(s); 1195 return true; 1196 } 1197 1198 static bool cmd_identify(IDEState *s, uint8_t cmd) 1199 { 1200 if (s->blk && s->drive_kind != IDE_CD) { 1201 if (s->drive_kind != IDE_CFATA) { 1202 ide_identify(s); 1203 } else { 1204 ide_cfata_identify(s); 1205 } 1206 s->status = READY_STAT | SEEK_STAT; 1207 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); 1208 ide_set_irq(s->bus); 1209 return false; 1210 } else { 1211 if (s->drive_kind == IDE_CD) { 1212 ide_set_signature(s); 1213 } 1214 ide_abort_command(s); 1215 } 1216 1217 return true; 1218 } 1219 1220 static bool cmd_verify(IDEState *s, uint8_t cmd) 1221 { 1222 bool lba48 = (cmd == WIN_VERIFY_EXT); 1223 1224 /* do sector number check ? */ 1225 ide_cmd_lba48_transform(s, lba48); 1226 1227 return true; 1228 } 1229 1230 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd) 1231 { 1232 if (s->drive_kind == IDE_CFATA && s->nsector == 0) { 1233 /* Disable Read and Write Multiple */ 1234 s->mult_sectors = 0; 1235 } else if ((s->nsector & 0xff) != 0 && 1236 ((s->nsector & 0xff) > MAX_MULT_SECTORS || 1237 (s->nsector & (s->nsector - 1)) != 0)) { 1238 ide_abort_command(s); 1239 } else { 1240 s->mult_sectors = s->nsector & 0xff; 1241 } 1242 1243 return true; 1244 } 1245 1246 static bool cmd_read_multiple(IDEState *s, uint8_t cmd) 1247 { 1248 bool lba48 = (cmd == WIN_MULTREAD_EXT); 1249 1250 if (!s->blk || !s->mult_sectors) { 1251 ide_abort_command(s); 1252 return true; 1253 } 1254 1255 ide_cmd_lba48_transform(s, lba48); 1256 s->req_nb_sectors = s->mult_sectors; 1257 ide_sector_read(s); 1258 return false; 1259 } 1260 1261 static bool cmd_write_multiple(IDEState *s, uint8_t cmd) 1262 { 1263 bool lba48 = (cmd == WIN_MULTWRITE_EXT); 1264 int n; 1265 1266 if (!s->blk || !s->mult_sectors) { 1267 ide_abort_command(s); 1268 return true; 1269 } 1270 1271 ide_cmd_lba48_transform(s, lba48); 1272 1273 s->req_nb_sectors = s->mult_sectors; 1274 n = MIN(s->nsector, s->req_nb_sectors); 1275 1276 s->status = SEEK_STAT | READY_STAT; 1277 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write); 1278 1279 s->media_changed = 1; 1280 1281 return false; 1282 } 1283 1284 static bool cmd_read_pio(IDEState *s, uint8_t cmd) 1285 { 1286 bool lba48 = (cmd == WIN_READ_EXT); 1287 1288 if (s->drive_kind == IDE_CD) { 1289 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */ 1290 ide_abort_command(s); 1291 return true; 1292 } 1293 1294 if (!s->blk) { 1295 ide_abort_command(s); 1296 return true; 1297 } 1298 1299 ide_cmd_lba48_transform(s, lba48); 1300 s->req_nb_sectors = 1; 1301 ide_sector_read(s); 1302 1303 return false; 1304 } 1305 1306 static bool cmd_write_pio(IDEState *s, uint8_t cmd) 1307 { 1308 bool lba48 = (cmd == WIN_WRITE_EXT); 1309 1310 if (!s->blk) { 1311 ide_abort_command(s); 1312 return true; 1313 } 1314 1315 ide_cmd_lba48_transform(s, lba48); 1316 1317 s->req_nb_sectors = 1; 1318 s->status = SEEK_STAT | READY_STAT; 1319 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write); 1320 1321 s->media_changed = 1; 1322 1323 return false; 1324 } 1325 1326 static bool cmd_read_dma(IDEState *s, uint8_t cmd) 1327 { 1328 bool lba48 = (cmd == WIN_READDMA_EXT); 1329 1330 if (!s->blk) { 1331 ide_abort_command(s); 1332 return true; 1333 } 1334 1335 ide_cmd_lba48_transform(s, lba48); 1336 ide_sector_start_dma(s, IDE_DMA_READ); 1337 1338 return false; 1339 } 1340 1341 static bool cmd_write_dma(IDEState *s, uint8_t cmd) 1342 { 1343 bool lba48 = (cmd == WIN_WRITEDMA_EXT); 1344 1345 if (!s->blk) { 1346 ide_abort_command(s); 1347 return true; 1348 } 1349 1350 ide_cmd_lba48_transform(s, lba48); 1351 ide_sector_start_dma(s, IDE_DMA_WRITE); 1352 1353 s->media_changed = 1; 1354 1355 return false; 1356 } 1357 1358 static bool cmd_flush_cache(IDEState *s, uint8_t cmd) 1359 { 1360 ide_flush_cache(s); 1361 return false; 1362 } 1363 1364 static bool cmd_seek(IDEState *s, uint8_t cmd) 1365 { 1366 /* XXX: Check that seek is within bounds */ 1367 return true; 1368 } 1369 1370 static bool cmd_read_native_max(IDEState *s, uint8_t cmd) 1371 { 1372 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT); 1373 1374 /* Refuse if no sectors are addressable (e.g. medium not inserted) */ 1375 if (s->nb_sectors == 0) { 1376 ide_abort_command(s); 1377 return true; 1378 } 1379 1380 ide_cmd_lba48_transform(s, lba48); 1381 ide_set_sector(s, s->nb_sectors - 1); 1382 1383 return true; 1384 } 1385 1386 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd) 1387 { 1388 s->nsector = 0xff; /* device active or idle */ 1389 return true; 1390 } 1391 1392 static bool cmd_set_features(IDEState *s, uint8_t cmd) 1393 { 1394 uint16_t *identify_data; 1395 1396 if (!s->blk) { 1397 ide_abort_command(s); 1398 return true; 1399 } 1400 1401 /* XXX: valid for CDROM ? */ 1402 switch (s->feature) { 1403 case 0x02: /* write cache enable */ 1404 blk_set_enable_write_cache(s->blk, true); 1405 identify_data = (uint16_t *)s->identify_data; 1406 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1); 1407 return true; 1408 case 0x82: /* write cache disable */ 1409 blk_set_enable_write_cache(s->blk, false); 1410 identify_data = (uint16_t *)s->identify_data; 1411 put_le16(identify_data + 85, (1 << 14) | 1); 1412 ide_flush_cache(s); 1413 return false; 1414 case 0xcc: /* reverting to power-on defaults enable */ 1415 case 0x66: /* reverting to power-on defaults disable */ 1416 case 0xaa: /* read look-ahead enable */ 1417 case 0x55: /* read look-ahead disable */ 1418 case 0x05: /* set advanced power management mode */ 1419 case 0x85: /* disable advanced power management mode */ 1420 case 0x69: /* NOP */ 1421 case 0x67: /* NOP */ 1422 case 0x96: /* NOP */ 1423 case 0x9a: /* NOP */ 1424 case 0x42: /* enable Automatic Acoustic Mode */ 1425 case 0xc2: /* disable Automatic Acoustic Mode */ 1426 return true; 1427 case 0x03: /* set transfer mode */ 1428 { 1429 uint8_t val = s->nsector & 0x07; 1430 identify_data = (uint16_t *)s->identify_data; 1431 1432 switch (s->nsector >> 3) { 1433 case 0x00: /* pio default */ 1434 case 0x01: /* pio mode */ 1435 put_le16(identify_data + 62, 0x07); 1436 put_le16(identify_data + 63, 0x07); 1437 put_le16(identify_data + 88, 0x3f); 1438 break; 1439 case 0x02: /* sigle word dma mode*/ 1440 put_le16(identify_data + 62, 0x07 | (1 << (val + 8))); 1441 put_le16(identify_data + 63, 0x07); 1442 put_le16(identify_data + 88, 0x3f); 1443 break; 1444 case 0x04: /* mdma mode */ 1445 put_le16(identify_data + 62, 0x07); 1446 put_le16(identify_data + 63, 0x07 | (1 << (val + 8))); 1447 put_le16(identify_data + 88, 0x3f); 1448 break; 1449 case 0x08: /* udma mode */ 1450 put_le16(identify_data + 62, 0x07); 1451 put_le16(identify_data + 63, 0x07); 1452 put_le16(identify_data + 88, 0x3f | (1 << (val + 8))); 1453 break; 1454 default: 1455 goto abort_cmd; 1456 } 1457 return true; 1458 } 1459 } 1460 1461 abort_cmd: 1462 ide_abort_command(s); 1463 return true; 1464 } 1465 1466 1467 /*** ATAPI commands ***/ 1468 1469 static bool cmd_identify_packet(IDEState *s, uint8_t cmd) 1470 { 1471 ide_atapi_identify(s); 1472 s->status = READY_STAT | SEEK_STAT; 1473 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); 1474 ide_set_irq(s->bus); 1475 return false; 1476 } 1477 1478 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd) 1479 { 1480 ide_set_signature(s); 1481 1482 if (s->drive_kind == IDE_CD) { 1483 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet 1484 * devices to return a clear status register 1485 * with READY_STAT *not* set. */ 1486 s->error = 0x01; 1487 } else { 1488 s->status = READY_STAT | SEEK_STAT; 1489 /* The bits of the error register are not as usual for this command! 1490 * They are part of the regular output (this is why ERR_STAT isn't set) 1491 * Device 0 passed, Device 1 passed or not present. */ 1492 s->error = 0x01; 1493 ide_set_irq(s->bus); 1494 } 1495 1496 return false; 1497 } 1498 1499 static bool cmd_device_reset(IDEState *s, uint8_t cmd) 1500 { 1501 ide_set_signature(s); 1502 s->status = 0x00; /* NOTE: READY is _not_ set */ 1503 s->error = 0x01; 1504 1505 return false; 1506 } 1507 1508 static bool cmd_packet(IDEState *s, uint8_t cmd) 1509 { 1510 /* overlapping commands not supported */ 1511 if (s->feature & 0x02) { 1512 ide_abort_command(s); 1513 return true; 1514 } 1515 1516 s->status = READY_STAT | SEEK_STAT; 1517 s->atapi_dma = s->feature & 1; 1518 s->nsector = 1; 1519 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, 1520 ide_atapi_cmd); 1521 return false; 1522 } 1523 1524 1525 /*** CF-ATA commands ***/ 1526 1527 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd) 1528 { 1529 s->error = 0x09; /* miscellaneous error */ 1530 s->status = READY_STAT | SEEK_STAT; 1531 ide_set_irq(s->bus); 1532 1533 return false; 1534 } 1535 1536 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd) 1537 { 1538 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is 1539 * required for Windows 8 to work with AHCI */ 1540 1541 if (cmd == CFA_WEAR_LEVEL) { 1542 s->nsector = 0; 1543 } 1544 1545 if (cmd == CFA_ERASE_SECTORS) { 1546 s->media_changed = 1; 1547 } 1548 1549 return true; 1550 } 1551 1552 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd) 1553 { 1554 s->status = READY_STAT | SEEK_STAT; 1555 1556 memset(s->io_buffer, 0, 0x200); 1557 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */ 1558 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */ 1559 s->io_buffer[0x02] = s->select; /* Head */ 1560 s->io_buffer[0x03] = s->sector; /* Sector */ 1561 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */ 1562 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */ 1563 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */ 1564 s->io_buffer[0x13] = 0x00; /* Erase flag */ 1565 s->io_buffer[0x18] = 0x00; /* Hot count */ 1566 s->io_buffer[0x19] = 0x00; /* Hot count */ 1567 s->io_buffer[0x1a] = 0x01; /* Hot count */ 1568 1569 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1570 ide_set_irq(s->bus); 1571 1572 return false; 1573 } 1574 1575 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd) 1576 { 1577 switch (s->feature) { 1578 case 0x02: /* Inquiry Metadata Storage */ 1579 ide_cfata_metadata_inquiry(s); 1580 break; 1581 case 0x03: /* Read Metadata Storage */ 1582 ide_cfata_metadata_read(s); 1583 break; 1584 case 0x04: /* Write Metadata Storage */ 1585 ide_cfata_metadata_write(s); 1586 break; 1587 default: 1588 ide_abort_command(s); 1589 return true; 1590 } 1591 1592 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1593 s->status = 0x00; /* NOTE: READY is _not_ set */ 1594 ide_set_irq(s->bus); 1595 1596 return false; 1597 } 1598 1599 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd) 1600 { 1601 switch (s->feature) { 1602 case 0x01: /* sense temperature in device */ 1603 s->nsector = 0x50; /* +20 C */ 1604 break; 1605 default: 1606 ide_abort_command(s); 1607 return true; 1608 } 1609 1610 return true; 1611 } 1612 1613 1614 /*** SMART commands ***/ 1615 1616 static bool cmd_smart(IDEState *s, uint8_t cmd) 1617 { 1618 int n; 1619 1620 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) { 1621 goto abort_cmd; 1622 } 1623 1624 if (!s->smart_enabled && s->feature != SMART_ENABLE) { 1625 goto abort_cmd; 1626 } 1627 1628 switch (s->feature) { 1629 case SMART_DISABLE: 1630 s->smart_enabled = 0; 1631 return true; 1632 1633 case SMART_ENABLE: 1634 s->smart_enabled = 1; 1635 return true; 1636 1637 case SMART_ATTR_AUTOSAVE: 1638 switch (s->sector) { 1639 case 0x00: 1640 s->smart_autosave = 0; 1641 break; 1642 case 0xf1: 1643 s->smart_autosave = 1; 1644 break; 1645 default: 1646 goto abort_cmd; 1647 } 1648 return true; 1649 1650 case SMART_STATUS: 1651 if (!s->smart_errors) { 1652 s->hcyl = 0xc2; 1653 s->lcyl = 0x4f; 1654 } else { 1655 s->hcyl = 0x2c; 1656 s->lcyl = 0xf4; 1657 } 1658 return true; 1659 1660 case SMART_READ_THRESH: 1661 memset(s->io_buffer, 0, 0x200); 1662 s->io_buffer[0] = 0x01; /* smart struct version */ 1663 1664 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) { 1665 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0]; 1666 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11]; 1667 } 1668 1669 /* checksum */ 1670 for (n = 0; n < 511; n++) { 1671 s->io_buffer[511] += s->io_buffer[n]; 1672 } 1673 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1674 1675 s->status = READY_STAT | SEEK_STAT; 1676 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1677 ide_set_irq(s->bus); 1678 return false; 1679 1680 case SMART_READ_DATA: 1681 memset(s->io_buffer, 0, 0x200); 1682 s->io_buffer[0] = 0x01; /* smart struct version */ 1683 1684 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) { 1685 int i; 1686 for (i = 0; i < 11; i++) { 1687 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i]; 1688 } 1689 } 1690 1691 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00); 1692 if (s->smart_selftest_count == 0) { 1693 s->io_buffer[363] = 0; 1694 } else { 1695 s->io_buffer[363] = 1696 s->smart_selftest_data[3 + 1697 (s->smart_selftest_count - 1) * 1698 24]; 1699 } 1700 s->io_buffer[364] = 0x20; 1701 s->io_buffer[365] = 0x01; 1702 /* offline data collection capacity: execute + self-test*/ 1703 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1); 1704 s->io_buffer[368] = 0x03; /* smart capability (1) */ 1705 s->io_buffer[369] = 0x00; /* smart capability (2) */ 1706 s->io_buffer[370] = 0x01; /* error logging supported */ 1707 s->io_buffer[372] = 0x02; /* minutes for poll short test */ 1708 s->io_buffer[373] = 0x36; /* minutes for poll ext test */ 1709 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */ 1710 1711 for (n = 0; n < 511; n++) { 1712 s->io_buffer[511] += s->io_buffer[n]; 1713 } 1714 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1715 1716 s->status = READY_STAT | SEEK_STAT; 1717 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1718 ide_set_irq(s->bus); 1719 return false; 1720 1721 case SMART_READ_LOG: 1722 switch (s->sector) { 1723 case 0x01: /* summary smart error log */ 1724 memset(s->io_buffer, 0, 0x200); 1725 s->io_buffer[0] = 0x01; 1726 s->io_buffer[1] = 0x00; /* no error entries */ 1727 s->io_buffer[452] = s->smart_errors & 0xff; 1728 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8; 1729 1730 for (n = 0; n < 511; n++) { 1731 s->io_buffer[511] += s->io_buffer[n]; 1732 } 1733 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1734 break; 1735 case 0x06: /* smart self test log */ 1736 memset(s->io_buffer, 0, 0x200); 1737 s->io_buffer[0] = 0x01; 1738 if (s->smart_selftest_count == 0) { 1739 s->io_buffer[508] = 0; 1740 } else { 1741 s->io_buffer[508] = s->smart_selftest_count; 1742 for (n = 2; n < 506; n++) { 1743 s->io_buffer[n] = s->smart_selftest_data[n]; 1744 } 1745 } 1746 1747 for (n = 0; n < 511; n++) { 1748 s->io_buffer[511] += s->io_buffer[n]; 1749 } 1750 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1751 break; 1752 default: 1753 goto abort_cmd; 1754 } 1755 s->status = READY_STAT | SEEK_STAT; 1756 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1757 ide_set_irq(s->bus); 1758 return false; 1759 1760 case SMART_EXECUTE_OFFLINE: 1761 switch (s->sector) { 1762 case 0: /* off-line routine */ 1763 case 1: /* short self test */ 1764 case 2: /* extended self test */ 1765 s->smart_selftest_count++; 1766 if (s->smart_selftest_count > 21) { 1767 s->smart_selftest_count = 1; 1768 } 1769 n = 2 + (s->smart_selftest_count - 1) * 24; 1770 s->smart_selftest_data[n] = s->sector; 1771 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */ 1772 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */ 1773 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */ 1774 break; 1775 default: 1776 goto abort_cmd; 1777 } 1778 return true; 1779 } 1780 1781 abort_cmd: 1782 ide_abort_command(s); 1783 return true; 1784 } 1785 1786 #define HD_OK (1u << IDE_HD) 1787 #define CD_OK (1u << IDE_CD) 1788 #define CFA_OK (1u << IDE_CFATA) 1789 #define HD_CFA_OK (HD_OK | CFA_OK) 1790 #define ALL_OK (HD_OK | CD_OK | CFA_OK) 1791 1792 /* Set the Disk Seek Completed status bit during completion */ 1793 #define SET_DSC (1u << 8) 1794 1795 /* See ACS-2 T13/2015-D Table B.2 Command codes */ 1796 static const struct { 1797 /* Returns true if the completion code should be run */ 1798 bool (*handler)(IDEState *s, uint8_t cmd); 1799 int flags; 1800 } ide_cmd_table[0x100] = { 1801 /* NOP not implemented, mandatory for CD */ 1802 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK }, 1803 [WIN_DSM] = { cmd_data_set_management, HD_CFA_OK }, 1804 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK }, 1805 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC}, 1806 [WIN_READ] = { cmd_read_pio, ALL_OK }, 1807 [WIN_READ_ONCE] = { cmd_read_pio, HD_CFA_OK }, 1808 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK }, 1809 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK }, 1810 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC }, 1811 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK }, 1812 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK }, 1813 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK }, 1814 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK }, 1815 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK }, 1816 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK }, 1817 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK }, 1818 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK }, 1819 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1820 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1821 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1822 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC }, 1823 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK }, 1824 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK }, 1825 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC }, 1826 [WIN_STANDBYNOW2] = { cmd_nop, HD_CFA_OK }, 1827 [WIN_IDLEIMMEDIATE2] = { cmd_nop, HD_CFA_OK }, 1828 [WIN_STANDBY2] = { cmd_nop, HD_CFA_OK }, 1829 [WIN_SETIDLE2] = { cmd_nop, HD_CFA_OK }, 1830 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC }, 1831 [WIN_SLEEPNOW2] = { cmd_nop, HD_CFA_OK }, 1832 [WIN_PACKETCMD] = { cmd_packet, CD_OK }, 1833 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK }, 1834 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC }, 1835 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK }, 1836 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC }, 1837 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK }, 1838 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK }, 1839 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC }, 1840 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK }, 1841 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK }, 1842 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK }, 1843 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK }, 1844 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK }, 1845 [WIN_STANDBYNOW1] = { cmd_nop, HD_CFA_OK }, 1846 [WIN_IDLEIMMEDIATE] = { cmd_nop, HD_CFA_OK }, 1847 [WIN_STANDBY] = { cmd_nop, HD_CFA_OK }, 1848 [WIN_SETIDLE1] = { cmd_nop, HD_CFA_OK }, 1849 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC }, 1850 [WIN_SLEEPNOW1] = { cmd_nop, HD_CFA_OK }, 1851 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK }, 1852 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK }, 1853 [WIN_IDENTIFY] = { cmd_identify, ALL_OK }, 1854 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC }, 1855 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC }, 1856 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC }, 1857 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, HD_CFA_OK | SET_DSC }, 1858 }; 1859 1860 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd) 1861 { 1862 return cmd < ARRAY_SIZE(ide_cmd_table) 1863 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind)); 1864 } 1865 1866 void ide_exec_cmd(IDEBus *bus, uint32_t val) 1867 { 1868 IDEState *s; 1869 bool complete; 1870 1871 #if defined(DEBUG_IDE) 1872 printf("ide: CMD=%02x\n", val); 1873 #endif 1874 s = idebus_active_if(bus); 1875 /* ignore commands to non existent slave */ 1876 if (s != bus->ifs && !s->blk) { 1877 return; 1878 } 1879 1880 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */ 1881 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET) 1882 return; 1883 1884 if (!ide_cmd_permitted(s, val)) { 1885 ide_abort_command(s); 1886 ide_set_irq(s->bus); 1887 return; 1888 } 1889 1890 s->status = READY_STAT | BUSY_STAT; 1891 s->error = 0; 1892 s->io_buffer_offset = 0; 1893 1894 complete = ide_cmd_table[val].handler(s, val); 1895 if (complete) { 1896 s->status &= ~BUSY_STAT; 1897 assert(!!s->error == !!(s->status & ERR_STAT)); 1898 1899 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) { 1900 s->status |= SEEK_STAT; 1901 } 1902 1903 ide_cmd_done(s); 1904 ide_set_irq(s->bus); 1905 } 1906 } 1907 1908 uint32_t ide_ioport_read(void *opaque, uint32_t addr1) 1909 { 1910 IDEBus *bus = opaque; 1911 IDEState *s = idebus_active_if(bus); 1912 uint32_t addr; 1913 int ret, hob; 1914 1915 addr = addr1 & 7; 1916 /* FIXME: HOB readback uses bit 7, but it's always set right now */ 1917 //hob = s->select & (1 << 7); 1918 hob = 0; 1919 switch(addr) { 1920 case 0: 1921 ret = 0xff; 1922 break; 1923 case 1: 1924 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) || 1925 (s != bus->ifs && !s->blk)) { 1926 ret = 0; 1927 } else if (!hob) { 1928 ret = s->error; 1929 } else { 1930 ret = s->hob_feature; 1931 } 1932 break; 1933 case 2: 1934 if (!bus->ifs[0].blk && !bus->ifs[1].blk) { 1935 ret = 0; 1936 } else if (!hob) { 1937 ret = s->nsector & 0xff; 1938 } else { 1939 ret = s->hob_nsector; 1940 } 1941 break; 1942 case 3: 1943 if (!bus->ifs[0].blk && !bus->ifs[1].blk) { 1944 ret = 0; 1945 } else if (!hob) { 1946 ret = s->sector; 1947 } else { 1948 ret = s->hob_sector; 1949 } 1950 break; 1951 case 4: 1952 if (!bus->ifs[0].blk && !bus->ifs[1].blk) { 1953 ret = 0; 1954 } else if (!hob) { 1955 ret = s->lcyl; 1956 } else { 1957 ret = s->hob_lcyl; 1958 } 1959 break; 1960 case 5: 1961 if (!bus->ifs[0].blk && !bus->ifs[1].blk) { 1962 ret = 0; 1963 } else if (!hob) { 1964 ret = s->hcyl; 1965 } else { 1966 ret = s->hob_hcyl; 1967 } 1968 break; 1969 case 6: 1970 if (!bus->ifs[0].blk && !bus->ifs[1].blk) { 1971 ret = 0; 1972 } else { 1973 ret = s->select; 1974 } 1975 break; 1976 default: 1977 case 7: 1978 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) || 1979 (s != bus->ifs && !s->blk)) { 1980 ret = 0; 1981 } else { 1982 ret = s->status; 1983 } 1984 qemu_irq_lower(bus->irq); 1985 break; 1986 } 1987 #ifdef DEBUG_IDE 1988 printf("ide: read addr=0x%x val=%02x\n", addr1, ret); 1989 #endif 1990 return ret; 1991 } 1992 1993 uint32_t ide_status_read(void *opaque, uint32_t addr) 1994 { 1995 IDEBus *bus = opaque; 1996 IDEState *s = idebus_active_if(bus); 1997 int ret; 1998 1999 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) || 2000 (s != bus->ifs && !s->blk)) { 2001 ret = 0; 2002 } else { 2003 ret = s->status; 2004 } 2005 #ifdef DEBUG_IDE 2006 printf("ide: read status addr=0x%x val=%02x\n", addr, ret); 2007 #endif 2008 return ret; 2009 } 2010 2011 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) 2012 { 2013 IDEBus *bus = opaque; 2014 IDEState *s; 2015 int i; 2016 2017 #ifdef DEBUG_IDE 2018 printf("ide: write control addr=0x%x val=%02x\n", addr, val); 2019 #endif 2020 /* common for both drives */ 2021 if (!(bus->cmd & IDE_CMD_RESET) && 2022 (val & IDE_CMD_RESET)) { 2023 /* reset low to high */ 2024 for(i = 0;i < 2; i++) { 2025 s = &bus->ifs[i]; 2026 s->status = BUSY_STAT | SEEK_STAT; 2027 s->error = 0x01; 2028 } 2029 } else if ((bus->cmd & IDE_CMD_RESET) && 2030 !(val & IDE_CMD_RESET)) { 2031 /* high to low */ 2032 for(i = 0;i < 2; i++) { 2033 s = &bus->ifs[i]; 2034 if (s->drive_kind == IDE_CD) 2035 s->status = 0x00; /* NOTE: READY is _not_ set */ 2036 else 2037 s->status = READY_STAT | SEEK_STAT; 2038 ide_set_signature(s); 2039 } 2040 } 2041 2042 bus->cmd = val; 2043 } 2044 2045 /* 2046 * Returns true if the running PIO transfer is a PIO out (i.e. data is 2047 * transferred from the device to the guest), false if it's a PIO in 2048 */ 2049 static bool ide_is_pio_out(IDEState *s) 2050 { 2051 if (s->end_transfer_func == ide_sector_write || 2052 s->end_transfer_func == ide_atapi_cmd) { 2053 return false; 2054 } else if (s->end_transfer_func == ide_sector_read || 2055 s->end_transfer_func == ide_transfer_stop || 2056 s->end_transfer_func == ide_atapi_cmd_reply_end || 2057 s->end_transfer_func == ide_dummy_transfer_stop) { 2058 return true; 2059 } 2060 2061 abort(); 2062 } 2063 2064 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val) 2065 { 2066 IDEBus *bus = opaque; 2067 IDEState *s = idebus_active_if(bus); 2068 uint8_t *p; 2069 2070 /* PIO data access allowed only when DRQ bit is set. The result of a write 2071 * during PIO out is indeterminate, just ignore it. */ 2072 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { 2073 return; 2074 } 2075 2076 p = s->data_ptr; 2077 if (p + 2 > s->data_end) { 2078 return; 2079 } 2080 2081 *(uint16_t *)p = le16_to_cpu(val); 2082 p += 2; 2083 s->data_ptr = p; 2084 if (p >= s->data_end) { 2085 s->status &= ~DRQ_STAT; 2086 s->end_transfer_func(s); 2087 } 2088 } 2089 2090 uint32_t ide_data_readw(void *opaque, uint32_t addr) 2091 { 2092 IDEBus *bus = opaque; 2093 IDEState *s = idebus_active_if(bus); 2094 uint8_t *p; 2095 int ret; 2096 2097 /* PIO data access allowed only when DRQ bit is set. The result of a read 2098 * during PIO in is indeterminate, return 0 and don't move forward. */ 2099 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { 2100 return 0; 2101 } 2102 2103 p = s->data_ptr; 2104 if (p + 2 > s->data_end) { 2105 return 0; 2106 } 2107 2108 ret = cpu_to_le16(*(uint16_t *)p); 2109 p += 2; 2110 s->data_ptr = p; 2111 if (p >= s->data_end) { 2112 s->status &= ~DRQ_STAT; 2113 s->end_transfer_func(s); 2114 } 2115 return ret; 2116 } 2117 2118 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val) 2119 { 2120 IDEBus *bus = opaque; 2121 IDEState *s = idebus_active_if(bus); 2122 uint8_t *p; 2123 2124 /* PIO data access allowed only when DRQ bit is set. The result of a write 2125 * during PIO out is indeterminate, just ignore it. */ 2126 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { 2127 return; 2128 } 2129 2130 p = s->data_ptr; 2131 if (p + 4 > s->data_end) { 2132 return; 2133 } 2134 2135 *(uint32_t *)p = le32_to_cpu(val); 2136 p += 4; 2137 s->data_ptr = p; 2138 if (p >= s->data_end) { 2139 s->status &= ~DRQ_STAT; 2140 s->end_transfer_func(s); 2141 } 2142 } 2143 2144 uint32_t ide_data_readl(void *opaque, uint32_t addr) 2145 { 2146 IDEBus *bus = opaque; 2147 IDEState *s = idebus_active_if(bus); 2148 uint8_t *p; 2149 int ret; 2150 2151 /* PIO data access allowed only when DRQ bit is set. The result of a read 2152 * during PIO in is indeterminate, return 0 and don't move forward. */ 2153 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { 2154 return 0; 2155 } 2156 2157 p = s->data_ptr; 2158 if (p + 4 > s->data_end) { 2159 return 0; 2160 } 2161 2162 ret = cpu_to_le32(*(uint32_t *)p); 2163 p += 4; 2164 s->data_ptr = p; 2165 if (p >= s->data_end) { 2166 s->status &= ~DRQ_STAT; 2167 s->end_transfer_func(s); 2168 } 2169 return ret; 2170 } 2171 2172 static void ide_dummy_transfer_stop(IDEState *s) 2173 { 2174 s->data_ptr = s->io_buffer; 2175 s->data_end = s->io_buffer; 2176 s->io_buffer[0] = 0xff; 2177 s->io_buffer[1] = 0xff; 2178 s->io_buffer[2] = 0xff; 2179 s->io_buffer[3] = 0xff; 2180 } 2181 2182 static void ide_reset(IDEState *s) 2183 { 2184 #ifdef DEBUG_IDE 2185 printf("ide: reset\n"); 2186 #endif 2187 2188 if (s->pio_aiocb) { 2189 blk_aio_cancel(s->pio_aiocb); 2190 s->pio_aiocb = NULL; 2191 } 2192 2193 if (s->drive_kind == IDE_CFATA) 2194 s->mult_sectors = 0; 2195 else 2196 s->mult_sectors = MAX_MULT_SECTORS; 2197 /* ide regs */ 2198 s->feature = 0; 2199 s->error = 0; 2200 s->nsector = 0; 2201 s->sector = 0; 2202 s->lcyl = 0; 2203 s->hcyl = 0; 2204 2205 /* lba48 */ 2206 s->hob_feature = 0; 2207 s->hob_sector = 0; 2208 s->hob_nsector = 0; 2209 s->hob_lcyl = 0; 2210 s->hob_hcyl = 0; 2211 2212 s->select = 0xa0; 2213 s->status = READY_STAT | SEEK_STAT; 2214 2215 s->lba48 = 0; 2216 2217 /* ATAPI specific */ 2218 s->sense_key = 0; 2219 s->asc = 0; 2220 s->cdrom_changed = 0; 2221 s->packet_transfer_size = 0; 2222 s->elementary_transfer_size = 0; 2223 s->io_buffer_index = 0; 2224 s->cd_sector_size = 0; 2225 s->atapi_dma = 0; 2226 s->tray_locked = 0; 2227 s->tray_open = 0; 2228 /* ATA DMA state */ 2229 s->io_buffer_size = 0; 2230 s->req_nb_sectors = 0; 2231 2232 ide_set_signature(s); 2233 /* init the transfer handler so that 0xffff is returned on data 2234 accesses */ 2235 s->end_transfer_func = ide_dummy_transfer_stop; 2236 ide_dummy_transfer_stop(s); 2237 s->media_changed = 0; 2238 } 2239 2240 void ide_bus_reset(IDEBus *bus) 2241 { 2242 bus->unit = 0; 2243 bus->cmd = 0; 2244 ide_reset(&bus->ifs[0]); 2245 ide_reset(&bus->ifs[1]); 2246 ide_clear_hob(bus); 2247 2248 /* pending async DMA */ 2249 if (bus->dma->aiocb) { 2250 #ifdef DEBUG_AIO 2251 printf("aio_cancel\n"); 2252 #endif 2253 blk_aio_cancel(bus->dma->aiocb); 2254 bus->dma->aiocb = NULL; 2255 } 2256 2257 /* reset dma provider too */ 2258 if (bus->dma->ops->reset) { 2259 bus->dma->ops->reset(bus->dma); 2260 } 2261 } 2262 2263 static bool ide_cd_is_tray_open(void *opaque) 2264 { 2265 return ((IDEState *)opaque)->tray_open; 2266 } 2267 2268 static bool ide_cd_is_medium_locked(void *opaque) 2269 { 2270 return ((IDEState *)opaque)->tray_locked; 2271 } 2272 2273 static void ide_resize_cb(void *opaque) 2274 { 2275 IDEState *s = opaque; 2276 uint64_t nb_sectors; 2277 2278 if (!s->identify_set) { 2279 return; 2280 } 2281 2282 blk_get_geometry(s->blk, &nb_sectors); 2283 s->nb_sectors = nb_sectors; 2284 2285 /* Update the identify data buffer. */ 2286 if (s->drive_kind == IDE_CFATA) { 2287 ide_cfata_identify_size(s); 2288 } else { 2289 /* IDE_CD uses a different set of callbacks entirely. */ 2290 assert(s->drive_kind != IDE_CD); 2291 ide_identify_size(s); 2292 } 2293 } 2294 2295 static const BlockDevOps ide_cd_block_ops = { 2296 .change_media_cb = ide_cd_change_cb, 2297 .eject_request_cb = ide_cd_eject_request_cb, 2298 .is_tray_open = ide_cd_is_tray_open, 2299 .is_medium_locked = ide_cd_is_medium_locked, 2300 }; 2301 2302 static const BlockDevOps ide_hd_block_ops = { 2303 .resize_cb = ide_resize_cb, 2304 }; 2305 2306 int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind, 2307 const char *version, const char *serial, const char *model, 2308 uint64_t wwn, 2309 uint32_t cylinders, uint32_t heads, uint32_t secs, 2310 int chs_trans) 2311 { 2312 uint64_t nb_sectors; 2313 2314 s->blk = blk; 2315 s->drive_kind = kind; 2316 2317 blk_get_geometry(blk, &nb_sectors); 2318 s->cylinders = cylinders; 2319 s->heads = heads; 2320 s->sectors = secs; 2321 s->chs_trans = chs_trans; 2322 s->nb_sectors = nb_sectors; 2323 s->wwn = wwn; 2324 /* The SMART values should be preserved across power cycles 2325 but they aren't. */ 2326 s->smart_enabled = 1; 2327 s->smart_autosave = 1; 2328 s->smart_errors = 0; 2329 s->smart_selftest_count = 0; 2330 if (kind == IDE_CD) { 2331 blk_set_dev_ops(blk, &ide_cd_block_ops, s); 2332 blk_set_guest_block_size(blk, 2048); 2333 } else { 2334 if (!blk_is_inserted(s->blk)) { 2335 error_report("Device needs media, but drive is empty"); 2336 return -1; 2337 } 2338 if (blk_is_read_only(blk)) { 2339 error_report("Can't use a read-only drive"); 2340 return -1; 2341 } 2342 blk_set_dev_ops(blk, &ide_hd_block_ops, s); 2343 } 2344 if (serial) { 2345 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial); 2346 } else { 2347 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str), 2348 "QM%05d", s->drive_serial); 2349 } 2350 if (model) { 2351 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model); 2352 } else { 2353 switch (kind) { 2354 case IDE_CD: 2355 strcpy(s->drive_model_str, "QEMU DVD-ROM"); 2356 break; 2357 case IDE_CFATA: 2358 strcpy(s->drive_model_str, "QEMU MICRODRIVE"); 2359 break; 2360 default: 2361 strcpy(s->drive_model_str, "QEMU HARDDISK"); 2362 break; 2363 } 2364 } 2365 2366 if (version) { 2367 pstrcpy(s->version, sizeof(s->version), version); 2368 } else { 2369 pstrcpy(s->version, sizeof(s->version), qemu_hw_version()); 2370 } 2371 2372 ide_reset(s); 2373 blk_iostatus_enable(blk); 2374 return 0; 2375 } 2376 2377 static void ide_init1(IDEBus *bus, int unit) 2378 { 2379 static int drive_serial = 1; 2380 IDEState *s = &bus->ifs[unit]; 2381 2382 s->bus = bus; 2383 s->unit = unit; 2384 s->drive_serial = drive_serial++; 2385 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */ 2386 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; 2387 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len); 2388 memset(s->io_buffer, 0, s->io_buffer_total_len); 2389 2390 s->smart_selftest_data = blk_blockalign(s->blk, 512); 2391 memset(s->smart_selftest_data, 0, 512); 2392 2393 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2394 ide_sector_write_timer_cb, s); 2395 } 2396 2397 static int ide_nop_int(IDEDMA *dma, int x) 2398 { 2399 return 0; 2400 } 2401 2402 static void ide_nop(IDEDMA *dma) 2403 { 2404 } 2405 2406 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l) 2407 { 2408 return 0; 2409 } 2410 2411 static const IDEDMAOps ide_dma_nop_ops = { 2412 .prepare_buf = ide_nop_int32, 2413 .restart_dma = ide_nop, 2414 .rw_buf = ide_nop_int, 2415 }; 2416 2417 static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd) 2418 { 2419 s->unit = s->bus->retry_unit; 2420 ide_set_sector(s, s->bus->retry_sector_num); 2421 s->nsector = s->bus->retry_nsector; 2422 s->bus->dma->ops->restart_dma(s->bus->dma); 2423 s->io_buffer_size = 0; 2424 s->dma_cmd = dma_cmd; 2425 ide_start_dma(s, ide_dma_cb); 2426 } 2427 2428 static void ide_restart_bh(void *opaque) 2429 { 2430 IDEBus *bus = opaque; 2431 IDEState *s; 2432 bool is_read; 2433 int error_status; 2434 2435 qemu_bh_delete(bus->bh); 2436 bus->bh = NULL; 2437 2438 error_status = bus->error_status; 2439 if (bus->error_status == 0) { 2440 return; 2441 } 2442 2443 s = idebus_active_if(bus); 2444 is_read = (bus->error_status & IDE_RETRY_READ) != 0; 2445 2446 /* The error status must be cleared before resubmitting the request: The 2447 * request may fail again, and this case can only be distinguished if the 2448 * called function can set a new error status. */ 2449 bus->error_status = 0; 2450 2451 /* The HBA has generically asked to be kicked on retry */ 2452 if (error_status & IDE_RETRY_HBA) { 2453 if (s->bus->dma->ops->restart) { 2454 s->bus->dma->ops->restart(s->bus->dma); 2455 } 2456 } 2457 2458 if (error_status & IDE_RETRY_DMA) { 2459 if (error_status & IDE_RETRY_TRIM) { 2460 ide_restart_dma(s, IDE_DMA_TRIM); 2461 } else { 2462 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE); 2463 } 2464 } else if (error_status & IDE_RETRY_PIO) { 2465 if (is_read) { 2466 ide_sector_read(s); 2467 } else { 2468 ide_sector_write(s); 2469 } 2470 } else if (error_status & IDE_RETRY_FLUSH) { 2471 ide_flush_cache(s); 2472 } else { 2473 /* 2474 * We've not got any bits to tell us about ATAPI - but 2475 * we do have the end_transfer_func that tells us what 2476 * we're trying to do. 2477 */ 2478 if (s->end_transfer_func == ide_atapi_cmd) { 2479 ide_atapi_dma_restart(s); 2480 } 2481 } 2482 } 2483 2484 static void ide_restart_cb(void *opaque, int running, RunState state) 2485 { 2486 IDEBus *bus = opaque; 2487 2488 if (!running) 2489 return; 2490 2491 if (!bus->bh) { 2492 bus->bh = qemu_bh_new(ide_restart_bh, bus); 2493 qemu_bh_schedule(bus->bh); 2494 } 2495 } 2496 2497 void ide_register_restart_cb(IDEBus *bus) 2498 { 2499 if (bus->dma->ops->restart_dma) { 2500 qemu_add_vm_change_state_handler(ide_restart_cb, bus); 2501 } 2502 } 2503 2504 static IDEDMA ide_dma_nop = { 2505 .ops = &ide_dma_nop_ops, 2506 .aiocb = NULL, 2507 }; 2508 2509 void ide_init2(IDEBus *bus, qemu_irq irq) 2510 { 2511 int i; 2512 2513 for(i = 0; i < 2; i++) { 2514 ide_init1(bus, i); 2515 ide_reset(&bus->ifs[i]); 2516 } 2517 bus->irq = irq; 2518 bus->dma = &ide_dma_nop; 2519 } 2520 2521 static const MemoryRegionPortio ide_portio_list[] = { 2522 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write }, 2523 { 0, 1, 2, .read = ide_data_readw, .write = ide_data_writew }, 2524 { 0, 1, 4, .read = ide_data_readl, .write = ide_data_writel }, 2525 PORTIO_END_OF_LIST(), 2526 }; 2527 2528 static const MemoryRegionPortio ide_portio2_list[] = { 2529 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write }, 2530 PORTIO_END_OF_LIST(), 2531 }; 2532 2533 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2) 2534 { 2535 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA 2536 bridge has been setup properly to always register with ISA. */ 2537 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide"); 2538 2539 if (iobase2) { 2540 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide"); 2541 } 2542 } 2543 2544 static bool is_identify_set(void *opaque, int version_id) 2545 { 2546 IDEState *s = opaque; 2547 2548 return s->identify_set != 0; 2549 } 2550 2551 static EndTransferFunc* transfer_end_table[] = { 2552 ide_sector_read, 2553 ide_sector_write, 2554 ide_transfer_stop, 2555 ide_atapi_cmd_reply_end, 2556 ide_atapi_cmd, 2557 ide_dummy_transfer_stop, 2558 }; 2559 2560 static int transfer_end_table_idx(EndTransferFunc *fn) 2561 { 2562 int i; 2563 2564 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++) 2565 if (transfer_end_table[i] == fn) 2566 return i; 2567 2568 return -1; 2569 } 2570 2571 static int ide_drive_post_load(void *opaque, int version_id) 2572 { 2573 IDEState *s = opaque; 2574 2575 if (s->blk && s->identify_set) { 2576 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5))); 2577 } 2578 return 0; 2579 } 2580 2581 static int ide_drive_pio_post_load(void *opaque, int version_id) 2582 { 2583 IDEState *s = opaque; 2584 2585 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) { 2586 return -EINVAL; 2587 } 2588 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx]; 2589 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset; 2590 s->data_end = s->data_ptr + s->cur_io_buffer_len; 2591 s->atapi_dma = s->feature & 1; /* as per cmd_packet */ 2592 2593 return 0; 2594 } 2595 2596 static void ide_drive_pio_pre_save(void *opaque) 2597 { 2598 IDEState *s = opaque; 2599 int idx; 2600 2601 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer; 2602 s->cur_io_buffer_len = s->data_end - s->data_ptr; 2603 2604 idx = transfer_end_table_idx(s->end_transfer_func); 2605 if (idx == -1) { 2606 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n", 2607 __func__); 2608 s->end_transfer_fn_idx = 2; 2609 } else { 2610 s->end_transfer_fn_idx = idx; 2611 } 2612 } 2613 2614 static bool ide_drive_pio_state_needed(void *opaque) 2615 { 2616 IDEState *s = opaque; 2617 2618 return ((s->status & DRQ_STAT) != 0) 2619 || (s->bus->error_status & IDE_RETRY_PIO); 2620 } 2621 2622 static bool ide_tray_state_needed(void *opaque) 2623 { 2624 IDEState *s = opaque; 2625 2626 return s->tray_open || s->tray_locked; 2627 } 2628 2629 static bool ide_atapi_gesn_needed(void *opaque) 2630 { 2631 IDEState *s = opaque; 2632 2633 return s->events.new_media || s->events.eject_request; 2634 } 2635 2636 static bool ide_error_needed(void *opaque) 2637 { 2638 IDEBus *bus = opaque; 2639 2640 return (bus->error_status != 0); 2641 } 2642 2643 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */ 2644 static const VMStateDescription vmstate_ide_atapi_gesn_state = { 2645 .name ="ide_drive/atapi/gesn_state", 2646 .version_id = 1, 2647 .minimum_version_id = 1, 2648 .needed = ide_atapi_gesn_needed, 2649 .fields = (VMStateField[]) { 2650 VMSTATE_BOOL(events.new_media, IDEState), 2651 VMSTATE_BOOL(events.eject_request, IDEState), 2652 VMSTATE_END_OF_LIST() 2653 } 2654 }; 2655 2656 static const VMStateDescription vmstate_ide_tray_state = { 2657 .name = "ide_drive/tray_state", 2658 .version_id = 1, 2659 .minimum_version_id = 1, 2660 .needed = ide_tray_state_needed, 2661 .fields = (VMStateField[]) { 2662 VMSTATE_BOOL(tray_open, IDEState), 2663 VMSTATE_BOOL(tray_locked, IDEState), 2664 VMSTATE_END_OF_LIST() 2665 } 2666 }; 2667 2668 static const VMStateDescription vmstate_ide_drive_pio_state = { 2669 .name = "ide_drive/pio_state", 2670 .version_id = 1, 2671 .minimum_version_id = 1, 2672 .pre_save = ide_drive_pio_pre_save, 2673 .post_load = ide_drive_pio_post_load, 2674 .needed = ide_drive_pio_state_needed, 2675 .fields = (VMStateField[]) { 2676 VMSTATE_INT32(req_nb_sectors, IDEState), 2677 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1, 2678 vmstate_info_uint8, uint8_t), 2679 VMSTATE_INT32(cur_io_buffer_offset, IDEState), 2680 VMSTATE_INT32(cur_io_buffer_len, IDEState), 2681 VMSTATE_UINT8(end_transfer_fn_idx, IDEState), 2682 VMSTATE_INT32(elementary_transfer_size, IDEState), 2683 VMSTATE_INT32(packet_transfer_size, IDEState), 2684 VMSTATE_END_OF_LIST() 2685 } 2686 }; 2687 2688 const VMStateDescription vmstate_ide_drive = { 2689 .name = "ide_drive", 2690 .version_id = 3, 2691 .minimum_version_id = 0, 2692 .post_load = ide_drive_post_load, 2693 .fields = (VMStateField[]) { 2694 VMSTATE_INT32(mult_sectors, IDEState), 2695 VMSTATE_INT32(identify_set, IDEState), 2696 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set), 2697 VMSTATE_UINT8(feature, IDEState), 2698 VMSTATE_UINT8(error, IDEState), 2699 VMSTATE_UINT32(nsector, IDEState), 2700 VMSTATE_UINT8(sector, IDEState), 2701 VMSTATE_UINT8(lcyl, IDEState), 2702 VMSTATE_UINT8(hcyl, IDEState), 2703 VMSTATE_UINT8(hob_feature, IDEState), 2704 VMSTATE_UINT8(hob_sector, IDEState), 2705 VMSTATE_UINT8(hob_nsector, IDEState), 2706 VMSTATE_UINT8(hob_lcyl, IDEState), 2707 VMSTATE_UINT8(hob_hcyl, IDEState), 2708 VMSTATE_UINT8(select, IDEState), 2709 VMSTATE_UINT8(status, IDEState), 2710 VMSTATE_UINT8(lba48, IDEState), 2711 VMSTATE_UINT8(sense_key, IDEState), 2712 VMSTATE_UINT8(asc, IDEState), 2713 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3), 2714 VMSTATE_END_OF_LIST() 2715 }, 2716 .subsections = (const VMStateDescription*[]) { 2717 &vmstate_ide_drive_pio_state, 2718 &vmstate_ide_tray_state, 2719 &vmstate_ide_atapi_gesn_state, 2720 NULL 2721 } 2722 }; 2723 2724 static const VMStateDescription vmstate_ide_error_status = { 2725 .name ="ide_bus/error", 2726 .version_id = 2, 2727 .minimum_version_id = 1, 2728 .needed = ide_error_needed, 2729 .fields = (VMStateField[]) { 2730 VMSTATE_INT32(error_status, IDEBus), 2731 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2), 2732 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2), 2733 VMSTATE_UINT8_V(retry_unit, IDEBus, 2), 2734 VMSTATE_END_OF_LIST() 2735 } 2736 }; 2737 2738 const VMStateDescription vmstate_ide_bus = { 2739 .name = "ide_bus", 2740 .version_id = 1, 2741 .minimum_version_id = 1, 2742 .fields = (VMStateField[]) { 2743 VMSTATE_UINT8(cmd, IDEBus), 2744 VMSTATE_UINT8(unit, IDEBus), 2745 VMSTATE_END_OF_LIST() 2746 }, 2747 .subsections = (const VMStateDescription*[]) { 2748 &vmstate_ide_error_status, 2749 NULL 2750 } 2751 }; 2752 2753 void ide_drive_get(DriveInfo **hd, int n) 2754 { 2755 int i; 2756 int highest_bus = drive_get_max_bus(IF_IDE) + 1; 2757 int max_devs = drive_get_max_devs(IF_IDE); 2758 int n_buses = max_devs ? (n / max_devs) : n; 2759 2760 /* 2761 * Note: The number of actual buses available is not known. 2762 * We compute this based on the size of the DriveInfo* array, n. 2763 * If it is less than max_devs * <num_real_buses>, 2764 * We will stop looking for drives prematurely instead of overfilling 2765 * the array. 2766 */ 2767 2768 if (highest_bus > n_buses) { 2769 error_report("Too many IDE buses defined (%d > %d)", 2770 highest_bus, n_buses); 2771 exit(1); 2772 } 2773 2774 for (i = 0; i < n; i++) { 2775 hd[i] = drive_get_by_index(IF_IDE, i); 2776 } 2777 } 2778