1 /* 2 * QEMU IDE disk and CD/DVD-ROM Emulator 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include <hw/hw.h> 26 #include <hw/i386/pc.h> 27 #include <hw/pci/pci.h> 28 #include <hw/isa/isa.h> 29 #include "qemu/error-report.h" 30 #include "qemu/timer.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/dma.h" 33 #include "hw/block/block.h" 34 #include "sysemu/blockdev.h" 35 36 #include <hw/ide/internal.h> 37 38 /* These values were based on a Seagate ST3500418AS but have been modified 39 to make more sense in QEMU */ 40 static const int smart_attributes[][12] = { 41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */ 42 /* raw read error rate*/ 43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06}, 44 /* spin up */ 45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 46 /* start stop count */ 47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14}, 48 /* remapped sectors */ 49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24}, 50 /* power on hours */ 51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 52 /* power cycle count */ 53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 54 /* airflow-temperature-celsius */ 55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32}, 56 }; 57 58 static int ide_handle_rw_error(IDEState *s, int error, int op); 59 static void ide_dummy_transfer_stop(IDEState *s); 60 61 static void padstr(char *str, const char *src, int len) 62 { 63 int i, v; 64 for(i = 0; i < len; i++) { 65 if (*src) 66 v = *src++; 67 else 68 v = ' '; 69 str[i^1] = v; 70 } 71 } 72 73 static void put_le16(uint16_t *p, unsigned int v) 74 { 75 *p = cpu_to_le16(v); 76 } 77 78 static void ide_identify(IDEState *s) 79 { 80 uint16_t *p; 81 unsigned int oldsize; 82 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master; 83 84 if (s->identify_set) { 85 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data)); 86 return; 87 } 88 89 memset(s->io_buffer, 0, 512); 90 p = (uint16_t *)s->io_buffer; 91 put_le16(p + 0, 0x0040); 92 put_le16(p + 1, s->cylinders); 93 put_le16(p + 3, s->heads); 94 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */ 95 put_le16(p + 5, 512); /* XXX: retired, remove ? */ 96 put_le16(p + 6, s->sectors); 97 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 98 put_le16(p + 20, 3); /* XXX: retired, remove ? */ 99 put_le16(p + 21, 512); /* cache size in sectors */ 100 put_le16(p + 22, 4); /* ecc bytes */ 101 padstr((char *)(p + 23), s->version, 8); /* firmware version */ 102 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */ 103 #if MAX_MULT_SECTORS > 1 104 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); 105 #endif 106 put_le16(p + 48, 1); /* dword I/O */ 107 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */ 108 put_le16(p + 51, 0x200); /* PIO transfer cycle */ 109 put_le16(p + 52, 0x200); /* DMA transfer cycle */ 110 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */ 111 put_le16(p + 54, s->cylinders); 112 put_le16(p + 55, s->heads); 113 put_le16(p + 56, s->sectors); 114 oldsize = s->cylinders * s->heads * s->sectors; 115 put_le16(p + 57, oldsize); 116 put_le16(p + 58, oldsize >> 16); 117 if (s->mult_sectors) 118 put_le16(p + 59, 0x100 | s->mult_sectors); 119 put_le16(p + 60, s->nb_sectors); 120 put_le16(p + 61, s->nb_sectors >> 16); 121 put_le16(p + 62, 0x07); /* single word dma0-2 supported */ 122 put_le16(p + 63, 0x07); /* mdma0-2 supported */ 123 put_le16(p + 64, 0x03); /* pio3-4 supported */ 124 put_le16(p + 65, 120); 125 put_le16(p + 66, 120); 126 put_le16(p + 67, 120); 127 put_le16(p + 68, 120); 128 if (dev && dev->conf.discard_granularity) { 129 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */ 130 } 131 132 if (s->ncq_queues) { 133 put_le16(p + 75, s->ncq_queues - 1); 134 /* NCQ supported */ 135 put_le16(p + 76, (1 << 8)); 136 } 137 138 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */ 139 put_le16(p + 81, 0x16); /* conforms to ata5 */ 140 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */ 141 put_le16(p + 82, (1 << 14) | (1 << 5) | 1); 142 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ 143 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); 144 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */ 145 if (s->wwn) { 146 put_le16(p + 84, (1 << 14) | (1 << 8) | 0); 147 } else { 148 put_le16(p + 84, (1 << 14) | 0); 149 } 150 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */ 151 if (bdrv_enable_write_cache(s->bs)) 152 put_le16(p + 85, (1 << 14) | (1 << 5) | 1); 153 else 154 put_le16(p + 85, (1 << 14) | 1); 155 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ 156 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10)); 157 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */ 158 if (s->wwn) { 159 put_le16(p + 87, (1 << 14) | (1 << 8) | 0); 160 } else { 161 put_le16(p + 87, (1 << 14) | 0); 162 } 163 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ 164 put_le16(p + 93, 1 | (1 << 14) | 0x2000); 165 put_le16(p + 100, s->nb_sectors); 166 put_le16(p + 101, s->nb_sectors >> 16); 167 put_le16(p + 102, s->nb_sectors >> 32); 168 put_le16(p + 103, s->nb_sectors >> 48); 169 170 if (dev && dev->conf.physical_block_size) 171 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf)); 172 if (s->wwn) { 173 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */ 174 put_le16(p + 108, s->wwn >> 48); 175 put_le16(p + 109, s->wwn >> 32); 176 put_le16(p + 110, s->wwn >> 16); 177 put_le16(p + 111, s->wwn); 178 } 179 if (dev && dev->conf.discard_granularity) { 180 put_le16(p + 169, 1); /* TRIM support */ 181 } 182 183 memcpy(s->identify_data, p, sizeof(s->identify_data)); 184 s->identify_set = 1; 185 } 186 187 static void ide_atapi_identify(IDEState *s) 188 { 189 uint16_t *p; 190 191 if (s->identify_set) { 192 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data)); 193 return; 194 } 195 196 memset(s->io_buffer, 0, 512); 197 p = (uint16_t *)s->io_buffer; 198 /* Removable CDROM, 50us response, 12 byte packets */ 199 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0)); 200 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 201 put_le16(p + 20, 3); /* buffer type */ 202 put_le16(p + 21, 512); /* cache size in sectors */ 203 put_le16(p + 22, 4); /* ecc bytes */ 204 padstr((char *)(p + 23), s->version, 8); /* firmware version */ 205 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */ 206 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */ 207 #ifdef USE_DMA_CDROM 208 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */ 209 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */ 210 put_le16(p + 62, 7); /* single word dma0-2 supported */ 211 put_le16(p + 63, 7); /* mdma0-2 supported */ 212 #else 213 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */ 214 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */ 215 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */ 216 #endif 217 put_le16(p + 64, 3); /* pio3-4 supported */ 218 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */ 219 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */ 220 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */ 221 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */ 222 223 put_le16(p + 71, 30); /* in ns */ 224 put_le16(p + 72, 30); /* in ns */ 225 226 if (s->ncq_queues) { 227 put_le16(p + 75, s->ncq_queues - 1); 228 /* NCQ supported */ 229 put_le16(p + 76, (1 << 8)); 230 } 231 232 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */ 233 #ifdef USE_DMA_CDROM 234 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ 235 #endif 236 memcpy(s->identify_data, p, sizeof(s->identify_data)); 237 s->identify_set = 1; 238 } 239 240 static void ide_cfata_identify(IDEState *s) 241 { 242 uint16_t *p; 243 uint32_t cur_sec; 244 245 p = (uint16_t *) s->identify_data; 246 if (s->identify_set) 247 goto fill_buffer; 248 249 memset(p, 0, sizeof(s->identify_data)); 250 251 cur_sec = s->cylinders * s->heads * s->sectors; 252 253 put_le16(p + 0, 0x848a); /* CF Storage Card signature */ 254 put_le16(p + 1, s->cylinders); /* Default cylinders */ 255 put_le16(p + 3, s->heads); /* Default heads */ 256 put_le16(p + 6, s->sectors); /* Default sectors per track */ 257 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */ 258 put_le16(p + 8, s->nb_sectors); /* Sectors per card */ 259 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */ 260 put_le16(p + 22, 0x0004); /* ECC bytes */ 261 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */ 262 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */ 263 #if MAX_MULT_SECTORS > 1 264 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); 265 #else 266 put_le16(p + 47, 0x0000); 267 #endif 268 put_le16(p + 49, 0x0f00); /* Capabilities */ 269 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */ 270 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */ 271 put_le16(p + 53, 0x0003); /* Translation params valid */ 272 put_le16(p + 54, s->cylinders); /* Current cylinders */ 273 put_le16(p + 55, s->heads); /* Current heads */ 274 put_le16(p + 56, s->sectors); /* Current sectors */ 275 put_le16(p + 57, cur_sec); /* Current capacity */ 276 put_le16(p + 58, cur_sec >> 16); /* Current capacity */ 277 if (s->mult_sectors) /* Multiple sector setting */ 278 put_le16(p + 59, 0x100 | s->mult_sectors); 279 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */ 280 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */ 281 put_le16(p + 63, 0x0203); /* Multiword DMA capability */ 282 put_le16(p + 64, 0x0001); /* Flow Control PIO support */ 283 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */ 284 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */ 285 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */ 286 put_le16(p + 82, 0x400c); /* Command Set supported */ 287 put_le16(p + 83, 0x7068); /* Command Set supported */ 288 put_le16(p + 84, 0x4000); /* Features supported */ 289 put_le16(p + 85, 0x000c); /* Command Set enabled */ 290 put_le16(p + 86, 0x7044); /* Command Set enabled */ 291 put_le16(p + 87, 0x4000); /* Features enabled */ 292 put_le16(p + 91, 0x4060); /* Current APM level */ 293 put_le16(p + 129, 0x0002); /* Current features option */ 294 put_le16(p + 130, 0x0005); /* Reassigned sectors */ 295 put_le16(p + 131, 0x0001); /* Initial power mode */ 296 put_le16(p + 132, 0x0000); /* User signature */ 297 put_le16(p + 160, 0x8100); /* Power requirement */ 298 put_le16(p + 161, 0x8001); /* CF command set */ 299 300 s->identify_set = 1; 301 302 fill_buffer: 303 memcpy(s->io_buffer, p, sizeof(s->identify_data)); 304 } 305 306 static void ide_set_signature(IDEState *s) 307 { 308 s->select &= 0xf0; /* clear head */ 309 /* put signature */ 310 s->nsector = 1; 311 s->sector = 1; 312 if (s->drive_kind == IDE_CD) { 313 s->lcyl = 0x14; 314 s->hcyl = 0xeb; 315 } else if (s->bs) { 316 s->lcyl = 0; 317 s->hcyl = 0; 318 } else { 319 s->lcyl = 0xff; 320 s->hcyl = 0xff; 321 } 322 } 323 324 typedef struct TrimAIOCB { 325 BlockDriverAIOCB common; 326 QEMUBH *bh; 327 int ret; 328 QEMUIOVector *qiov; 329 BlockDriverAIOCB *aiocb; 330 int i, j; 331 } TrimAIOCB; 332 333 static void trim_aio_cancel(BlockDriverAIOCB *acb) 334 { 335 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common); 336 337 /* Exit the loop in case bdrv_aio_cancel calls ide_issue_trim_cb again. */ 338 iocb->j = iocb->qiov->niov - 1; 339 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1; 340 341 /* Tell ide_issue_trim_cb not to trigger the completion, too. */ 342 qemu_bh_delete(iocb->bh); 343 iocb->bh = NULL; 344 345 if (iocb->aiocb) { 346 bdrv_aio_cancel(iocb->aiocb); 347 } 348 qemu_aio_release(iocb); 349 } 350 351 static const AIOCBInfo trim_aiocb_info = { 352 .aiocb_size = sizeof(TrimAIOCB), 353 .cancel = trim_aio_cancel, 354 }; 355 356 static void ide_trim_bh_cb(void *opaque) 357 { 358 TrimAIOCB *iocb = opaque; 359 360 iocb->common.cb(iocb->common.opaque, iocb->ret); 361 362 qemu_bh_delete(iocb->bh); 363 iocb->bh = NULL; 364 qemu_aio_release(iocb); 365 } 366 367 static void ide_issue_trim_cb(void *opaque, int ret) 368 { 369 TrimAIOCB *iocb = opaque; 370 if (ret >= 0) { 371 while (iocb->j < iocb->qiov->niov) { 372 int j = iocb->j; 373 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) { 374 int i = iocb->i; 375 uint64_t *buffer = iocb->qiov->iov[j].iov_base; 376 377 /* 6-byte LBA + 2-byte range per entry */ 378 uint64_t entry = le64_to_cpu(buffer[i]); 379 uint64_t sector = entry & 0x0000ffffffffffffULL; 380 uint16_t count = entry >> 48; 381 382 if (count == 0) { 383 continue; 384 } 385 386 /* Got an entry! Submit and exit. */ 387 iocb->aiocb = bdrv_aio_discard(iocb->common.bs, sector, count, 388 ide_issue_trim_cb, opaque); 389 return; 390 } 391 392 iocb->j++; 393 iocb->i = -1; 394 } 395 } else { 396 iocb->ret = ret; 397 } 398 399 iocb->aiocb = NULL; 400 if (iocb->bh) { 401 qemu_bh_schedule(iocb->bh); 402 } 403 } 404 405 BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs, 406 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, 407 BlockDriverCompletionFunc *cb, void *opaque) 408 { 409 TrimAIOCB *iocb; 410 411 iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque); 412 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb); 413 iocb->ret = 0; 414 iocb->qiov = qiov; 415 iocb->i = -1; 416 iocb->j = 0; 417 ide_issue_trim_cb(iocb, 0); 418 return &iocb->common; 419 } 420 421 static inline void ide_abort_command(IDEState *s) 422 { 423 s->status = READY_STAT | ERR_STAT; 424 s->error = ABRT_ERR; 425 } 426 427 /* prepare data transfer and tell what to do after */ 428 void ide_transfer_start(IDEState *s, uint8_t *buf, int size, 429 EndTransferFunc *end_transfer_func) 430 { 431 s->end_transfer_func = end_transfer_func; 432 s->data_ptr = buf; 433 s->data_end = buf + size; 434 if (!(s->status & ERR_STAT)) { 435 s->status |= DRQ_STAT; 436 } 437 s->bus->dma->ops->start_transfer(s->bus->dma); 438 } 439 440 void ide_transfer_stop(IDEState *s) 441 { 442 s->end_transfer_func = ide_transfer_stop; 443 s->data_ptr = s->io_buffer; 444 s->data_end = s->io_buffer; 445 s->status &= ~DRQ_STAT; 446 } 447 448 int64_t ide_get_sector(IDEState *s) 449 { 450 int64_t sector_num; 451 if (s->select & 0x40) { 452 /* lba */ 453 if (!s->lba48) { 454 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | 455 (s->lcyl << 8) | s->sector; 456 } else { 457 sector_num = ((int64_t)s->hob_hcyl << 40) | 458 ((int64_t) s->hob_lcyl << 32) | 459 ((int64_t) s->hob_sector << 24) | 460 ((int64_t) s->hcyl << 16) | 461 ((int64_t) s->lcyl << 8) | s->sector; 462 } 463 } else { 464 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors + 465 (s->select & 0x0f) * s->sectors + (s->sector - 1); 466 } 467 return sector_num; 468 } 469 470 void ide_set_sector(IDEState *s, int64_t sector_num) 471 { 472 unsigned int cyl, r; 473 if (s->select & 0x40) { 474 if (!s->lba48) { 475 s->select = (s->select & 0xf0) | (sector_num >> 24); 476 s->hcyl = (sector_num >> 16); 477 s->lcyl = (sector_num >> 8); 478 s->sector = (sector_num); 479 } else { 480 s->sector = sector_num; 481 s->lcyl = sector_num >> 8; 482 s->hcyl = sector_num >> 16; 483 s->hob_sector = sector_num >> 24; 484 s->hob_lcyl = sector_num >> 32; 485 s->hob_hcyl = sector_num >> 40; 486 } 487 } else { 488 cyl = sector_num / (s->heads * s->sectors); 489 r = sector_num % (s->heads * s->sectors); 490 s->hcyl = cyl >> 8; 491 s->lcyl = cyl; 492 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f); 493 s->sector = (r % s->sectors) + 1; 494 } 495 } 496 497 static void ide_rw_error(IDEState *s) { 498 ide_abort_command(s); 499 ide_set_irq(s->bus); 500 } 501 502 static bool ide_sect_range_ok(IDEState *s, 503 uint64_t sector, uint64_t nb_sectors) 504 { 505 uint64_t total_sectors; 506 507 bdrv_get_geometry(s->bs, &total_sectors); 508 if (sector > total_sectors || nb_sectors > total_sectors - sector) { 509 return false; 510 } 511 return true; 512 } 513 514 static void ide_sector_read_cb(void *opaque, int ret) 515 { 516 IDEState *s = opaque; 517 int n; 518 519 s->pio_aiocb = NULL; 520 s->status &= ~BUSY_STAT; 521 522 bdrv_acct_done(s->bs, &s->acct); 523 if (ret != 0) { 524 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY | 525 BM_STATUS_RETRY_READ)) { 526 return; 527 } 528 } 529 530 n = s->nsector; 531 if (n > s->req_nb_sectors) { 532 n = s->req_nb_sectors; 533 } 534 535 /* Allow the guest to read the io_buffer */ 536 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read); 537 538 ide_set_irq(s->bus); 539 540 ide_set_sector(s, ide_get_sector(s) + n); 541 s->nsector -= n; 542 } 543 544 void ide_sector_read(IDEState *s) 545 { 546 int64_t sector_num; 547 int n; 548 549 s->status = READY_STAT | SEEK_STAT; 550 s->error = 0; /* not needed by IDE spec, but needed by Windows */ 551 sector_num = ide_get_sector(s); 552 n = s->nsector; 553 554 if (n == 0) { 555 ide_transfer_stop(s); 556 return; 557 } 558 559 s->status |= BUSY_STAT; 560 561 if (n > s->req_nb_sectors) { 562 n = s->req_nb_sectors; 563 } 564 565 #if defined(DEBUG_IDE) 566 printf("sector=%" PRId64 "\n", sector_num); 567 #endif 568 569 if (!ide_sect_range_ok(s, sector_num, n)) { 570 ide_rw_error(s); 571 return; 572 } 573 574 s->iov.iov_base = s->io_buffer; 575 s->iov.iov_len = n * BDRV_SECTOR_SIZE; 576 qemu_iovec_init_external(&s->qiov, &s->iov, 1); 577 578 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ); 579 s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n, 580 ide_sector_read_cb, s); 581 } 582 583 static void dma_buf_commit(IDEState *s) 584 { 585 qemu_sglist_destroy(&s->sg); 586 } 587 588 static void ide_async_cmd_done(IDEState *s) 589 { 590 if (s->bus->dma->ops->async_cmd_done) { 591 s->bus->dma->ops->async_cmd_done(s->bus->dma); 592 } 593 } 594 595 void ide_set_inactive(IDEState *s) 596 { 597 s->bus->dma->aiocb = NULL; 598 s->bus->dma->ops->set_inactive(s->bus->dma); 599 ide_async_cmd_done(s); 600 } 601 602 void ide_dma_error(IDEState *s) 603 { 604 ide_transfer_stop(s); 605 s->error = ABRT_ERR; 606 s->status = READY_STAT | ERR_STAT; 607 ide_set_inactive(s); 608 ide_set_irq(s->bus); 609 } 610 611 static int ide_handle_rw_error(IDEState *s, int error, int op) 612 { 613 bool is_read = (op & BM_STATUS_RETRY_READ) != 0; 614 BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error); 615 616 if (action == BLOCK_ERROR_ACTION_STOP) { 617 s->bus->dma->ops->set_unit(s->bus->dma, s->unit); 618 s->bus->error_status = op; 619 } else if (action == BLOCK_ERROR_ACTION_REPORT) { 620 if (op & BM_STATUS_DMA_RETRY) { 621 dma_buf_commit(s); 622 ide_dma_error(s); 623 } else { 624 ide_rw_error(s); 625 } 626 } 627 bdrv_error_action(s->bs, action, is_read, error); 628 return action != BLOCK_ERROR_ACTION_IGNORE; 629 } 630 631 void ide_dma_cb(void *opaque, int ret) 632 { 633 IDEState *s = opaque; 634 int n; 635 int64_t sector_num; 636 bool stay_active = false; 637 638 if (ret < 0) { 639 int op = BM_STATUS_DMA_RETRY; 640 641 if (s->dma_cmd == IDE_DMA_READ) 642 op |= BM_STATUS_RETRY_READ; 643 else if (s->dma_cmd == IDE_DMA_TRIM) 644 op |= BM_STATUS_RETRY_TRIM; 645 646 if (ide_handle_rw_error(s, -ret, op)) { 647 return; 648 } 649 } 650 651 n = s->io_buffer_size >> 9; 652 if (n > s->nsector) { 653 /* The PRDs were longer than needed for this request. Shorten them so 654 * we don't get a negative remainder. The Active bit must remain set 655 * after the request completes. */ 656 n = s->nsector; 657 stay_active = true; 658 } 659 660 sector_num = ide_get_sector(s); 661 if (n > 0) { 662 dma_buf_commit(s); 663 sector_num += n; 664 ide_set_sector(s, sector_num); 665 s->nsector -= n; 666 } 667 668 /* end of transfer ? */ 669 if (s->nsector == 0) { 670 s->status = READY_STAT | SEEK_STAT; 671 ide_set_irq(s->bus); 672 goto eot; 673 } 674 675 /* launch next transfer */ 676 n = s->nsector; 677 s->io_buffer_index = 0; 678 s->io_buffer_size = n * 512; 679 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) { 680 /* The PRDs were too short. Reset the Active bit, but don't raise an 681 * interrupt. */ 682 s->status = READY_STAT | SEEK_STAT; 683 goto eot; 684 } 685 686 #ifdef DEBUG_AIO 687 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n", 688 sector_num, n, s->dma_cmd); 689 #endif 690 691 if (!ide_sect_range_ok(s, sector_num, n)) { 692 dma_buf_commit(s); 693 ide_dma_error(s); 694 return; 695 } 696 697 switch (s->dma_cmd) { 698 case IDE_DMA_READ: 699 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num, 700 ide_dma_cb, s); 701 break; 702 case IDE_DMA_WRITE: 703 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num, 704 ide_dma_cb, s); 705 break; 706 case IDE_DMA_TRIM: 707 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num, 708 ide_issue_trim, ide_dma_cb, s, 709 DMA_DIRECTION_TO_DEVICE); 710 break; 711 } 712 return; 713 714 eot: 715 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { 716 bdrv_acct_done(s->bs, &s->acct); 717 } 718 ide_set_inactive(s); 719 if (stay_active) { 720 s->bus->dma->ops->add_status(s->bus->dma, BM_STATUS_DMAING); 721 } 722 } 723 724 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd) 725 { 726 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; 727 s->io_buffer_index = 0; 728 s->io_buffer_size = 0; 729 s->dma_cmd = dma_cmd; 730 731 switch (dma_cmd) { 732 case IDE_DMA_READ: 733 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE, 734 BDRV_ACCT_READ); 735 break; 736 case IDE_DMA_WRITE: 737 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE, 738 BDRV_ACCT_WRITE); 739 break; 740 default: 741 break; 742 } 743 744 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb); 745 } 746 747 static void ide_sector_write_timer_cb(void *opaque) 748 { 749 IDEState *s = opaque; 750 ide_set_irq(s->bus); 751 } 752 753 static void ide_sector_write_cb(void *opaque, int ret) 754 { 755 IDEState *s = opaque; 756 int n; 757 758 bdrv_acct_done(s->bs, &s->acct); 759 760 s->pio_aiocb = NULL; 761 s->status &= ~BUSY_STAT; 762 763 if (ret != 0) { 764 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) { 765 return; 766 } 767 } 768 769 n = s->nsector; 770 if (n > s->req_nb_sectors) { 771 n = s->req_nb_sectors; 772 } 773 s->nsector -= n; 774 if (s->nsector == 0) { 775 /* no more sectors to write */ 776 ide_transfer_stop(s); 777 } else { 778 int n1 = s->nsector; 779 if (n1 > s->req_nb_sectors) { 780 n1 = s->req_nb_sectors; 781 } 782 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE, 783 ide_sector_write); 784 } 785 ide_set_sector(s, ide_get_sector(s) + n); 786 787 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) { 788 /* It seems there is a bug in the Windows 2000 installer HDD 789 IDE driver which fills the disk with empty logs when the 790 IDE write IRQ comes too early. This hack tries to correct 791 that at the expense of slower write performances. Use this 792 option _only_ to install Windows 2000. You must disable it 793 for normal use. */ 794 timer_mod(s->sector_write_timer, 795 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000)); 796 } else { 797 ide_set_irq(s->bus); 798 } 799 } 800 801 void ide_sector_write(IDEState *s) 802 { 803 int64_t sector_num; 804 int n; 805 806 s->status = READY_STAT | SEEK_STAT | BUSY_STAT; 807 sector_num = ide_get_sector(s); 808 #if defined(DEBUG_IDE) 809 printf("sector=%" PRId64 "\n", sector_num); 810 #endif 811 n = s->nsector; 812 if (n > s->req_nb_sectors) { 813 n = s->req_nb_sectors; 814 } 815 816 if (!ide_sect_range_ok(s, sector_num, n)) { 817 ide_rw_error(s); 818 return; 819 } 820 821 s->iov.iov_base = s->io_buffer; 822 s->iov.iov_len = n * BDRV_SECTOR_SIZE; 823 qemu_iovec_init_external(&s->qiov, &s->iov, 1); 824 825 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ); 826 s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n, 827 ide_sector_write_cb, s); 828 } 829 830 static void ide_flush_cb(void *opaque, int ret) 831 { 832 IDEState *s = opaque; 833 834 if (ret < 0) { 835 /* XXX: What sector number to set here? */ 836 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) { 837 return; 838 } 839 } 840 841 bdrv_acct_done(s->bs, &s->acct); 842 s->status = READY_STAT | SEEK_STAT; 843 ide_async_cmd_done(s); 844 ide_set_irq(s->bus); 845 } 846 847 void ide_flush_cache(IDEState *s) 848 { 849 if (s->bs == NULL) { 850 ide_flush_cb(s, 0); 851 return; 852 } 853 854 s->status |= BUSY_STAT; 855 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH); 856 bdrv_aio_flush(s->bs, ide_flush_cb, s); 857 } 858 859 static void ide_cfata_metadata_inquiry(IDEState *s) 860 { 861 uint16_t *p; 862 uint32_t spd; 863 864 p = (uint16_t *) s->io_buffer; 865 memset(p, 0, 0x200); 866 spd = ((s->mdata_size - 1) >> 9) + 1; 867 868 put_le16(p + 0, 0x0001); /* Data format revision */ 869 put_le16(p + 1, 0x0000); /* Media property: silicon */ 870 put_le16(p + 2, s->media_changed); /* Media status */ 871 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */ 872 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */ 873 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */ 874 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */ 875 } 876 877 static void ide_cfata_metadata_read(IDEState *s) 878 { 879 uint16_t *p; 880 881 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { 882 s->status = ERR_STAT; 883 s->error = ABRT_ERR; 884 return; 885 } 886 887 p = (uint16_t *) s->io_buffer; 888 memset(p, 0, 0x200); 889 890 put_le16(p + 0, s->media_changed); /* Media status */ 891 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), 892 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), 893 s->nsector << 9), 0x200 - 2)); 894 } 895 896 static void ide_cfata_metadata_write(IDEState *s) 897 { 898 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { 899 s->status = ERR_STAT; 900 s->error = ABRT_ERR; 901 return; 902 } 903 904 s->media_changed = 0; 905 906 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), 907 s->io_buffer + 2, 908 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), 909 s->nsector << 9), 0x200 - 2)); 910 } 911 912 /* called when the inserted state of the media has changed */ 913 static void ide_cd_change_cb(void *opaque, bool load) 914 { 915 IDEState *s = opaque; 916 uint64_t nb_sectors; 917 918 s->tray_open = !load; 919 bdrv_get_geometry(s->bs, &nb_sectors); 920 s->nb_sectors = nb_sectors; 921 922 /* 923 * First indicate to the guest that a CD has been removed. That's 924 * done on the next command the guest sends us. 925 * 926 * Then we set UNIT_ATTENTION, by which the guest will 927 * detect a new CD in the drive. See ide_atapi_cmd() for details. 928 */ 929 s->cdrom_changed = 1; 930 s->events.new_media = true; 931 s->events.eject_request = false; 932 ide_set_irq(s->bus); 933 } 934 935 static void ide_cd_eject_request_cb(void *opaque, bool force) 936 { 937 IDEState *s = opaque; 938 939 s->events.eject_request = true; 940 if (force) { 941 s->tray_locked = false; 942 } 943 ide_set_irq(s->bus); 944 } 945 946 static void ide_cmd_lba48_transform(IDEState *s, int lba48) 947 { 948 s->lba48 = lba48; 949 950 /* handle the 'magic' 0 nsector count conversion here. to avoid 951 * fiddling with the rest of the read logic, we just store the 952 * full sector count in ->nsector and ignore ->hob_nsector from now 953 */ 954 if (!s->lba48) { 955 if (!s->nsector) 956 s->nsector = 256; 957 } else { 958 if (!s->nsector && !s->hob_nsector) 959 s->nsector = 65536; 960 else { 961 int lo = s->nsector; 962 int hi = s->hob_nsector; 963 964 s->nsector = (hi << 8) | lo; 965 } 966 } 967 } 968 969 static void ide_clear_hob(IDEBus *bus) 970 { 971 /* any write clears HOB high bit of device control register */ 972 bus->ifs[0].select &= ~(1 << 7); 973 bus->ifs[1].select &= ~(1 << 7); 974 } 975 976 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) 977 { 978 IDEBus *bus = opaque; 979 980 #ifdef DEBUG_IDE 981 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val); 982 #endif 983 984 addr &= 7; 985 986 /* ignore writes to command block while busy with previous command */ 987 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT))) 988 return; 989 990 switch(addr) { 991 case 0: 992 break; 993 case 1: 994 ide_clear_hob(bus); 995 /* NOTE: data is written to the two drives */ 996 bus->ifs[0].hob_feature = bus->ifs[0].feature; 997 bus->ifs[1].hob_feature = bus->ifs[1].feature; 998 bus->ifs[0].feature = val; 999 bus->ifs[1].feature = val; 1000 break; 1001 case 2: 1002 ide_clear_hob(bus); 1003 bus->ifs[0].hob_nsector = bus->ifs[0].nsector; 1004 bus->ifs[1].hob_nsector = bus->ifs[1].nsector; 1005 bus->ifs[0].nsector = val; 1006 bus->ifs[1].nsector = val; 1007 break; 1008 case 3: 1009 ide_clear_hob(bus); 1010 bus->ifs[0].hob_sector = bus->ifs[0].sector; 1011 bus->ifs[1].hob_sector = bus->ifs[1].sector; 1012 bus->ifs[0].sector = val; 1013 bus->ifs[1].sector = val; 1014 break; 1015 case 4: 1016 ide_clear_hob(bus); 1017 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl; 1018 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl; 1019 bus->ifs[0].lcyl = val; 1020 bus->ifs[1].lcyl = val; 1021 break; 1022 case 5: 1023 ide_clear_hob(bus); 1024 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl; 1025 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl; 1026 bus->ifs[0].hcyl = val; 1027 bus->ifs[1].hcyl = val; 1028 break; 1029 case 6: 1030 /* FIXME: HOB readback uses bit 7 */ 1031 bus->ifs[0].select = (val & ~0x10) | 0xa0; 1032 bus->ifs[1].select = (val | 0x10) | 0xa0; 1033 /* select drive */ 1034 bus->unit = (val >> 4) & 1; 1035 break; 1036 default: 1037 case 7: 1038 /* command */ 1039 ide_exec_cmd(bus, val); 1040 break; 1041 } 1042 } 1043 1044 static bool cmd_nop(IDEState *s, uint8_t cmd) 1045 { 1046 return true; 1047 } 1048 1049 static bool cmd_data_set_management(IDEState *s, uint8_t cmd) 1050 { 1051 switch (s->feature) { 1052 case DSM_TRIM: 1053 if (s->bs) { 1054 ide_sector_start_dma(s, IDE_DMA_TRIM); 1055 return false; 1056 } 1057 break; 1058 } 1059 1060 ide_abort_command(s); 1061 return true; 1062 } 1063 1064 static bool cmd_identify(IDEState *s, uint8_t cmd) 1065 { 1066 if (s->bs && s->drive_kind != IDE_CD) { 1067 if (s->drive_kind != IDE_CFATA) { 1068 ide_identify(s); 1069 } else { 1070 ide_cfata_identify(s); 1071 } 1072 s->status = READY_STAT | SEEK_STAT; 1073 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); 1074 ide_set_irq(s->bus); 1075 return false; 1076 } else { 1077 if (s->drive_kind == IDE_CD) { 1078 ide_set_signature(s); 1079 } 1080 ide_abort_command(s); 1081 } 1082 1083 return true; 1084 } 1085 1086 static bool cmd_verify(IDEState *s, uint8_t cmd) 1087 { 1088 bool lba48 = (cmd == WIN_VERIFY_EXT); 1089 1090 /* do sector number check ? */ 1091 ide_cmd_lba48_transform(s, lba48); 1092 1093 return true; 1094 } 1095 1096 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd) 1097 { 1098 if (s->drive_kind == IDE_CFATA && s->nsector == 0) { 1099 /* Disable Read and Write Multiple */ 1100 s->mult_sectors = 0; 1101 } else if ((s->nsector & 0xff) != 0 && 1102 ((s->nsector & 0xff) > MAX_MULT_SECTORS || 1103 (s->nsector & (s->nsector - 1)) != 0)) { 1104 ide_abort_command(s); 1105 } else { 1106 s->mult_sectors = s->nsector & 0xff; 1107 } 1108 1109 return true; 1110 } 1111 1112 static bool cmd_read_multiple(IDEState *s, uint8_t cmd) 1113 { 1114 bool lba48 = (cmd == WIN_MULTREAD_EXT); 1115 1116 if (!s->bs || !s->mult_sectors) { 1117 ide_abort_command(s); 1118 return true; 1119 } 1120 1121 ide_cmd_lba48_transform(s, lba48); 1122 s->req_nb_sectors = s->mult_sectors; 1123 ide_sector_read(s); 1124 return false; 1125 } 1126 1127 static bool cmd_write_multiple(IDEState *s, uint8_t cmd) 1128 { 1129 bool lba48 = (cmd == WIN_MULTWRITE_EXT); 1130 int n; 1131 1132 if (!s->bs || !s->mult_sectors) { 1133 ide_abort_command(s); 1134 return true; 1135 } 1136 1137 ide_cmd_lba48_transform(s, lba48); 1138 1139 s->req_nb_sectors = s->mult_sectors; 1140 n = MIN(s->nsector, s->req_nb_sectors); 1141 1142 s->status = SEEK_STAT | READY_STAT; 1143 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write); 1144 1145 s->media_changed = 1; 1146 1147 return false; 1148 } 1149 1150 static bool cmd_read_pio(IDEState *s, uint8_t cmd) 1151 { 1152 bool lba48 = (cmd == WIN_READ_EXT); 1153 1154 if (s->drive_kind == IDE_CD) { 1155 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */ 1156 ide_abort_command(s); 1157 return true; 1158 } 1159 1160 if (!s->bs) { 1161 ide_abort_command(s); 1162 return true; 1163 } 1164 1165 ide_cmd_lba48_transform(s, lba48); 1166 s->req_nb_sectors = 1; 1167 ide_sector_read(s); 1168 1169 return false; 1170 } 1171 1172 static bool cmd_write_pio(IDEState *s, uint8_t cmd) 1173 { 1174 bool lba48 = (cmd == WIN_WRITE_EXT); 1175 1176 if (!s->bs) { 1177 ide_abort_command(s); 1178 return true; 1179 } 1180 1181 ide_cmd_lba48_transform(s, lba48); 1182 1183 s->req_nb_sectors = 1; 1184 s->status = SEEK_STAT | READY_STAT; 1185 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write); 1186 1187 s->media_changed = 1; 1188 1189 return false; 1190 } 1191 1192 static bool cmd_read_dma(IDEState *s, uint8_t cmd) 1193 { 1194 bool lba48 = (cmd == WIN_READDMA_EXT); 1195 1196 if (!s->bs) { 1197 ide_abort_command(s); 1198 return true; 1199 } 1200 1201 ide_cmd_lba48_transform(s, lba48); 1202 ide_sector_start_dma(s, IDE_DMA_READ); 1203 1204 return false; 1205 } 1206 1207 static bool cmd_write_dma(IDEState *s, uint8_t cmd) 1208 { 1209 bool lba48 = (cmd == WIN_WRITEDMA_EXT); 1210 1211 if (!s->bs) { 1212 ide_abort_command(s); 1213 return true; 1214 } 1215 1216 ide_cmd_lba48_transform(s, lba48); 1217 ide_sector_start_dma(s, IDE_DMA_WRITE); 1218 1219 s->media_changed = 1; 1220 1221 return false; 1222 } 1223 1224 static bool cmd_flush_cache(IDEState *s, uint8_t cmd) 1225 { 1226 ide_flush_cache(s); 1227 return false; 1228 } 1229 1230 static bool cmd_seek(IDEState *s, uint8_t cmd) 1231 { 1232 /* XXX: Check that seek is within bounds */ 1233 return true; 1234 } 1235 1236 static bool cmd_read_native_max(IDEState *s, uint8_t cmd) 1237 { 1238 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT); 1239 1240 /* Refuse if no sectors are addressable (e.g. medium not inserted) */ 1241 if (s->nb_sectors == 0) { 1242 ide_abort_command(s); 1243 return true; 1244 } 1245 1246 ide_cmd_lba48_transform(s, lba48); 1247 ide_set_sector(s, s->nb_sectors - 1); 1248 1249 return true; 1250 } 1251 1252 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd) 1253 { 1254 s->nsector = 0xff; /* device active or idle */ 1255 return true; 1256 } 1257 1258 static bool cmd_set_features(IDEState *s, uint8_t cmd) 1259 { 1260 uint16_t *identify_data; 1261 1262 if (!s->bs) { 1263 ide_abort_command(s); 1264 return true; 1265 } 1266 1267 /* XXX: valid for CDROM ? */ 1268 switch (s->feature) { 1269 case 0x02: /* write cache enable */ 1270 bdrv_set_enable_write_cache(s->bs, true); 1271 identify_data = (uint16_t *)s->identify_data; 1272 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1); 1273 return true; 1274 case 0x82: /* write cache disable */ 1275 bdrv_set_enable_write_cache(s->bs, false); 1276 identify_data = (uint16_t *)s->identify_data; 1277 put_le16(identify_data + 85, (1 << 14) | 1); 1278 ide_flush_cache(s); 1279 return false; 1280 case 0xcc: /* reverting to power-on defaults enable */ 1281 case 0x66: /* reverting to power-on defaults disable */ 1282 case 0xaa: /* read look-ahead enable */ 1283 case 0x55: /* read look-ahead disable */ 1284 case 0x05: /* set advanced power management mode */ 1285 case 0x85: /* disable advanced power management mode */ 1286 case 0x69: /* NOP */ 1287 case 0x67: /* NOP */ 1288 case 0x96: /* NOP */ 1289 case 0x9a: /* NOP */ 1290 case 0x42: /* enable Automatic Acoustic Mode */ 1291 case 0xc2: /* disable Automatic Acoustic Mode */ 1292 return true; 1293 case 0x03: /* set transfer mode */ 1294 { 1295 uint8_t val = s->nsector & 0x07; 1296 identify_data = (uint16_t *)s->identify_data; 1297 1298 switch (s->nsector >> 3) { 1299 case 0x00: /* pio default */ 1300 case 0x01: /* pio mode */ 1301 put_le16(identify_data + 62, 0x07); 1302 put_le16(identify_data + 63, 0x07); 1303 put_le16(identify_data + 88, 0x3f); 1304 break; 1305 case 0x02: /* sigle word dma mode*/ 1306 put_le16(identify_data + 62, 0x07 | (1 << (val + 8))); 1307 put_le16(identify_data + 63, 0x07); 1308 put_le16(identify_data + 88, 0x3f); 1309 break; 1310 case 0x04: /* mdma mode */ 1311 put_le16(identify_data + 62, 0x07); 1312 put_le16(identify_data + 63, 0x07 | (1 << (val + 8))); 1313 put_le16(identify_data + 88, 0x3f); 1314 break; 1315 case 0x08: /* udma mode */ 1316 put_le16(identify_data + 62, 0x07); 1317 put_le16(identify_data + 63, 0x07); 1318 put_le16(identify_data + 88, 0x3f | (1 << (val + 8))); 1319 break; 1320 default: 1321 goto abort_cmd; 1322 } 1323 return true; 1324 } 1325 } 1326 1327 abort_cmd: 1328 ide_abort_command(s); 1329 return true; 1330 } 1331 1332 1333 /*** ATAPI commands ***/ 1334 1335 static bool cmd_identify_packet(IDEState *s, uint8_t cmd) 1336 { 1337 ide_atapi_identify(s); 1338 s->status = READY_STAT | SEEK_STAT; 1339 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop); 1340 ide_set_irq(s->bus); 1341 return false; 1342 } 1343 1344 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd) 1345 { 1346 ide_set_signature(s); 1347 1348 if (s->drive_kind == IDE_CD) { 1349 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet 1350 * devices to return a clear status register 1351 * with READY_STAT *not* set. */ 1352 s->error = 0x01; 1353 } else { 1354 s->status = READY_STAT | SEEK_STAT; 1355 /* The bits of the error register are not as usual for this command! 1356 * They are part of the regular output (this is why ERR_STAT isn't set) 1357 * Device 0 passed, Device 1 passed or not present. */ 1358 s->error = 0x01; 1359 ide_set_irq(s->bus); 1360 } 1361 1362 return false; 1363 } 1364 1365 static bool cmd_device_reset(IDEState *s, uint8_t cmd) 1366 { 1367 ide_set_signature(s); 1368 s->status = 0x00; /* NOTE: READY is _not_ set */ 1369 s->error = 0x01; 1370 1371 return false; 1372 } 1373 1374 static bool cmd_packet(IDEState *s, uint8_t cmd) 1375 { 1376 /* overlapping commands not supported */ 1377 if (s->feature & 0x02) { 1378 ide_abort_command(s); 1379 return true; 1380 } 1381 1382 s->status = READY_STAT | SEEK_STAT; 1383 s->atapi_dma = s->feature & 1; 1384 s->nsector = 1; 1385 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, 1386 ide_atapi_cmd); 1387 return false; 1388 } 1389 1390 1391 /*** CF-ATA commands ***/ 1392 1393 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd) 1394 { 1395 s->error = 0x09; /* miscellaneous error */ 1396 s->status = READY_STAT | SEEK_STAT; 1397 ide_set_irq(s->bus); 1398 1399 return false; 1400 } 1401 1402 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd) 1403 { 1404 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is 1405 * required for Windows 8 to work with AHCI */ 1406 1407 if (cmd == CFA_WEAR_LEVEL) { 1408 s->nsector = 0; 1409 } 1410 1411 if (cmd == CFA_ERASE_SECTORS) { 1412 s->media_changed = 1; 1413 } 1414 1415 return true; 1416 } 1417 1418 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd) 1419 { 1420 s->status = READY_STAT | SEEK_STAT; 1421 1422 memset(s->io_buffer, 0, 0x200); 1423 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */ 1424 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */ 1425 s->io_buffer[0x02] = s->select; /* Head */ 1426 s->io_buffer[0x03] = s->sector; /* Sector */ 1427 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */ 1428 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */ 1429 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */ 1430 s->io_buffer[0x13] = 0x00; /* Erase flag */ 1431 s->io_buffer[0x18] = 0x00; /* Hot count */ 1432 s->io_buffer[0x19] = 0x00; /* Hot count */ 1433 s->io_buffer[0x1a] = 0x01; /* Hot count */ 1434 1435 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1436 ide_set_irq(s->bus); 1437 1438 return false; 1439 } 1440 1441 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd) 1442 { 1443 switch (s->feature) { 1444 case 0x02: /* Inquiry Metadata Storage */ 1445 ide_cfata_metadata_inquiry(s); 1446 break; 1447 case 0x03: /* Read Metadata Storage */ 1448 ide_cfata_metadata_read(s); 1449 break; 1450 case 0x04: /* Write Metadata Storage */ 1451 ide_cfata_metadata_write(s); 1452 break; 1453 default: 1454 ide_abort_command(s); 1455 return true; 1456 } 1457 1458 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1459 s->status = 0x00; /* NOTE: READY is _not_ set */ 1460 ide_set_irq(s->bus); 1461 1462 return false; 1463 } 1464 1465 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd) 1466 { 1467 switch (s->feature) { 1468 case 0x01: /* sense temperature in device */ 1469 s->nsector = 0x50; /* +20 C */ 1470 break; 1471 default: 1472 ide_abort_command(s); 1473 return true; 1474 } 1475 1476 return true; 1477 } 1478 1479 1480 /*** SMART commands ***/ 1481 1482 static bool cmd_smart(IDEState *s, uint8_t cmd) 1483 { 1484 int n; 1485 1486 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) { 1487 goto abort_cmd; 1488 } 1489 1490 if (!s->smart_enabled && s->feature != SMART_ENABLE) { 1491 goto abort_cmd; 1492 } 1493 1494 switch (s->feature) { 1495 case SMART_DISABLE: 1496 s->smart_enabled = 0; 1497 return true; 1498 1499 case SMART_ENABLE: 1500 s->smart_enabled = 1; 1501 return true; 1502 1503 case SMART_ATTR_AUTOSAVE: 1504 switch (s->sector) { 1505 case 0x00: 1506 s->smart_autosave = 0; 1507 break; 1508 case 0xf1: 1509 s->smart_autosave = 1; 1510 break; 1511 default: 1512 goto abort_cmd; 1513 } 1514 return true; 1515 1516 case SMART_STATUS: 1517 if (!s->smart_errors) { 1518 s->hcyl = 0xc2; 1519 s->lcyl = 0x4f; 1520 } else { 1521 s->hcyl = 0x2c; 1522 s->lcyl = 0xf4; 1523 } 1524 return true; 1525 1526 case SMART_READ_THRESH: 1527 memset(s->io_buffer, 0, 0x200); 1528 s->io_buffer[0] = 0x01; /* smart struct version */ 1529 1530 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) { 1531 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0]; 1532 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11]; 1533 } 1534 1535 /* checksum */ 1536 for (n = 0; n < 511; n++) { 1537 s->io_buffer[511] += s->io_buffer[n]; 1538 } 1539 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1540 1541 s->status = READY_STAT | SEEK_STAT; 1542 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1543 ide_set_irq(s->bus); 1544 return false; 1545 1546 case SMART_READ_DATA: 1547 memset(s->io_buffer, 0, 0x200); 1548 s->io_buffer[0] = 0x01; /* smart struct version */ 1549 1550 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) { 1551 int i; 1552 for (i = 0; i < 11; i++) { 1553 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i]; 1554 } 1555 } 1556 1557 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00); 1558 if (s->smart_selftest_count == 0) { 1559 s->io_buffer[363] = 0; 1560 } else { 1561 s->io_buffer[363] = 1562 s->smart_selftest_data[3 + 1563 (s->smart_selftest_count - 1) * 1564 24]; 1565 } 1566 s->io_buffer[364] = 0x20; 1567 s->io_buffer[365] = 0x01; 1568 /* offline data collection capacity: execute + self-test*/ 1569 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1); 1570 s->io_buffer[368] = 0x03; /* smart capability (1) */ 1571 s->io_buffer[369] = 0x00; /* smart capability (2) */ 1572 s->io_buffer[370] = 0x01; /* error logging supported */ 1573 s->io_buffer[372] = 0x02; /* minutes for poll short test */ 1574 s->io_buffer[373] = 0x36; /* minutes for poll ext test */ 1575 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */ 1576 1577 for (n = 0; n < 511; n++) { 1578 s->io_buffer[511] += s->io_buffer[n]; 1579 } 1580 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1581 1582 s->status = READY_STAT | SEEK_STAT; 1583 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1584 ide_set_irq(s->bus); 1585 return false; 1586 1587 case SMART_READ_LOG: 1588 switch (s->sector) { 1589 case 0x01: /* summary smart error log */ 1590 memset(s->io_buffer, 0, 0x200); 1591 s->io_buffer[0] = 0x01; 1592 s->io_buffer[1] = 0x00; /* no error entries */ 1593 s->io_buffer[452] = s->smart_errors & 0xff; 1594 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8; 1595 1596 for (n = 0; n < 511; n++) { 1597 s->io_buffer[511] += s->io_buffer[n]; 1598 } 1599 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1600 break; 1601 case 0x06: /* smart self test log */ 1602 memset(s->io_buffer, 0, 0x200); 1603 s->io_buffer[0] = 0x01; 1604 if (s->smart_selftest_count == 0) { 1605 s->io_buffer[508] = 0; 1606 } else { 1607 s->io_buffer[508] = s->smart_selftest_count; 1608 for (n = 2; n < 506; n++) { 1609 s->io_buffer[n] = s->smart_selftest_data[n]; 1610 } 1611 } 1612 1613 for (n = 0; n < 511; n++) { 1614 s->io_buffer[511] += s->io_buffer[n]; 1615 } 1616 s->io_buffer[511] = 0x100 - s->io_buffer[511]; 1617 break; 1618 default: 1619 goto abort_cmd; 1620 } 1621 s->status = READY_STAT | SEEK_STAT; 1622 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop); 1623 ide_set_irq(s->bus); 1624 return false; 1625 1626 case SMART_EXECUTE_OFFLINE: 1627 switch (s->sector) { 1628 case 0: /* off-line routine */ 1629 case 1: /* short self test */ 1630 case 2: /* extended self test */ 1631 s->smart_selftest_count++; 1632 if (s->smart_selftest_count > 21) { 1633 s->smart_selftest_count = 1; 1634 } 1635 n = 2 + (s->smart_selftest_count - 1) * 24; 1636 s->smart_selftest_data[n] = s->sector; 1637 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */ 1638 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */ 1639 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */ 1640 break; 1641 default: 1642 goto abort_cmd; 1643 } 1644 return true; 1645 } 1646 1647 abort_cmd: 1648 ide_abort_command(s); 1649 return true; 1650 } 1651 1652 #define HD_OK (1u << IDE_HD) 1653 #define CD_OK (1u << IDE_CD) 1654 #define CFA_OK (1u << IDE_CFATA) 1655 #define HD_CFA_OK (HD_OK | CFA_OK) 1656 #define ALL_OK (HD_OK | CD_OK | CFA_OK) 1657 1658 /* Set the Disk Seek Completed status bit during completion */ 1659 #define SET_DSC (1u << 8) 1660 1661 /* See ACS-2 T13/2015-D Table B.2 Command codes */ 1662 static const struct { 1663 /* Returns true if the completion code should be run */ 1664 bool (*handler)(IDEState *s, uint8_t cmd); 1665 int flags; 1666 } ide_cmd_table[0x100] = { 1667 /* NOP not implemented, mandatory for CD */ 1668 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK }, 1669 [WIN_DSM] = { cmd_data_set_management, ALL_OK }, 1670 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK }, 1671 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC}, 1672 [WIN_READ] = { cmd_read_pio, ALL_OK }, 1673 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK }, 1674 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK }, 1675 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK }, 1676 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC }, 1677 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK }, 1678 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK }, 1679 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK }, 1680 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK }, 1681 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK }, 1682 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK }, 1683 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK }, 1684 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK }, 1685 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1686 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1687 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC }, 1688 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC }, 1689 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK }, 1690 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK }, 1691 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC }, 1692 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK }, 1693 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK }, 1694 [WIN_STANDBY2] = { cmd_nop, ALL_OK }, 1695 [WIN_SETIDLE2] = { cmd_nop, ALL_OK }, 1696 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC }, 1697 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK }, 1698 [WIN_PACKETCMD] = { cmd_packet, CD_OK }, 1699 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK }, 1700 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC }, 1701 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK }, 1702 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC }, 1703 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK }, 1704 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK }, 1705 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC }, 1706 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK }, 1707 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK }, 1708 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK }, 1709 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK }, 1710 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK }, 1711 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK }, 1712 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK }, 1713 [WIN_STANDBY] = { cmd_nop, ALL_OK }, 1714 [WIN_SETIDLE1] = { cmd_nop, ALL_OK }, 1715 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC }, 1716 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK }, 1717 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK }, 1718 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK }, 1719 [WIN_IDENTIFY] = { cmd_identify, ALL_OK }, 1720 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC }, 1721 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC }, 1722 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC }, 1723 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC }, 1724 }; 1725 1726 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd) 1727 { 1728 return cmd < ARRAY_SIZE(ide_cmd_table) 1729 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind)); 1730 } 1731 1732 void ide_exec_cmd(IDEBus *bus, uint32_t val) 1733 { 1734 IDEState *s; 1735 bool complete; 1736 1737 #if defined(DEBUG_IDE) 1738 printf("ide: CMD=%02x\n", val); 1739 #endif 1740 s = idebus_active_if(bus); 1741 /* ignore commands to non existent slave */ 1742 if (s != bus->ifs && !s->bs) 1743 return; 1744 1745 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */ 1746 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET) 1747 return; 1748 1749 if (!ide_cmd_permitted(s, val)) { 1750 ide_abort_command(s); 1751 ide_set_irq(s->bus); 1752 return; 1753 } 1754 1755 s->status = READY_STAT | BUSY_STAT; 1756 s->error = 0; 1757 1758 complete = ide_cmd_table[val].handler(s, val); 1759 if (complete) { 1760 s->status &= ~BUSY_STAT; 1761 assert(!!s->error == !!(s->status & ERR_STAT)); 1762 1763 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) { 1764 s->status |= SEEK_STAT; 1765 } 1766 1767 ide_set_irq(s->bus); 1768 } 1769 } 1770 1771 uint32_t ide_ioport_read(void *opaque, uint32_t addr1) 1772 { 1773 IDEBus *bus = opaque; 1774 IDEState *s = idebus_active_if(bus); 1775 uint32_t addr; 1776 int ret, hob; 1777 1778 addr = addr1 & 7; 1779 /* FIXME: HOB readback uses bit 7, but it's always set right now */ 1780 //hob = s->select & (1 << 7); 1781 hob = 0; 1782 switch(addr) { 1783 case 0: 1784 ret = 0xff; 1785 break; 1786 case 1: 1787 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || 1788 (s != bus->ifs && !s->bs)) 1789 ret = 0; 1790 else if (!hob) 1791 ret = s->error; 1792 else 1793 ret = s->hob_feature; 1794 break; 1795 case 2: 1796 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1797 ret = 0; 1798 else if (!hob) 1799 ret = s->nsector & 0xff; 1800 else 1801 ret = s->hob_nsector; 1802 break; 1803 case 3: 1804 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1805 ret = 0; 1806 else if (!hob) 1807 ret = s->sector; 1808 else 1809 ret = s->hob_sector; 1810 break; 1811 case 4: 1812 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1813 ret = 0; 1814 else if (!hob) 1815 ret = s->lcyl; 1816 else 1817 ret = s->hob_lcyl; 1818 break; 1819 case 5: 1820 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1821 ret = 0; 1822 else if (!hob) 1823 ret = s->hcyl; 1824 else 1825 ret = s->hob_hcyl; 1826 break; 1827 case 6: 1828 if (!bus->ifs[0].bs && !bus->ifs[1].bs) 1829 ret = 0; 1830 else 1831 ret = s->select; 1832 break; 1833 default: 1834 case 7: 1835 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || 1836 (s != bus->ifs && !s->bs)) 1837 ret = 0; 1838 else 1839 ret = s->status; 1840 qemu_irq_lower(bus->irq); 1841 break; 1842 } 1843 #ifdef DEBUG_IDE 1844 printf("ide: read addr=0x%x val=%02x\n", addr1, ret); 1845 #endif 1846 return ret; 1847 } 1848 1849 uint32_t ide_status_read(void *opaque, uint32_t addr) 1850 { 1851 IDEBus *bus = opaque; 1852 IDEState *s = idebus_active_if(bus); 1853 int ret; 1854 1855 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) || 1856 (s != bus->ifs && !s->bs)) 1857 ret = 0; 1858 else 1859 ret = s->status; 1860 #ifdef DEBUG_IDE 1861 printf("ide: read status addr=0x%x val=%02x\n", addr, ret); 1862 #endif 1863 return ret; 1864 } 1865 1866 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) 1867 { 1868 IDEBus *bus = opaque; 1869 IDEState *s; 1870 int i; 1871 1872 #ifdef DEBUG_IDE 1873 printf("ide: write control addr=0x%x val=%02x\n", addr, val); 1874 #endif 1875 /* common for both drives */ 1876 if (!(bus->cmd & IDE_CMD_RESET) && 1877 (val & IDE_CMD_RESET)) { 1878 /* reset low to high */ 1879 for(i = 0;i < 2; i++) { 1880 s = &bus->ifs[i]; 1881 s->status = BUSY_STAT | SEEK_STAT; 1882 s->error = 0x01; 1883 } 1884 } else if ((bus->cmd & IDE_CMD_RESET) && 1885 !(val & IDE_CMD_RESET)) { 1886 /* high to low */ 1887 for(i = 0;i < 2; i++) { 1888 s = &bus->ifs[i]; 1889 if (s->drive_kind == IDE_CD) 1890 s->status = 0x00; /* NOTE: READY is _not_ set */ 1891 else 1892 s->status = READY_STAT | SEEK_STAT; 1893 ide_set_signature(s); 1894 } 1895 } 1896 1897 bus->cmd = val; 1898 } 1899 1900 /* 1901 * Returns true if the running PIO transfer is a PIO out (i.e. data is 1902 * transferred from the device to the guest), false if it's a PIO in 1903 */ 1904 static bool ide_is_pio_out(IDEState *s) 1905 { 1906 if (s->end_transfer_func == ide_sector_write || 1907 s->end_transfer_func == ide_atapi_cmd) { 1908 return false; 1909 } else if (s->end_transfer_func == ide_sector_read || 1910 s->end_transfer_func == ide_transfer_stop || 1911 s->end_transfer_func == ide_atapi_cmd_reply_end || 1912 s->end_transfer_func == ide_dummy_transfer_stop) { 1913 return true; 1914 } 1915 1916 abort(); 1917 } 1918 1919 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val) 1920 { 1921 IDEBus *bus = opaque; 1922 IDEState *s = idebus_active_if(bus); 1923 uint8_t *p; 1924 1925 /* PIO data access allowed only when DRQ bit is set. The result of a write 1926 * during PIO out is indeterminate, just ignore it. */ 1927 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { 1928 return; 1929 } 1930 1931 p = s->data_ptr; 1932 *(uint16_t *)p = le16_to_cpu(val); 1933 p += 2; 1934 s->data_ptr = p; 1935 if (p >= s->data_end) 1936 s->end_transfer_func(s); 1937 } 1938 1939 uint32_t ide_data_readw(void *opaque, uint32_t addr) 1940 { 1941 IDEBus *bus = opaque; 1942 IDEState *s = idebus_active_if(bus); 1943 uint8_t *p; 1944 int ret; 1945 1946 /* PIO data access allowed only when DRQ bit is set. The result of a read 1947 * during PIO in is indeterminate, return 0 and don't move forward. */ 1948 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { 1949 return 0; 1950 } 1951 1952 p = s->data_ptr; 1953 ret = cpu_to_le16(*(uint16_t *)p); 1954 p += 2; 1955 s->data_ptr = p; 1956 if (p >= s->data_end) 1957 s->end_transfer_func(s); 1958 return ret; 1959 } 1960 1961 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val) 1962 { 1963 IDEBus *bus = opaque; 1964 IDEState *s = idebus_active_if(bus); 1965 uint8_t *p; 1966 1967 /* PIO data access allowed only when DRQ bit is set. The result of a write 1968 * during PIO out is indeterminate, just ignore it. */ 1969 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) { 1970 return; 1971 } 1972 1973 p = s->data_ptr; 1974 *(uint32_t *)p = le32_to_cpu(val); 1975 p += 4; 1976 s->data_ptr = p; 1977 if (p >= s->data_end) 1978 s->end_transfer_func(s); 1979 } 1980 1981 uint32_t ide_data_readl(void *opaque, uint32_t addr) 1982 { 1983 IDEBus *bus = opaque; 1984 IDEState *s = idebus_active_if(bus); 1985 uint8_t *p; 1986 int ret; 1987 1988 /* PIO data access allowed only when DRQ bit is set. The result of a read 1989 * during PIO in is indeterminate, return 0 and don't move forward. */ 1990 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) { 1991 return 0; 1992 } 1993 1994 p = s->data_ptr; 1995 ret = cpu_to_le32(*(uint32_t *)p); 1996 p += 4; 1997 s->data_ptr = p; 1998 if (p >= s->data_end) 1999 s->end_transfer_func(s); 2000 return ret; 2001 } 2002 2003 static void ide_dummy_transfer_stop(IDEState *s) 2004 { 2005 s->data_ptr = s->io_buffer; 2006 s->data_end = s->io_buffer; 2007 s->io_buffer[0] = 0xff; 2008 s->io_buffer[1] = 0xff; 2009 s->io_buffer[2] = 0xff; 2010 s->io_buffer[3] = 0xff; 2011 } 2012 2013 static void ide_reset(IDEState *s) 2014 { 2015 #ifdef DEBUG_IDE 2016 printf("ide: reset\n"); 2017 #endif 2018 2019 if (s->pio_aiocb) { 2020 bdrv_aio_cancel(s->pio_aiocb); 2021 s->pio_aiocb = NULL; 2022 } 2023 2024 if (s->drive_kind == IDE_CFATA) 2025 s->mult_sectors = 0; 2026 else 2027 s->mult_sectors = MAX_MULT_SECTORS; 2028 /* ide regs */ 2029 s->feature = 0; 2030 s->error = 0; 2031 s->nsector = 0; 2032 s->sector = 0; 2033 s->lcyl = 0; 2034 s->hcyl = 0; 2035 2036 /* lba48 */ 2037 s->hob_feature = 0; 2038 s->hob_sector = 0; 2039 s->hob_nsector = 0; 2040 s->hob_lcyl = 0; 2041 s->hob_hcyl = 0; 2042 2043 s->select = 0xa0; 2044 s->status = READY_STAT | SEEK_STAT; 2045 2046 s->lba48 = 0; 2047 2048 /* ATAPI specific */ 2049 s->sense_key = 0; 2050 s->asc = 0; 2051 s->cdrom_changed = 0; 2052 s->packet_transfer_size = 0; 2053 s->elementary_transfer_size = 0; 2054 s->io_buffer_index = 0; 2055 s->cd_sector_size = 0; 2056 s->atapi_dma = 0; 2057 s->tray_locked = 0; 2058 s->tray_open = 0; 2059 /* ATA DMA state */ 2060 s->io_buffer_size = 0; 2061 s->req_nb_sectors = 0; 2062 2063 ide_set_signature(s); 2064 /* init the transfer handler so that 0xffff is returned on data 2065 accesses */ 2066 s->end_transfer_func = ide_dummy_transfer_stop; 2067 ide_dummy_transfer_stop(s); 2068 s->media_changed = 0; 2069 } 2070 2071 void ide_bus_reset(IDEBus *bus) 2072 { 2073 bus->unit = 0; 2074 bus->cmd = 0; 2075 ide_reset(&bus->ifs[0]); 2076 ide_reset(&bus->ifs[1]); 2077 ide_clear_hob(bus); 2078 2079 /* pending async DMA */ 2080 if (bus->dma->aiocb) { 2081 #ifdef DEBUG_AIO 2082 printf("aio_cancel\n"); 2083 #endif 2084 bdrv_aio_cancel(bus->dma->aiocb); 2085 bus->dma->aiocb = NULL; 2086 } 2087 2088 /* reset dma provider too */ 2089 bus->dma->ops->reset(bus->dma); 2090 } 2091 2092 static bool ide_cd_is_tray_open(void *opaque) 2093 { 2094 return ((IDEState *)opaque)->tray_open; 2095 } 2096 2097 static bool ide_cd_is_medium_locked(void *opaque) 2098 { 2099 return ((IDEState *)opaque)->tray_locked; 2100 } 2101 2102 static const BlockDevOps ide_cd_block_ops = { 2103 .change_media_cb = ide_cd_change_cb, 2104 .eject_request_cb = ide_cd_eject_request_cb, 2105 .is_tray_open = ide_cd_is_tray_open, 2106 .is_medium_locked = ide_cd_is_medium_locked, 2107 }; 2108 2109 int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind, 2110 const char *version, const char *serial, const char *model, 2111 uint64_t wwn, 2112 uint32_t cylinders, uint32_t heads, uint32_t secs, 2113 int chs_trans) 2114 { 2115 uint64_t nb_sectors; 2116 2117 s->bs = bs; 2118 s->drive_kind = kind; 2119 2120 bdrv_get_geometry(bs, &nb_sectors); 2121 s->cylinders = cylinders; 2122 s->heads = heads; 2123 s->sectors = secs; 2124 s->chs_trans = chs_trans; 2125 s->nb_sectors = nb_sectors; 2126 s->wwn = wwn; 2127 /* The SMART values should be preserved across power cycles 2128 but they aren't. */ 2129 s->smart_enabled = 1; 2130 s->smart_autosave = 1; 2131 s->smart_errors = 0; 2132 s->smart_selftest_count = 0; 2133 if (kind == IDE_CD) { 2134 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s); 2135 bdrv_set_guest_block_size(bs, 2048); 2136 } else { 2137 if (!bdrv_is_inserted(s->bs)) { 2138 error_report("Device needs media, but drive is empty"); 2139 return -1; 2140 } 2141 if (bdrv_is_read_only(bs)) { 2142 error_report("Can't use a read-only drive"); 2143 return -1; 2144 } 2145 } 2146 if (serial) { 2147 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial); 2148 } else { 2149 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str), 2150 "QM%05d", s->drive_serial); 2151 } 2152 if (model) { 2153 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model); 2154 } else { 2155 switch (kind) { 2156 case IDE_CD: 2157 strcpy(s->drive_model_str, "QEMU DVD-ROM"); 2158 break; 2159 case IDE_CFATA: 2160 strcpy(s->drive_model_str, "QEMU MICRODRIVE"); 2161 break; 2162 default: 2163 strcpy(s->drive_model_str, "QEMU HARDDISK"); 2164 break; 2165 } 2166 } 2167 2168 if (version) { 2169 pstrcpy(s->version, sizeof(s->version), version); 2170 } else { 2171 pstrcpy(s->version, sizeof(s->version), qemu_get_version()); 2172 } 2173 2174 ide_reset(s); 2175 bdrv_iostatus_enable(bs); 2176 return 0; 2177 } 2178 2179 static void ide_init1(IDEBus *bus, int unit) 2180 { 2181 static int drive_serial = 1; 2182 IDEState *s = &bus->ifs[unit]; 2183 2184 s->bus = bus; 2185 s->unit = unit; 2186 s->drive_serial = drive_serial++; 2187 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */ 2188 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; 2189 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len); 2190 memset(s->io_buffer, 0, s->io_buffer_total_len); 2191 2192 s->smart_selftest_data = qemu_blockalign(s->bs, 512); 2193 memset(s->smart_selftest_data, 0, 512); 2194 2195 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2196 ide_sector_write_timer_cb, s); 2197 } 2198 2199 static void ide_nop_start(IDEDMA *dma, IDEState *s, 2200 BlockDriverCompletionFunc *cb) 2201 { 2202 } 2203 2204 static int ide_nop(IDEDMA *dma) 2205 { 2206 return 0; 2207 } 2208 2209 static int ide_nop_int(IDEDMA *dma, int x) 2210 { 2211 return 0; 2212 } 2213 2214 static void ide_nop_restart(void *opaque, int x, RunState y) 2215 { 2216 } 2217 2218 static const IDEDMAOps ide_dma_nop_ops = { 2219 .start_dma = ide_nop_start, 2220 .start_transfer = ide_nop, 2221 .prepare_buf = ide_nop_int, 2222 .rw_buf = ide_nop_int, 2223 .set_unit = ide_nop_int, 2224 .add_status = ide_nop_int, 2225 .set_inactive = ide_nop, 2226 .restart_cb = ide_nop_restart, 2227 .reset = ide_nop, 2228 }; 2229 2230 static IDEDMA ide_dma_nop = { 2231 .ops = &ide_dma_nop_ops, 2232 .aiocb = NULL, 2233 }; 2234 2235 void ide_init2(IDEBus *bus, qemu_irq irq) 2236 { 2237 int i; 2238 2239 for(i = 0; i < 2; i++) { 2240 ide_init1(bus, i); 2241 ide_reset(&bus->ifs[i]); 2242 } 2243 bus->irq = irq; 2244 bus->dma = &ide_dma_nop; 2245 } 2246 2247 static const MemoryRegionPortio ide_portio_list[] = { 2248 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write }, 2249 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew }, 2250 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel }, 2251 PORTIO_END_OF_LIST(), 2252 }; 2253 2254 static const MemoryRegionPortio ide_portio2_list[] = { 2255 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write }, 2256 PORTIO_END_OF_LIST(), 2257 }; 2258 2259 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2) 2260 { 2261 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA 2262 bridge has been setup properly to always register with ISA. */ 2263 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide"); 2264 2265 if (iobase2) { 2266 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide"); 2267 } 2268 } 2269 2270 static bool is_identify_set(void *opaque, int version_id) 2271 { 2272 IDEState *s = opaque; 2273 2274 return s->identify_set != 0; 2275 } 2276 2277 static EndTransferFunc* transfer_end_table[] = { 2278 ide_sector_read, 2279 ide_sector_write, 2280 ide_transfer_stop, 2281 ide_atapi_cmd_reply_end, 2282 ide_atapi_cmd, 2283 ide_dummy_transfer_stop, 2284 }; 2285 2286 static int transfer_end_table_idx(EndTransferFunc *fn) 2287 { 2288 int i; 2289 2290 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++) 2291 if (transfer_end_table[i] == fn) 2292 return i; 2293 2294 return -1; 2295 } 2296 2297 static int ide_drive_post_load(void *opaque, int version_id) 2298 { 2299 IDEState *s = opaque; 2300 2301 if (s->identify_set) { 2302 bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5))); 2303 } 2304 return 0; 2305 } 2306 2307 static int ide_drive_pio_post_load(void *opaque, int version_id) 2308 { 2309 IDEState *s = opaque; 2310 2311 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) { 2312 return -EINVAL; 2313 } 2314 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx]; 2315 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset; 2316 s->data_end = s->data_ptr + s->cur_io_buffer_len; 2317 2318 return 0; 2319 } 2320 2321 static void ide_drive_pio_pre_save(void *opaque) 2322 { 2323 IDEState *s = opaque; 2324 int idx; 2325 2326 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer; 2327 s->cur_io_buffer_len = s->data_end - s->data_ptr; 2328 2329 idx = transfer_end_table_idx(s->end_transfer_func); 2330 if (idx == -1) { 2331 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n", 2332 __func__); 2333 s->end_transfer_fn_idx = 2; 2334 } else { 2335 s->end_transfer_fn_idx = idx; 2336 } 2337 } 2338 2339 static bool ide_drive_pio_state_needed(void *opaque) 2340 { 2341 IDEState *s = opaque; 2342 2343 return ((s->status & DRQ_STAT) != 0) 2344 || (s->bus->error_status & BM_STATUS_PIO_RETRY); 2345 } 2346 2347 static bool ide_tray_state_needed(void *opaque) 2348 { 2349 IDEState *s = opaque; 2350 2351 return s->tray_open || s->tray_locked; 2352 } 2353 2354 static bool ide_atapi_gesn_needed(void *opaque) 2355 { 2356 IDEState *s = opaque; 2357 2358 return s->events.new_media || s->events.eject_request; 2359 } 2360 2361 static bool ide_error_needed(void *opaque) 2362 { 2363 IDEBus *bus = opaque; 2364 2365 return (bus->error_status != 0); 2366 } 2367 2368 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */ 2369 static const VMStateDescription vmstate_ide_atapi_gesn_state = { 2370 .name ="ide_drive/atapi/gesn_state", 2371 .version_id = 1, 2372 .minimum_version_id = 1, 2373 .fields = (VMStateField[]) { 2374 VMSTATE_BOOL(events.new_media, IDEState), 2375 VMSTATE_BOOL(events.eject_request, IDEState), 2376 VMSTATE_END_OF_LIST() 2377 } 2378 }; 2379 2380 static const VMStateDescription vmstate_ide_tray_state = { 2381 .name = "ide_drive/tray_state", 2382 .version_id = 1, 2383 .minimum_version_id = 1, 2384 .fields = (VMStateField[]) { 2385 VMSTATE_BOOL(tray_open, IDEState), 2386 VMSTATE_BOOL(tray_locked, IDEState), 2387 VMSTATE_END_OF_LIST() 2388 } 2389 }; 2390 2391 static const VMStateDescription vmstate_ide_drive_pio_state = { 2392 .name = "ide_drive/pio_state", 2393 .version_id = 1, 2394 .minimum_version_id = 1, 2395 .pre_save = ide_drive_pio_pre_save, 2396 .post_load = ide_drive_pio_post_load, 2397 .fields = (VMStateField[]) { 2398 VMSTATE_INT32(req_nb_sectors, IDEState), 2399 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1, 2400 vmstate_info_uint8, uint8_t), 2401 VMSTATE_INT32(cur_io_buffer_offset, IDEState), 2402 VMSTATE_INT32(cur_io_buffer_len, IDEState), 2403 VMSTATE_UINT8(end_transfer_fn_idx, IDEState), 2404 VMSTATE_INT32(elementary_transfer_size, IDEState), 2405 VMSTATE_INT32(packet_transfer_size, IDEState), 2406 VMSTATE_END_OF_LIST() 2407 } 2408 }; 2409 2410 const VMStateDescription vmstate_ide_drive = { 2411 .name = "ide_drive", 2412 .version_id = 3, 2413 .minimum_version_id = 0, 2414 .post_load = ide_drive_post_load, 2415 .fields = (VMStateField[]) { 2416 VMSTATE_INT32(mult_sectors, IDEState), 2417 VMSTATE_INT32(identify_set, IDEState), 2418 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set), 2419 VMSTATE_UINT8(feature, IDEState), 2420 VMSTATE_UINT8(error, IDEState), 2421 VMSTATE_UINT32(nsector, IDEState), 2422 VMSTATE_UINT8(sector, IDEState), 2423 VMSTATE_UINT8(lcyl, IDEState), 2424 VMSTATE_UINT8(hcyl, IDEState), 2425 VMSTATE_UINT8(hob_feature, IDEState), 2426 VMSTATE_UINT8(hob_sector, IDEState), 2427 VMSTATE_UINT8(hob_nsector, IDEState), 2428 VMSTATE_UINT8(hob_lcyl, IDEState), 2429 VMSTATE_UINT8(hob_hcyl, IDEState), 2430 VMSTATE_UINT8(select, IDEState), 2431 VMSTATE_UINT8(status, IDEState), 2432 VMSTATE_UINT8(lba48, IDEState), 2433 VMSTATE_UINT8(sense_key, IDEState), 2434 VMSTATE_UINT8(asc, IDEState), 2435 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3), 2436 VMSTATE_END_OF_LIST() 2437 }, 2438 .subsections = (VMStateSubsection []) { 2439 { 2440 .vmsd = &vmstate_ide_drive_pio_state, 2441 .needed = ide_drive_pio_state_needed, 2442 }, { 2443 .vmsd = &vmstate_ide_tray_state, 2444 .needed = ide_tray_state_needed, 2445 }, { 2446 .vmsd = &vmstate_ide_atapi_gesn_state, 2447 .needed = ide_atapi_gesn_needed, 2448 }, { 2449 /* empty */ 2450 } 2451 } 2452 }; 2453 2454 static const VMStateDescription vmstate_ide_error_status = { 2455 .name ="ide_bus/error", 2456 .version_id = 1, 2457 .minimum_version_id = 1, 2458 .fields = (VMStateField[]) { 2459 VMSTATE_INT32(error_status, IDEBus), 2460 VMSTATE_END_OF_LIST() 2461 } 2462 }; 2463 2464 const VMStateDescription vmstate_ide_bus = { 2465 .name = "ide_bus", 2466 .version_id = 1, 2467 .minimum_version_id = 1, 2468 .fields = (VMStateField[]) { 2469 VMSTATE_UINT8(cmd, IDEBus), 2470 VMSTATE_UINT8(unit, IDEBus), 2471 VMSTATE_END_OF_LIST() 2472 }, 2473 .subsections = (VMStateSubsection []) { 2474 { 2475 .vmsd = &vmstate_ide_error_status, 2476 .needed = ide_error_needed, 2477 }, { 2478 /* empty */ 2479 } 2480 } 2481 }; 2482 2483 void ide_drive_get(DriveInfo **hd, int max_bus) 2484 { 2485 int i; 2486 2487 if (drive_get_max_bus(IF_IDE) >= max_bus) { 2488 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus); 2489 exit(1); 2490 } 2491 2492 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) { 2493 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); 2494 } 2495 } 2496