1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #ifndef HW_IDE_AHCI_INTERNAL_H 25 #define HW_IDE_AHCI_INTERNAL_H 26 27 #include "hw/ide/ahci.h" 28 #include "hw/sysbus.h" 29 30 #define AHCI_MEM_BAR_SIZE 0x1000 31 #define AHCI_MAX_PORTS 32 32 #define AHCI_MAX_SG 168 /* hardware max is 64K */ 33 #define AHCI_DMA_BOUNDARY 0xffffffff 34 #define AHCI_USE_CLUSTERING 0 35 #define AHCI_MAX_CMDS 32 36 #define AHCI_CMD_SZ 32 37 #define AHCI_CMD_SLOT_SZ (AHCI_MAX_CMDS * AHCI_CMD_SZ) 38 #define AHCI_RX_FIS_SZ 256 39 #define AHCI_CMD_TBL_CDB 0x40 40 #define AHCI_CMD_TBL_HDR_SZ 0x80 41 #define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16)) 42 #define AHCI_CMD_TBL_AR_SZ (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS) 43 #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \ 44 AHCI_RX_FIS_SZ) 45 46 #define AHCI_IRQ_ON_SG (1U << 31) 47 #define AHCI_CMD_ATAPI (1 << 5) 48 #define AHCI_CMD_WRITE (1 << 6) 49 #define AHCI_CMD_PREFETCH (1 << 7) 50 #define AHCI_CMD_RESET (1 << 8) 51 #define AHCI_CMD_CLR_BUSY (1 << 10) 52 53 #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ 54 #define RX_FIS_SDB 0x58 /* offset of SDB FIS data */ 55 #define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */ 56 57 /* global controller registers */ 58 enum AHCIHostReg { 59 AHCI_HOST_REG_CAP = 0, /* CAP: host capabilities */ 60 AHCI_HOST_REG_CTL = 1, /* GHC: global host control */ 61 AHCI_HOST_REG_IRQ_STAT = 2, /* IS: interrupt status */ 62 AHCI_HOST_REG_PORTS_IMPL = 3, /* PI: bitmap of implemented ports */ 63 AHCI_HOST_REG_VERSION = 4, /* VS: AHCI spec. version compliancy */ 64 AHCI_HOST_REG_CCC_CTL = 5, /* CCC_CTL: CCC Control */ 65 AHCI_HOST_REG_CCC_PORTS = 6, /* CCC_PORTS: CCC Ports */ 66 AHCI_HOST_REG_EM_LOC = 7, /* EM_LOC: Enclosure Mgmt Location */ 67 AHCI_HOST_REG_EM_CTL = 8, /* EM_CTL: Enclosure Mgmt Control */ 68 AHCI_HOST_REG_CAP2 = 9, /* CAP2: host capabilities, extended */ 69 AHCI_HOST_REG_BOHC = 10, /* BOHC: firmare/os handoff ctrl & status */ 70 AHCI_HOST_REG__COUNT = 11 71 }; 72 73 /* HOST_CTL bits */ 74 #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */ 75 #define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */ 76 #define HOST_CTL_AHCI_EN (1U << 31) /* AHCI enabled */ 77 78 /* HOST_CAP bits */ 79 #define HOST_CAP_SSC (1 << 14) /* Slumber capable */ 80 #define HOST_CAP_AHCI (1 << 18) /* AHCI only */ 81 #define HOST_CAP_CLO (1 << 24) /* Command List Override support */ 82 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */ 83 #define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */ 84 #define HOST_CAP_64 (1U << 31) /* PCI DAC (64-bit DMA) support */ 85 86 /* registers for each SATA port */ 87 enum AHCIPortReg { 88 AHCI_PORT_REG_LST_ADDR = 0, /* PxCLB: command list DMA addr */ 89 AHCI_PORT_REG_LST_ADDR_HI = 1, /* PxCLBU: command list DMA addr hi */ 90 AHCI_PORT_REG_FIS_ADDR = 2, /* PxFB: FIS rx buf addr */ 91 AHCI_PORT_REG_FIS_ADDR_HI = 3, /* PxFBU: FIX rx buf addr hi */ 92 AHCI_PORT_REG_IRQ_STAT = 4, /* PxIS: interrupt status */ 93 AHCI_PORT_REG_IRQ_MASK = 5, /* PxIE: interrupt enable/disable mask */ 94 AHCI_PORT_REG_CMD = 6, /* PxCMD: port command */ 95 /* RESERVED */ 96 AHCI_PORT_REG_TFDATA = 8, /* PxTFD: taskfile data */ 97 AHCI_PORT_REG_SIG = 9, /* PxSIG: device TF signature */ 98 AHCI_PORT_REG_SCR_STAT = 10, /* PxSSTS: SATA phy register: SStatus */ 99 AHCI_PORT_REG_SCR_CTL = 11, /* PxSCTL: SATA phy register: SControl */ 100 AHCI_PORT_REG_SCR_ERR = 12, /* PxSERR: SATA phy register: SError */ 101 AHCI_PORT_REG_SCR_ACT = 13, /* PxSACT: SATA phy register: SActive */ 102 AHCI_PORT_REG_CMD_ISSUE = 14, /* PxCI: command issue */ 103 AHCI_PORT_REG_SCR_NOTIF = 15, /* PxSNTF: SATA phy register: SNotification */ 104 AHCI_PORT_REG_FIS_CTL = 16, /* PxFBS: Port multiplier switching ctl */ 105 AHCI_PORT_REG_DEV_SLEEP = 17, /* PxDEVSLP: device sleep control */ 106 /* RESERVED */ 107 AHCI_PORT_REG_VENDOR_1 = 28, /* PxVS: Vendor Specific */ 108 AHCI_PORT_REG_VENDOR_2 = 29, 109 AHCI_PORT_REG_VENDOR_3 = 30, 110 AHCI_PORT_REG_VENDOR_4 = 31, 111 AHCI_PORT_REG__COUNT = 32 112 }; 113 114 /* Port interrupt bit descriptors */ 115 enum AHCIPortIRQ { 116 AHCI_PORT_IRQ_BIT_DHRS = 0, 117 AHCI_PORT_IRQ_BIT_PSS = 1, 118 AHCI_PORT_IRQ_BIT_DSS = 2, 119 AHCI_PORT_IRQ_BIT_SDBS = 3, 120 AHCI_PORT_IRQ_BIT_UFS = 4, 121 AHCI_PORT_IRQ_BIT_DPS = 5, 122 AHCI_PORT_IRQ_BIT_PCS = 6, 123 AHCI_PORT_IRQ_BIT_DMPS = 7, 124 /* RESERVED */ 125 AHCI_PORT_IRQ_BIT_PRCS = 22, 126 AHCI_PORT_IRQ_BIT_IPMS = 23, 127 AHCI_PORT_IRQ_BIT_OFS = 24, 128 /* RESERVED */ 129 AHCI_PORT_IRQ_BIT_INFS = 26, 130 AHCI_PORT_IRQ_BIT_IFS = 27, 131 AHCI_PORT_IRQ_BIT_HBDS = 28, 132 AHCI_PORT_IRQ_BIT_HBFS = 29, 133 AHCI_PORT_IRQ_BIT_TFES = 30, 134 AHCI_PORT_IRQ_BIT_CPDS = 31, 135 AHCI_PORT_IRQ__COUNT = 32 136 }; 137 138 139 /* PORT_IRQ_{STAT,MASK} bits */ 140 #define PORT_IRQ_COLD_PRES (1U << 31) /* cold presence detect */ 141 #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ 142 #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ 143 #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ 144 #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ 145 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ 146 /* reserved */ 147 #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ 148 #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ 149 #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ 150 /* reserved */ 151 #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ 152 #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ 153 #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ 154 #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ 155 #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ 156 #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ 157 #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ 158 #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ 159 160 #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \ 161 PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \ 162 PORT_IRQ_UNK_FIS) 163 #define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \ 164 PORT_IRQ_HBUS_DATA_ERR) 165 #define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \ 166 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \ 167 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS) 168 169 /* PORT_CMD bits */ 170 #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ 171 #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ 172 #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ 173 #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ 174 #define PORT_CMD_CLO (1 << 3) /* Command list override */ 175 #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ 176 #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ 177 #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ 178 179 #define PORT_CMD_ICC_MASK (0xfU << 28) /* i/f ICC state mask */ 180 #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ 181 #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ 182 #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ 183 184 #define PORT_CMD_RO_MASK 0x007dffe0 /* Which CMD bits are read only? */ 185 186 /* ap->flags bits */ 187 #define AHCI_FLAG_NO_NCQ (1 << 24) 188 #define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25) /* ignore IRQ_IF_ERR */ 189 #define AHCI_FLAG_HONOR_PI (1 << 26) /* honor PORTS_IMPL */ 190 #define AHCI_FLAG_IGN_SERR_INTERNAL (1 << 27) /* ignore SERR_INTERNAL */ 191 #define AHCI_FLAG_32BIT_ONLY (1 << 28) /* force 32bit */ 192 193 #define ATA_SRST (1 << 2) /* software reset */ 194 195 #define STATE_RUN 0 196 #define STATE_RESET 1 197 198 #define SATA_SCR_SSTATUS_DET_NODEV 0x0 199 #define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3 200 201 #define SATA_SCR_SSTATUS_SPD_NODEV 0x00 202 #define SATA_SCR_SSTATUS_SPD_GEN1 0x10 203 204 #define SATA_SCR_SSTATUS_IPM_NODEV 0x000 205 #define SATA_SCR_SSTATUS_IPM_ACTIVE 0X100 206 207 #define AHCI_SCR_SCTL_DET 0xf 208 209 #define SATA_FIS_TYPE_REGISTER_H2D 0x27 210 #define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80 211 #define SATA_FIS_TYPE_REGISTER_D2H 0x34 212 #define SATA_FIS_TYPE_PIO_SETUP 0x5f 213 #define SATA_FIS_TYPE_SDB 0xA1 214 215 #define AHCI_CMD_HDR_CMD_FIS_LEN 0x1f 216 #define AHCI_CMD_HDR_PRDT_LEN 16 217 218 #define SATA_SIGNATURE_CDROM 0xeb140101 219 #define SATA_SIGNATURE_DISK 0x00000101 220 221 #define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x2c 222 223 #define AHCI_PORT_REGS_START_ADDR 0x100 224 #define AHCI_PORT_ADDR_OFFSET_MASK 0x7f 225 #define AHCI_PORT_ADDR_OFFSET_LEN 0x80 226 227 #define AHCI_NUM_COMMAND_SLOTS 31 228 #define AHCI_SUPPORTED_SPEED 20 229 #define AHCI_SUPPORTED_SPEED_GEN1 1 230 #define AHCI_VERSION_1_0 0x10000 231 232 #define AHCI_PROGMODE_MAJOR_REV_1 1 233 234 #define AHCI_COMMAND_TABLE_ACMD 0x40 235 236 #define AHCI_PRDT_SIZE_MASK 0x3fffff 237 238 #define IDE_FEATURE_DMA 1 239 240 #define READ_FPDMA_QUEUED 0x60 241 #define WRITE_FPDMA_QUEUED 0x61 242 #define NCQ_NON_DATA 0x63 243 #define RECEIVE_FPDMA_QUEUED 0x65 244 #define SEND_FPDMA_QUEUED 0x64 245 246 #define NCQ_FIS_FUA_MASK 0x80 247 #define NCQ_FIS_RARC_MASK 0x01 248 249 #define RES_FIS_DSFIS 0x00 250 #define RES_FIS_PSFIS 0x20 251 #define RES_FIS_RFIS 0x40 252 #define RES_FIS_SDBFIS 0x58 253 #define RES_FIS_UFIS 0x60 254 255 #define SATA_CAP_SIZE 0x8 256 #define SATA_CAP_REV 0x2 257 #define SATA_CAP_BAR 0x4 258 259 typedef struct AHCIPortRegs { 260 uint32_t lst_addr; 261 uint32_t lst_addr_hi; 262 uint32_t fis_addr; 263 uint32_t fis_addr_hi; 264 uint32_t irq_stat; 265 uint32_t irq_mask; 266 uint32_t cmd; 267 uint32_t unused0; 268 uint32_t tfdata; 269 uint32_t sig; 270 uint32_t scr_stat; 271 uint32_t scr_ctl; 272 uint32_t scr_err; 273 uint32_t scr_act; 274 uint32_t cmd_issue; 275 uint32_t reserved; 276 } AHCIPortRegs; 277 278 typedef struct AHCICmdHdr { 279 uint16_t opts; 280 uint16_t prdtl; 281 uint32_t status; 282 uint64_t tbl_addr; 283 uint32_t reserved[4]; 284 } QEMU_PACKED AHCICmdHdr; 285 286 typedef struct AHCI_SG { 287 uint64_t addr; 288 uint32_t reserved; 289 uint32_t flags_size; 290 } QEMU_PACKED AHCI_SG; 291 292 typedef struct NCQTransferState { 293 AHCIDevice *drive; 294 BlockAIOCB *aiocb; 295 AHCICmdHdr *cmdh; 296 QEMUSGList sglist; 297 BlockAcctCookie acct; 298 uint32_t sector_count; 299 uint64_t lba; 300 uint8_t tag; 301 uint8_t cmd; 302 uint8_t slot; 303 bool used; 304 bool halt; 305 } NCQTransferState; 306 307 struct AHCIDevice { 308 IDEDMA dma; 309 IDEBus port; 310 int port_no; 311 uint32_t port_state; 312 uint32_t finished; 313 AHCIPortRegs port_regs; 314 struct AHCIState *hba; 315 QEMUBH *check_bh; 316 uint8_t *lst; 317 uint8_t *res_fis; 318 bool done_first_drq; 319 int32_t busy_slot; 320 bool init_d2h_sent; 321 AHCICmdHdr *cur_cmd; 322 NCQTransferState ncq_tfs[AHCI_MAX_CMDS]; 323 }; 324 325 struct AHCIPCIState { 326 /*< private >*/ 327 PCIDevice parent_obj; 328 /*< public >*/ 329 330 AHCIState ahci; 331 }; 332 333 #define ICH_AHCI(obj) \ 334 OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI) 335 336 extern const VMStateDescription vmstate_ahci; 337 338 #define VMSTATE_AHCI(_field, _state) { \ 339 .name = (stringify(_field)), \ 340 .size = sizeof(AHCIState), \ 341 .vmsd = &vmstate_ahci, \ 342 .flags = VMS_STRUCT, \ 343 .offset = vmstate_offset_value(_state, _field, AHCIState), \ 344 } 345 346 /** 347 * NCQFrame is the same as a Register H2D FIS (described in SATA 3.2), 348 * but some fields have been re-mapped and re-purposed, as seen in 349 * SATA 3.2 section 13.6.4.1 ("READ FPDMA QUEUED") 350 * 351 * cmd_fis[3], feature 7:0, becomes sector count 7:0. 352 * cmd_fis[7], device 7:0, uses bit 7 as the Force Unit Access bit. 353 * cmd_fis[11], feature 15:8, becomes sector count 15:8. 354 * cmd_fis[12], count 7:0, becomes the NCQ TAG (7:3) and RARC bit (0) 355 * cmd_fis[13], count 15:8, becomes the priority value (7:6) 356 * bytes 16-19 become an le32 "auxiliary" field. 357 */ 358 typedef struct NCQFrame { 359 uint8_t fis_type; 360 uint8_t c; 361 uint8_t command; 362 uint8_t sector_count_low; /* (feature 7:0) */ 363 uint8_t lba0; 364 uint8_t lba1; 365 uint8_t lba2; 366 uint8_t fua; /* (device 7:0) */ 367 uint8_t lba3; 368 uint8_t lba4; 369 uint8_t lba5; 370 uint8_t sector_count_high; /* (feature 15:8) */ 371 uint8_t tag; /* (count 0:7) */ 372 uint8_t prio; /* (count 15:8) */ 373 uint8_t icc; 374 uint8_t control; 375 uint8_t aux0; 376 uint8_t aux1; 377 uint8_t aux2; 378 uint8_t aux3; 379 } QEMU_PACKED NCQFrame; 380 381 typedef struct SDBFIS { 382 uint8_t type; 383 uint8_t flags; 384 uint8_t status; 385 uint8_t error; 386 uint32_t payload; 387 } QEMU_PACKED SDBFIS; 388 389 void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports); 390 void ahci_init(AHCIState *s, DeviceState *qdev); 391 void ahci_uninit(AHCIState *s); 392 393 void ahci_reset(AHCIState *s); 394 395 #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI) 396 397 #endif /* HW_IDE_AHCI_H */ 398