1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include <hw/hw.h> 25 #include <hw/pci/msi.h> 26 #include <hw/i386/pc.h> 27 #include <hw/pci/pci.h> 28 #include <hw/sysbus.h> 29 30 #include "monitor/monitor.h" 31 #include "sysemu/dma.h" 32 #include "internal.h" 33 #include <hw/ide/pci.h> 34 #include <hw/ide/ahci.h> 35 36 /* #define DEBUG_AHCI */ 37 38 #ifdef DEBUG_AHCI 39 #define DPRINTF(port, fmt, ...) \ 40 do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \ 41 fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 42 #else 43 #define DPRINTF(port, fmt, ...) do {} while(0) 44 #endif 45 46 static void check_cmd(AHCIState *s, int port); 47 static int handle_cmd(AHCIState *s,int port,int slot); 48 static void ahci_reset_port(AHCIState *s, int port); 49 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis); 50 static void ahci_init_d2h(AHCIDevice *ad); 51 52 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 53 { 54 uint32_t val; 55 AHCIPortRegs *pr; 56 pr = &s->dev[port].port_regs; 57 58 switch (offset) { 59 case PORT_LST_ADDR: 60 val = pr->lst_addr; 61 break; 62 case PORT_LST_ADDR_HI: 63 val = pr->lst_addr_hi; 64 break; 65 case PORT_FIS_ADDR: 66 val = pr->fis_addr; 67 break; 68 case PORT_FIS_ADDR_HI: 69 val = pr->fis_addr_hi; 70 break; 71 case PORT_IRQ_STAT: 72 val = pr->irq_stat; 73 break; 74 case PORT_IRQ_MASK: 75 val = pr->irq_mask; 76 break; 77 case PORT_CMD: 78 val = pr->cmd; 79 break; 80 case PORT_TFDATA: 81 val = ((uint16_t)s->dev[port].port.ifs[0].error << 8) | 82 s->dev[port].port.ifs[0].status; 83 break; 84 case PORT_SIG: 85 val = pr->sig; 86 break; 87 case PORT_SCR_STAT: 88 if (s->dev[port].port.ifs[0].bs) { 89 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 90 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 91 } else { 92 val = SATA_SCR_SSTATUS_DET_NODEV; 93 } 94 break; 95 case PORT_SCR_CTL: 96 val = pr->scr_ctl; 97 break; 98 case PORT_SCR_ERR: 99 val = pr->scr_err; 100 break; 101 case PORT_SCR_ACT: 102 pr->scr_act &= ~s->dev[port].finished; 103 s->dev[port].finished = 0; 104 val = pr->scr_act; 105 break; 106 case PORT_CMD_ISSUE: 107 val = pr->cmd_issue; 108 break; 109 case PORT_RESERVED: 110 default: 111 val = 0; 112 } 113 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 114 return val; 115 116 } 117 118 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev) 119 { 120 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 121 PCIDevice *pci_dev = PCI_DEVICE(d); 122 123 DPRINTF(0, "raise irq\n"); 124 125 if (msi_enabled(pci_dev)) { 126 msi_notify(pci_dev, 0); 127 } else { 128 qemu_irq_raise(s->irq); 129 } 130 } 131 132 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev) 133 { 134 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 135 136 DPRINTF(0, "lower irq\n"); 137 138 if (!msi_enabled(PCI_DEVICE(d))) { 139 qemu_irq_lower(s->irq); 140 } 141 } 142 143 static void ahci_check_irq(AHCIState *s) 144 { 145 int i; 146 147 DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus); 148 149 s->control_regs.irqstatus = 0; 150 for (i = 0; i < s->ports; i++) { 151 AHCIPortRegs *pr = &s->dev[i].port_regs; 152 if (pr->irq_stat & pr->irq_mask) { 153 s->control_regs.irqstatus |= (1 << i); 154 } 155 } 156 157 if (s->control_regs.irqstatus && 158 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 159 ahci_irq_raise(s, NULL); 160 } else { 161 ahci_irq_lower(s, NULL); 162 } 163 } 164 165 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 166 int irq_type) 167 { 168 DPRINTF(d->port_no, "trigger irq %#x -> %x\n", 169 irq_type, d->port_regs.irq_mask & irq_type); 170 171 d->port_regs.irq_stat |= irq_type; 172 ahci_check_irq(s); 173 } 174 175 static void map_page(uint8_t **ptr, uint64_t addr, uint32_t wanted) 176 { 177 hwaddr len = wanted; 178 179 if (*ptr) { 180 cpu_physical_memory_unmap(*ptr, len, 1, len); 181 } 182 183 *ptr = cpu_physical_memory_map(addr, &len, 1); 184 if (len < wanted) { 185 cpu_physical_memory_unmap(*ptr, len, 1, len); 186 *ptr = NULL; 187 } 188 } 189 190 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 191 { 192 AHCIPortRegs *pr = &s->dev[port].port_regs; 193 194 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 195 switch (offset) { 196 case PORT_LST_ADDR: 197 pr->lst_addr = val; 198 map_page(&s->dev[port].lst, 199 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 200 s->dev[port].cur_cmd = NULL; 201 break; 202 case PORT_LST_ADDR_HI: 203 pr->lst_addr_hi = val; 204 map_page(&s->dev[port].lst, 205 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 206 s->dev[port].cur_cmd = NULL; 207 break; 208 case PORT_FIS_ADDR: 209 pr->fis_addr = val; 210 map_page(&s->dev[port].res_fis, 211 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 212 break; 213 case PORT_FIS_ADDR_HI: 214 pr->fis_addr_hi = val; 215 map_page(&s->dev[port].res_fis, 216 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 217 break; 218 case PORT_IRQ_STAT: 219 pr->irq_stat &= ~val; 220 ahci_check_irq(s); 221 break; 222 case PORT_IRQ_MASK: 223 pr->irq_mask = val & 0xfdc000ff; 224 ahci_check_irq(s); 225 break; 226 case PORT_CMD: 227 pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); 228 229 if (pr->cmd & PORT_CMD_START) { 230 pr->cmd |= PORT_CMD_LIST_ON; 231 } 232 233 if (pr->cmd & PORT_CMD_FIS_RX) { 234 pr->cmd |= PORT_CMD_FIS_ON; 235 } 236 237 /* XXX usually the FIS would be pending on the bus here and 238 issuing deferred until the OS enables FIS receival. 239 Instead, we only submit it once - which works in most 240 cases, but is a hack. */ 241 if ((pr->cmd & PORT_CMD_FIS_ON) && 242 !s->dev[port].init_d2h_sent) { 243 ahci_init_d2h(&s->dev[port]); 244 s->dev[port].init_d2h_sent = true; 245 } 246 247 check_cmd(s, port); 248 break; 249 case PORT_TFDATA: 250 s->dev[port].port.ifs[0].error = (val >> 8) & 0xff; 251 s->dev[port].port.ifs[0].status = val & 0xff; 252 break; 253 case PORT_SIG: 254 pr->sig = val; 255 break; 256 case PORT_SCR_STAT: 257 pr->scr_stat = val; 258 break; 259 case PORT_SCR_CTL: 260 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 261 ((val & AHCI_SCR_SCTL_DET) == 0)) { 262 ahci_reset_port(s, port); 263 } 264 pr->scr_ctl = val; 265 break; 266 case PORT_SCR_ERR: 267 pr->scr_err &= ~val; 268 break; 269 case PORT_SCR_ACT: 270 /* RW1 */ 271 pr->scr_act |= val; 272 break; 273 case PORT_CMD_ISSUE: 274 pr->cmd_issue |= val; 275 check_cmd(s, port); 276 break; 277 default: 278 break; 279 } 280 } 281 282 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, 283 unsigned size) 284 { 285 AHCIState *s = opaque; 286 uint32_t val = 0; 287 288 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 289 switch (addr) { 290 case HOST_CAP: 291 val = s->control_regs.cap; 292 break; 293 case HOST_CTL: 294 val = s->control_regs.ghc; 295 break; 296 case HOST_IRQ_STAT: 297 val = s->control_regs.irqstatus; 298 break; 299 case HOST_PORTS_IMPL: 300 val = s->control_regs.impl; 301 break; 302 case HOST_VERSION: 303 val = s->control_regs.version; 304 break; 305 } 306 307 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val); 308 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 309 (addr < (AHCI_PORT_REGS_START_ADDR + 310 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 311 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 312 addr & AHCI_PORT_ADDR_OFFSET_MASK); 313 } 314 315 return val; 316 } 317 318 319 320 static void ahci_mem_write(void *opaque, hwaddr addr, 321 uint64_t val, unsigned size) 322 { 323 AHCIState *s = opaque; 324 325 /* Only aligned reads are allowed on AHCI */ 326 if (addr & 3) { 327 fprintf(stderr, "ahci: Mis-aligned write to addr 0x" 328 TARGET_FMT_plx "\n", addr); 329 return; 330 } 331 332 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 333 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, val); 334 335 switch (addr) { 336 case HOST_CAP: /* R/WO, RO */ 337 /* FIXME handle R/WO */ 338 break; 339 case HOST_CTL: /* R/W */ 340 if (val & HOST_CTL_RESET) { 341 DPRINTF(-1, "HBA Reset\n"); 342 ahci_reset(s); 343 } else { 344 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 345 ahci_check_irq(s); 346 } 347 break; 348 case HOST_IRQ_STAT: /* R/WC, RO */ 349 s->control_regs.irqstatus &= ~val; 350 ahci_check_irq(s); 351 break; 352 case HOST_PORTS_IMPL: /* R/WO, RO */ 353 /* FIXME handle R/WO */ 354 break; 355 case HOST_VERSION: /* RO */ 356 /* FIXME report write? */ 357 break; 358 default: 359 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr); 360 } 361 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 362 (addr < (AHCI_PORT_REGS_START_ADDR + 363 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 364 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 365 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 366 } 367 368 } 369 370 static const MemoryRegionOps ahci_mem_ops = { 371 .read = ahci_mem_read, 372 .write = ahci_mem_write, 373 .endianness = DEVICE_LITTLE_ENDIAN, 374 }; 375 376 static uint64_t ahci_idp_read(void *opaque, hwaddr addr, 377 unsigned size) 378 { 379 AHCIState *s = opaque; 380 381 if (addr == s->idp_offset) { 382 /* index register */ 383 return s->idp_index; 384 } else if (addr == s->idp_offset + 4) { 385 /* data register - do memory read at location selected by index */ 386 return ahci_mem_read(opaque, s->idp_index, size); 387 } else { 388 return 0; 389 } 390 } 391 392 static void ahci_idp_write(void *opaque, hwaddr addr, 393 uint64_t val, unsigned size) 394 { 395 AHCIState *s = opaque; 396 397 if (addr == s->idp_offset) { 398 /* index register - mask off reserved bits */ 399 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 400 } else if (addr == s->idp_offset + 4) { 401 /* data register - do memory write at location selected by index */ 402 ahci_mem_write(opaque, s->idp_index, val, size); 403 } 404 } 405 406 static const MemoryRegionOps ahci_idp_ops = { 407 .read = ahci_idp_read, 408 .write = ahci_idp_write, 409 .endianness = DEVICE_LITTLE_ENDIAN, 410 }; 411 412 413 static void ahci_reg_init(AHCIState *s) 414 { 415 int i; 416 417 s->control_regs.cap = (s->ports - 1) | 418 (AHCI_NUM_COMMAND_SLOTS << 8) | 419 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 420 HOST_CAP_NCQ | HOST_CAP_AHCI; 421 422 s->control_regs.impl = (1 << s->ports) - 1; 423 424 s->control_regs.version = AHCI_VERSION_1_0; 425 426 for (i = 0; i < s->ports; i++) { 427 s->dev[i].port_state = STATE_RUN; 428 } 429 } 430 431 static void check_cmd(AHCIState *s, int port) 432 { 433 AHCIPortRegs *pr = &s->dev[port].port_regs; 434 int slot; 435 436 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 437 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 438 if ((pr->cmd_issue & (1 << slot)) && 439 !handle_cmd(s, port, slot)) { 440 pr->cmd_issue &= ~(1 << slot); 441 } 442 } 443 } 444 } 445 446 static void ahci_check_cmd_bh(void *opaque) 447 { 448 AHCIDevice *ad = opaque; 449 450 qemu_bh_delete(ad->check_bh); 451 ad->check_bh = NULL; 452 453 if ((ad->busy_slot != -1) && 454 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 455 /* no longer busy */ 456 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot); 457 ad->busy_slot = -1; 458 } 459 460 check_cmd(ad->hba, ad->port_no); 461 } 462 463 static void ahci_init_d2h(AHCIDevice *ad) 464 { 465 uint8_t init_fis[20]; 466 IDEState *ide_state = &ad->port.ifs[0]; 467 468 memset(init_fis, 0, sizeof(init_fis)); 469 470 init_fis[4] = 1; 471 init_fis[12] = 1; 472 473 if (ide_state->drive_kind == IDE_CD) { 474 init_fis[5] = ide_state->lcyl; 475 init_fis[6] = ide_state->hcyl; 476 } 477 478 ahci_write_fis_d2h(ad, init_fis); 479 } 480 481 static void ahci_reset_port(AHCIState *s, int port) 482 { 483 AHCIDevice *d = &s->dev[port]; 484 AHCIPortRegs *pr = &d->port_regs; 485 IDEState *ide_state = &d->port.ifs[0]; 486 int i; 487 488 DPRINTF(port, "reset port\n"); 489 490 ide_bus_reset(&d->port); 491 ide_state->ncq_queues = AHCI_MAX_CMDS; 492 493 pr->scr_stat = 0; 494 pr->scr_err = 0; 495 pr->scr_act = 0; 496 d->busy_slot = -1; 497 d->init_d2h_sent = false; 498 499 ide_state = &s->dev[port].port.ifs[0]; 500 if (!ide_state->bs) { 501 return; 502 } 503 504 /* reset ncq queue */ 505 for (i = 0; i < AHCI_MAX_CMDS; i++) { 506 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 507 if (!ncq_tfs->used) { 508 continue; 509 } 510 511 if (ncq_tfs->aiocb) { 512 bdrv_aio_cancel(ncq_tfs->aiocb); 513 ncq_tfs->aiocb = NULL; 514 } 515 516 /* Maybe we just finished the request thanks to bdrv_aio_cancel() */ 517 if (!ncq_tfs->used) { 518 continue; 519 } 520 521 qemu_sglist_destroy(&ncq_tfs->sglist); 522 ncq_tfs->used = 0; 523 } 524 525 s->dev[port].port_state = STATE_RUN; 526 if (!ide_state->bs) { 527 s->dev[port].port_regs.sig = 0; 528 ide_state->status = SEEK_STAT | WRERR_STAT; 529 } else if (ide_state->drive_kind == IDE_CD) { 530 s->dev[port].port_regs.sig = SATA_SIGNATURE_CDROM; 531 ide_state->lcyl = 0x14; 532 ide_state->hcyl = 0xeb; 533 DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl); 534 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 535 } else { 536 s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK; 537 ide_state->status = SEEK_STAT | WRERR_STAT; 538 } 539 540 ide_state->error = 1; 541 ahci_init_d2h(d); 542 } 543 544 static void debug_print_fis(uint8_t *fis, int cmd_len) 545 { 546 #ifdef DEBUG_AHCI 547 int i; 548 549 fprintf(stderr, "fis:"); 550 for (i = 0; i < cmd_len; i++) { 551 if ((i & 0xf) == 0) { 552 fprintf(stderr, "\n%02x:",i); 553 } 554 fprintf(stderr, "%02x ",fis[i]); 555 } 556 fprintf(stderr, "\n"); 557 #endif 558 } 559 560 static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished) 561 { 562 AHCIPortRegs *pr = &s->dev[port].port_regs; 563 IDEState *ide_state; 564 uint8_t *sdb_fis; 565 566 if (!s->dev[port].res_fis || 567 !(pr->cmd & PORT_CMD_FIS_RX)) { 568 return; 569 } 570 571 sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS]; 572 ide_state = &s->dev[port].port.ifs[0]; 573 574 /* clear memory */ 575 *(uint32_t*)sdb_fis = 0; 576 577 /* write values */ 578 sdb_fis[0] = ide_state->error; 579 sdb_fis[2] = ide_state->status & 0x77; 580 s->dev[port].finished |= finished; 581 *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished); 582 583 ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_STAT_SDBS); 584 } 585 586 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) 587 { 588 AHCIPortRegs *pr = &ad->port_regs; 589 uint8_t *d2h_fis; 590 int i; 591 dma_addr_t cmd_len = 0x80; 592 int cmd_mapped = 0; 593 594 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 595 return; 596 } 597 598 if (!cmd_fis) { 599 /* map cmd_fis */ 600 uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr); 601 cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len, 602 DMA_DIRECTION_TO_DEVICE); 603 cmd_mapped = 1; 604 } 605 606 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 607 608 d2h_fis[0] = 0x34; 609 d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0); 610 d2h_fis[2] = ad->port.ifs[0].status; 611 d2h_fis[3] = ad->port.ifs[0].error; 612 613 d2h_fis[4] = cmd_fis[4]; 614 d2h_fis[5] = cmd_fis[5]; 615 d2h_fis[6] = cmd_fis[6]; 616 d2h_fis[7] = cmd_fis[7]; 617 d2h_fis[8] = cmd_fis[8]; 618 d2h_fis[9] = cmd_fis[9]; 619 d2h_fis[10] = cmd_fis[10]; 620 d2h_fis[11] = cmd_fis[11]; 621 d2h_fis[12] = cmd_fis[12]; 622 d2h_fis[13] = cmd_fis[13]; 623 for (i = 14; i < 20; i++) { 624 d2h_fis[i] = 0; 625 } 626 627 if (d2h_fis[2] & ERR_STAT) { 628 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_TFES); 629 } 630 631 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS); 632 633 if (cmd_mapped) { 634 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len, 635 DMA_DIRECTION_TO_DEVICE, cmd_len); 636 } 637 } 638 639 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset) 640 { 641 AHCICmdHdr *cmd = ad->cur_cmd; 642 uint32_t opts = le32_to_cpu(cmd->opts); 643 uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80; 644 int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN; 645 dma_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG)); 646 dma_addr_t real_prdt_len = prdt_len; 647 uint8_t *prdt; 648 int i; 649 int r = 0; 650 int sum = 0; 651 int off_idx = -1; 652 int off_pos = -1; 653 int tbl_entry_size; 654 IDEBus *bus = &ad->port; 655 BusState *qbus = BUS(bus); 656 657 if (!sglist_alloc_hint) { 658 DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts); 659 return -1; 660 } 661 662 /* map PRDT */ 663 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, 664 DMA_DIRECTION_TO_DEVICE))){ 665 DPRINTF(ad->port_no, "map failed\n"); 666 return -1; 667 } 668 669 if (prdt_len < real_prdt_len) { 670 DPRINTF(ad->port_no, "mapped less than expected\n"); 671 r = -1; 672 goto out; 673 } 674 675 /* Get entries in the PRDT, init a qemu sglist accordingly */ 676 if (sglist_alloc_hint > 0) { 677 AHCI_SG *tbl = (AHCI_SG *)prdt; 678 sum = 0; 679 for (i = 0; i < sglist_alloc_hint; i++) { 680 /* flags_size is zero-based */ 681 tbl_entry_size = (le32_to_cpu(tbl[i].flags_size) + 1); 682 if (offset <= (sum + tbl_entry_size)) { 683 off_idx = i; 684 off_pos = offset - sum; 685 break; 686 } 687 sum += tbl_entry_size; 688 } 689 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { 690 DPRINTF(ad->port_no, "%s: Incorrect offset! " 691 "off_idx: %d, off_pos: %d\n", 692 __func__, off_idx, off_pos); 693 r = -1; 694 goto out; 695 } 696 697 qemu_sglist_init(sglist, qbus->parent, (sglist_alloc_hint - off_idx), 698 ad->hba->as); 699 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos), 700 le32_to_cpu(tbl[off_idx].flags_size) + 1 - off_pos); 701 702 for (i = off_idx + 1; i < sglist_alloc_hint; i++) { 703 /* flags_size is zero-based */ 704 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 705 le32_to_cpu(tbl[i].flags_size) + 1); 706 } 707 } 708 709 out: 710 dma_memory_unmap(ad->hba->as, prdt, prdt_len, 711 DMA_DIRECTION_TO_DEVICE, prdt_len); 712 return r; 713 } 714 715 static void ncq_cb(void *opaque, int ret) 716 { 717 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 718 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 719 720 /* Clear bit for this tag in SActive */ 721 ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag); 722 723 if (ret < 0) { 724 /* error */ 725 ide_state->error = ABRT_ERR; 726 ide_state->status = READY_STAT | ERR_STAT; 727 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); 728 } else { 729 ide_state->status = READY_STAT | SEEK_STAT; 730 } 731 732 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, 733 (1 << ncq_tfs->tag)); 734 735 DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n", 736 ncq_tfs->tag); 737 738 bdrv_acct_done(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct); 739 qemu_sglist_destroy(&ncq_tfs->sglist); 740 ncq_tfs->used = 0; 741 } 742 743 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis, 744 int slot) 745 { 746 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis; 747 uint8_t tag = ncq_fis->tag >> 3; 748 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag]; 749 750 if (ncq_tfs->used) { 751 /* error - already in use */ 752 fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag); 753 return; 754 } 755 756 ncq_tfs->used = 1; 757 ncq_tfs->drive = &s->dev[port]; 758 ncq_tfs->slot = slot; 759 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 760 ((uint64_t)ncq_fis->lba4 << 32) | 761 ((uint64_t)ncq_fis->lba3 << 24) | 762 ((uint64_t)ncq_fis->lba2 << 16) | 763 ((uint64_t)ncq_fis->lba1 << 8) | 764 (uint64_t)ncq_fis->lba0; 765 766 /* Note: We calculate the sector count, but don't currently rely on it. 767 * The total size of the DMA buffer tells us the transfer size instead. */ 768 ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) | 769 ncq_fis->sector_count_low; 770 771 DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", " 772 "drive max %"PRId64"\n", 773 ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2, 774 s->dev[port].port.ifs[0].nb_sectors - 1); 775 776 ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist, 0); 777 ncq_tfs->tag = tag; 778 779 switch(ncq_fis->command) { 780 case READ_FPDMA_QUEUED: 781 DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", " 782 "tag %d\n", 783 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 784 785 DPRINTF(port, "tag %d aio read %"PRId64"\n", 786 ncq_tfs->tag, ncq_tfs->lba); 787 788 dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 789 &ncq_tfs->sglist, BDRV_ACCT_READ); 790 ncq_tfs->aiocb = dma_bdrv_read(ncq_tfs->drive->port.ifs[0].bs, 791 &ncq_tfs->sglist, ncq_tfs->lba, 792 ncq_cb, ncq_tfs); 793 break; 794 case WRITE_FPDMA_QUEUED: 795 DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n", 796 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 797 798 DPRINTF(port, "tag %d aio write %"PRId64"\n", 799 ncq_tfs->tag, ncq_tfs->lba); 800 801 dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 802 &ncq_tfs->sglist, BDRV_ACCT_WRITE); 803 ncq_tfs->aiocb = dma_bdrv_write(ncq_tfs->drive->port.ifs[0].bs, 804 &ncq_tfs->sglist, ncq_tfs->lba, 805 ncq_cb, ncq_tfs); 806 break; 807 default: 808 DPRINTF(port, "error: tried to process non-NCQ command as NCQ\n"); 809 qemu_sglist_destroy(&ncq_tfs->sglist); 810 break; 811 } 812 } 813 814 static int handle_cmd(AHCIState *s, int port, int slot) 815 { 816 IDEState *ide_state; 817 uint32_t opts; 818 uint64_t tbl_addr; 819 AHCICmdHdr *cmd; 820 uint8_t *cmd_fis; 821 dma_addr_t cmd_len; 822 823 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 824 /* Engine currently busy, try again later */ 825 DPRINTF(port, "engine busy\n"); 826 return -1; 827 } 828 829 cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot]; 830 831 if (!s->dev[port].lst) { 832 DPRINTF(port, "error: lst not given but cmd handled"); 833 return -1; 834 } 835 836 /* remember current slot handle for later */ 837 s->dev[port].cur_cmd = cmd; 838 839 opts = le32_to_cpu(cmd->opts); 840 tbl_addr = le64_to_cpu(cmd->tbl_addr); 841 842 cmd_len = 0x80; 843 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, 844 DMA_DIRECTION_FROM_DEVICE); 845 846 if (!cmd_fis) { 847 DPRINTF(port, "error: guest passed us an invalid cmd fis\n"); 848 return -1; 849 } 850 851 /* The device we are working for */ 852 ide_state = &s->dev[port].port.ifs[0]; 853 854 if (!ide_state->bs) { 855 DPRINTF(port, "error: guest accessed unused port"); 856 goto out; 857 } 858 859 debug_print_fis(cmd_fis, 0x90); 860 //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4); 861 862 switch (cmd_fis[0]) { 863 case SATA_FIS_TYPE_REGISTER_H2D: 864 break; 865 default: 866 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 867 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 868 cmd_fis[2]); 869 goto out; 870 break; 871 } 872 873 switch (cmd_fis[1]) { 874 case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER: 875 break; 876 case 0: 877 break; 878 default: 879 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 880 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 881 cmd_fis[2]); 882 goto out; 883 break; 884 } 885 886 switch (s->dev[port].port_state) { 887 case STATE_RUN: 888 if (cmd_fis[15] & ATA_SRST) { 889 s->dev[port].port_state = STATE_RESET; 890 } 891 break; 892 case STATE_RESET: 893 if (!(cmd_fis[15] & ATA_SRST)) { 894 ahci_reset_port(s, port); 895 } 896 break; 897 } 898 899 if (cmd_fis[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER) { 900 901 /* Check for NCQ command */ 902 if ((cmd_fis[2] == READ_FPDMA_QUEUED) || 903 (cmd_fis[2] == WRITE_FPDMA_QUEUED)) { 904 process_ncq_command(s, port, cmd_fis, slot); 905 goto out; 906 } 907 908 /* Decompose the FIS */ 909 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 910 ide_state->feature = cmd_fis[3]; 911 if (!ide_state->nsector) { 912 ide_state->nsector = 256; 913 } 914 915 if (ide_state->drive_kind != IDE_CD) { 916 /* 917 * We set the sector depending on the sector defined in the FIS. 918 * Unfortunately, the spec isn't exactly obvious on this one. 919 * 920 * Apparently LBA48 commands set fis bytes 10,9,8,6,5,4 to the 921 * 48 bit sector number. ATA_CMD_READ_DMA_EXT is an example for 922 * such a command. 923 * 924 * Non-LBA48 commands however use 7[lower 4 bits],6,5,4 to define a 925 * 28-bit sector number. ATA_CMD_READ_DMA is an example for such 926 * a command. 927 * 928 * Since the spec doesn't explicitly state what each field should 929 * do, I simply assume non-used fields as reserved and OR everything 930 * together, independent of the command. 931 */ 932 ide_set_sector(ide_state, ((uint64_t)cmd_fis[10] << 40) 933 | ((uint64_t)cmd_fis[9] << 32) 934 /* This is used for LBA48 commands */ 935 | ((uint64_t)cmd_fis[8] << 24) 936 /* This is used for non-LBA48 commands */ 937 | ((uint64_t)(cmd_fis[7] & 0xf) << 24) 938 | ((uint64_t)cmd_fis[6] << 16) 939 | ((uint64_t)cmd_fis[5] << 8) 940 | cmd_fis[4]); 941 } 942 943 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 944 * table to ide_state->io_buffer 945 */ 946 if (opts & AHCI_CMD_ATAPI) { 947 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 948 ide_state->lcyl = 0x14; 949 ide_state->hcyl = 0xeb; 950 debug_print_fis(ide_state->io_buffer, 0x10); 951 ide_state->feature = IDE_FEATURE_DMA; 952 s->dev[port].done_atapi_packet = false; 953 /* XXX send PIO setup FIS */ 954 } 955 956 ide_state->error = 0; 957 958 /* Reset transferred byte counter */ 959 cmd->status = 0; 960 961 /* We're ready to process the command in FIS byte 2. */ 962 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]); 963 964 if (s->dev[port].port.ifs[0].status & READY_STAT) { 965 ahci_write_fis_d2h(&s->dev[port], cmd_fis); 966 } 967 } 968 969 out: 970 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE, 971 cmd_len); 972 973 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 974 /* async command, complete later */ 975 s->dev[port].busy_slot = slot; 976 return -1; 977 } 978 979 /* done handling the command */ 980 return 0; 981 } 982 983 /* DMA dev <-> ram */ 984 static int ahci_start_transfer(IDEDMA *dma) 985 { 986 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 987 IDEState *s = &ad->port.ifs[0]; 988 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 989 /* write == ram -> device */ 990 uint32_t opts = le32_to_cpu(ad->cur_cmd->opts); 991 int is_write = opts & AHCI_CMD_WRITE; 992 int is_atapi = opts & AHCI_CMD_ATAPI; 993 int has_sglist = 0; 994 995 if (is_atapi && !ad->done_atapi_packet) { 996 /* already prepopulated iobuffer */ 997 ad->done_atapi_packet = true; 998 goto out; 999 } 1000 1001 if (!ahci_populate_sglist(ad, &s->sg, 0)) { 1002 has_sglist = 1; 1003 } 1004 1005 DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n", 1006 is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata", 1007 has_sglist ? "" : "o"); 1008 1009 if (has_sglist && size) { 1010 if (is_write) { 1011 dma_buf_write(s->data_ptr, size, &s->sg); 1012 } else { 1013 dma_buf_read(s->data_ptr, size, &s->sg); 1014 } 1015 } 1016 1017 /* update number of transferred bytes */ 1018 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + size); 1019 1020 out: 1021 /* declare that we processed everything */ 1022 s->data_ptr = s->data_end; 1023 1024 if (has_sglist) { 1025 qemu_sglist_destroy(&s->sg); 1026 } 1027 1028 s->end_transfer_func(s); 1029 1030 if (!(s->status & DRQ_STAT)) { 1031 /* done with DMA */ 1032 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS); 1033 } 1034 1035 return 0; 1036 } 1037 1038 static void ahci_start_dma(IDEDMA *dma, IDEState *s, 1039 BlockDriverCompletionFunc *dma_cb) 1040 { 1041 #ifdef DEBUG_AHCI 1042 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1043 #endif 1044 DPRINTF(ad->port_no, "\n"); 1045 s->io_buffer_offset = 0; 1046 dma_cb(s, 0); 1047 } 1048 1049 static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write) 1050 { 1051 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1052 IDEState *s = &ad->port.ifs[0]; 1053 1054 ahci_populate_sglist(ad, &s->sg, 0); 1055 s->io_buffer_size = s->sg.size; 1056 1057 DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size); 1058 return s->io_buffer_size != 0; 1059 } 1060 1061 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) 1062 { 1063 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1064 IDEState *s = &ad->port.ifs[0]; 1065 uint8_t *p = s->io_buffer + s->io_buffer_index; 1066 int l = s->io_buffer_size - s->io_buffer_index; 1067 1068 if (ahci_populate_sglist(ad, &s->sg, s->io_buffer_offset)) { 1069 return 0; 1070 } 1071 1072 if (is_write) { 1073 dma_buf_read(p, l, &s->sg); 1074 } else { 1075 dma_buf_write(p, l, &s->sg); 1076 } 1077 1078 /* free sglist that was created in ahci_populate_sglist() */ 1079 qemu_sglist_destroy(&s->sg); 1080 1081 /* update number of transferred bytes */ 1082 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + l); 1083 s->io_buffer_index += l; 1084 s->io_buffer_offset += l; 1085 1086 DPRINTF(ad->port_no, "len=%#x\n", l); 1087 1088 return 1; 1089 } 1090 1091 static int ahci_dma_set_unit(IDEDMA *dma, int unit) 1092 { 1093 /* only a single unit per link */ 1094 return 0; 1095 } 1096 1097 static int ahci_dma_add_status(IDEDMA *dma, int status) 1098 { 1099 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1100 DPRINTF(ad->port_no, "set status: %x\n", status); 1101 1102 if (status & BM_STATUS_INT) { 1103 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS); 1104 } 1105 1106 return 0; 1107 } 1108 1109 static int ahci_dma_set_inactive(IDEDMA *dma) 1110 { 1111 return 0; 1112 } 1113 1114 static int ahci_async_cmd_done(IDEDMA *dma) 1115 { 1116 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1117 1118 DPRINTF(ad->port_no, "async cmd done\n"); 1119 1120 /* update d2h status */ 1121 ahci_write_fis_d2h(ad, NULL); 1122 1123 if (!ad->check_bh) { 1124 /* maybe we still have something to process, check later */ 1125 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad); 1126 qemu_bh_schedule(ad->check_bh); 1127 } 1128 1129 return 0; 1130 } 1131 1132 static void ahci_irq_set(void *opaque, int n, int level) 1133 { 1134 } 1135 1136 static void ahci_dma_restart_cb(void *opaque, int running, RunState state) 1137 { 1138 } 1139 1140 static int ahci_dma_reset(IDEDMA *dma) 1141 { 1142 return 0; 1143 } 1144 1145 static const IDEDMAOps ahci_dma_ops = { 1146 .start_dma = ahci_start_dma, 1147 .start_transfer = ahci_start_transfer, 1148 .prepare_buf = ahci_dma_prepare_buf, 1149 .rw_buf = ahci_dma_rw_buf, 1150 .set_unit = ahci_dma_set_unit, 1151 .add_status = ahci_dma_add_status, 1152 .set_inactive = ahci_dma_set_inactive, 1153 .async_cmd_done = ahci_async_cmd_done, 1154 .restart_cb = ahci_dma_restart_cb, 1155 .reset = ahci_dma_reset, 1156 }; 1157 1158 void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) 1159 { 1160 qemu_irq *irqs; 1161 int i; 1162 1163 s->as = as; 1164 s->ports = ports; 1165 s->dev = g_malloc0(sizeof(AHCIDevice) * ports); 1166 ahci_reg_init(s); 1167 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1168 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, 1169 "ahci", AHCI_MEM_BAR_SIZE); 1170 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, 1171 "ahci-idp", 32); 1172 1173 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1174 1175 for (i = 0; i < s->ports; i++) { 1176 AHCIDevice *ad = &s->dev[i]; 1177 1178 ide_bus_new(&ad->port, qdev, i, 1); 1179 ide_init2(&ad->port, irqs[i]); 1180 1181 ad->hba = s; 1182 ad->port_no = i; 1183 ad->port.dma = &ad->dma; 1184 ad->port.dma->ops = &ahci_dma_ops; 1185 } 1186 } 1187 1188 void ahci_uninit(AHCIState *s) 1189 { 1190 memory_region_destroy(&s->mem); 1191 memory_region_destroy(&s->idp); 1192 g_free(s->dev); 1193 } 1194 1195 void ahci_reset(AHCIState *s) 1196 { 1197 AHCIPortRegs *pr; 1198 int i; 1199 1200 s->control_regs.irqstatus = 0; 1201 s->control_regs.ghc = 0; 1202 1203 for (i = 0; i < s->ports; i++) { 1204 pr = &s->dev[i].port_regs; 1205 pr->irq_stat = 0; 1206 pr->irq_mask = 0; 1207 pr->scr_ctl = 0; 1208 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1209 ahci_reset_port(s, i); 1210 } 1211 } 1212 1213 static const VMStateDescription vmstate_ahci_device = { 1214 .name = "ahci port", 1215 .version_id = 1, 1216 .fields = (VMStateField []) { 1217 VMSTATE_IDE_BUS(port, AHCIDevice), 1218 VMSTATE_UINT32(port_state, AHCIDevice), 1219 VMSTATE_UINT32(finished, AHCIDevice), 1220 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), 1221 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), 1222 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), 1223 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), 1224 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), 1225 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), 1226 VMSTATE_UINT32(port_regs.cmd, AHCIDevice), 1227 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), 1228 VMSTATE_UINT32(port_regs.sig, AHCIDevice), 1229 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), 1230 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), 1231 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), 1232 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), 1233 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), 1234 VMSTATE_BOOL(done_atapi_packet, AHCIDevice), 1235 VMSTATE_INT32(busy_slot, AHCIDevice), 1236 VMSTATE_BOOL(init_d2h_sent, AHCIDevice), 1237 VMSTATE_END_OF_LIST() 1238 }, 1239 }; 1240 1241 static int ahci_state_post_load(void *opaque, int version_id) 1242 { 1243 int i; 1244 struct AHCIDevice *ad; 1245 AHCIState *s = opaque; 1246 1247 for (i = 0; i < s->ports; i++) { 1248 ad = &s->dev[i]; 1249 AHCIPortRegs *pr = &ad->port_regs; 1250 1251 map_page(&ad->lst, 1252 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 1253 map_page(&ad->res_fis, 1254 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 1255 /* 1256 * All pending i/o should be flushed out on a migrate. However, 1257 * we might not have cleared the busy_slot since this is done 1258 * in a bh. Also, issue i/o against any slots that are pending. 1259 */ 1260 if ((ad->busy_slot != -1) && 1261 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 1262 pr->cmd_issue &= ~(1 << ad->busy_slot); 1263 ad->busy_slot = -1; 1264 } 1265 check_cmd(s, i); 1266 } 1267 1268 return 0; 1269 } 1270 1271 const VMStateDescription vmstate_ahci = { 1272 .name = "ahci", 1273 .version_id = 1, 1274 .post_load = ahci_state_post_load, 1275 .fields = (VMStateField []) { 1276 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports, 1277 vmstate_ahci_device, AHCIDevice), 1278 VMSTATE_UINT32(control_regs.cap, AHCIState), 1279 VMSTATE_UINT32(control_regs.ghc, AHCIState), 1280 VMSTATE_UINT32(control_regs.irqstatus, AHCIState), 1281 VMSTATE_UINT32(control_regs.impl, AHCIState), 1282 VMSTATE_UINT32(control_regs.version, AHCIState), 1283 VMSTATE_UINT32(idp_index, AHCIState), 1284 VMSTATE_INT32(ports, AHCIState), 1285 VMSTATE_END_OF_LIST() 1286 }, 1287 }; 1288 1289 #define TYPE_SYSBUS_AHCI "sysbus-ahci" 1290 #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI) 1291 1292 typedef struct SysbusAHCIState { 1293 /*< private >*/ 1294 SysBusDevice parent_obj; 1295 /*< public >*/ 1296 1297 AHCIState ahci; 1298 uint32_t num_ports; 1299 } SysbusAHCIState; 1300 1301 static const VMStateDescription vmstate_sysbus_ahci = { 1302 .name = "sysbus-ahci", 1303 .unmigratable = 1, /* Still buggy under I/O load */ 1304 .fields = (VMStateField []) { 1305 VMSTATE_AHCI(ahci, AHCIPCIState), 1306 VMSTATE_END_OF_LIST() 1307 }, 1308 }; 1309 1310 static void sysbus_ahci_reset(DeviceState *dev) 1311 { 1312 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1313 1314 ahci_reset(&s->ahci); 1315 } 1316 1317 static void sysbus_ahci_realize(DeviceState *dev, Error **errp) 1318 { 1319 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1320 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1321 1322 ahci_init(&s->ahci, dev, NULL, s->num_ports); 1323 1324 sysbus_init_mmio(sbd, &s->ahci.mem); 1325 sysbus_init_irq(sbd, &s->ahci.irq); 1326 } 1327 1328 static Property sysbus_ahci_properties[] = { 1329 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1), 1330 DEFINE_PROP_END_OF_LIST(), 1331 }; 1332 1333 static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 1334 { 1335 DeviceClass *dc = DEVICE_CLASS(klass); 1336 1337 dc->realize = sysbus_ahci_realize; 1338 dc->vmsd = &vmstate_sysbus_ahci; 1339 dc->props = sysbus_ahci_properties; 1340 dc->reset = sysbus_ahci_reset; 1341 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1342 } 1343 1344 static const TypeInfo sysbus_ahci_info = { 1345 .name = TYPE_SYSBUS_AHCI, 1346 .parent = TYPE_SYS_BUS_DEVICE, 1347 .instance_size = sizeof(SysbusAHCIState), 1348 .class_init = sysbus_ahci_class_init, 1349 }; 1350 1351 static void sysbus_ahci_register_types(void) 1352 { 1353 type_register_static(&sysbus_ahci_info); 1354 } 1355 1356 type_init(sysbus_ahci_register_types) 1357