1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/pci.h" 27 #include "migration/vmstate.h" 28 29 #include "qemu/error-report.h" 30 #include "qemu/log.h" 31 #include "qemu/main-loop.h" 32 #include "qemu/module.h" 33 #include "sysemu/block-backend.h" 34 #include "sysemu/dma.h" 35 #include "hw/ide/internal.h" 36 #include "hw/ide/pci.h" 37 #include "ahci_internal.h" 38 39 #include "trace.h" 40 41 static void check_cmd(AHCIState *s, int port); 42 static int handle_cmd(AHCIState *s, int port, uint8_t slot); 43 static void ahci_reset_port(AHCIState *s, int port); 44 static bool ahci_write_fis_d2h(AHCIDevice *ad); 45 static void ahci_init_d2h(AHCIDevice *ad); 46 static int ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit); 47 static bool ahci_map_clb_address(AHCIDevice *ad); 48 static bool ahci_map_fis_address(AHCIDevice *ad); 49 static void ahci_unmap_clb_address(AHCIDevice *ad); 50 static void ahci_unmap_fis_address(AHCIDevice *ad); 51 52 static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = { 53 [AHCI_HOST_REG_CAP] = "CAP", 54 [AHCI_HOST_REG_CTL] = "GHC", 55 [AHCI_HOST_REG_IRQ_STAT] = "IS", 56 [AHCI_HOST_REG_PORTS_IMPL] = "PI", 57 [AHCI_HOST_REG_VERSION] = "VS", 58 [AHCI_HOST_REG_CCC_CTL] = "CCC_CTL", 59 [AHCI_HOST_REG_CCC_PORTS] = "CCC_PORTS", 60 [AHCI_HOST_REG_EM_LOC] = "EM_LOC", 61 [AHCI_HOST_REG_EM_CTL] = "EM_CTL", 62 [AHCI_HOST_REG_CAP2] = "CAP2", 63 [AHCI_HOST_REG_BOHC] = "BOHC", 64 }; 65 66 static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = { 67 [AHCI_PORT_REG_LST_ADDR] = "PxCLB", 68 [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU", 69 [AHCI_PORT_REG_FIS_ADDR] = "PxFB", 70 [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU", 71 [AHCI_PORT_REG_IRQ_STAT] = "PxIS", 72 [AHCI_PORT_REG_IRQ_MASK] = "PXIE", 73 [AHCI_PORT_REG_CMD] = "PxCMD", 74 [7] = "Reserved", 75 [AHCI_PORT_REG_TFDATA] = "PxTFD", 76 [AHCI_PORT_REG_SIG] = "PxSIG", 77 [AHCI_PORT_REG_SCR_STAT] = "PxSSTS", 78 [AHCI_PORT_REG_SCR_CTL] = "PxSCTL", 79 [AHCI_PORT_REG_SCR_ERR] = "PxSERR", 80 [AHCI_PORT_REG_SCR_ACT] = "PxSACT", 81 [AHCI_PORT_REG_CMD_ISSUE] = "PxCI", 82 [AHCI_PORT_REG_SCR_NOTIF] = "PxSNTF", 83 [AHCI_PORT_REG_FIS_CTL] = "PxFBS", 84 [AHCI_PORT_REG_DEV_SLEEP] = "PxDEVSLP", 85 [18 ... 27] = "Reserved", 86 [AHCI_PORT_REG_VENDOR_1 ... 87 AHCI_PORT_REG_VENDOR_4] = "PxVS", 88 }; 89 90 static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = { 91 [AHCI_PORT_IRQ_BIT_DHRS] = "DHRS", 92 [AHCI_PORT_IRQ_BIT_PSS] = "PSS", 93 [AHCI_PORT_IRQ_BIT_DSS] = "DSS", 94 [AHCI_PORT_IRQ_BIT_SDBS] = "SDBS", 95 [AHCI_PORT_IRQ_BIT_UFS] = "UFS", 96 [AHCI_PORT_IRQ_BIT_DPS] = "DPS", 97 [AHCI_PORT_IRQ_BIT_PCS] = "PCS", 98 [AHCI_PORT_IRQ_BIT_DMPS] = "DMPS", 99 [8 ... 21] = "RESERVED", 100 [AHCI_PORT_IRQ_BIT_PRCS] = "PRCS", 101 [AHCI_PORT_IRQ_BIT_IPMS] = "IPMS", 102 [AHCI_PORT_IRQ_BIT_OFS] = "OFS", 103 [25] = "RESERVED", 104 [AHCI_PORT_IRQ_BIT_INFS] = "INFS", 105 [AHCI_PORT_IRQ_BIT_IFS] = "IFS", 106 [AHCI_PORT_IRQ_BIT_HBDS] = "HBDS", 107 [AHCI_PORT_IRQ_BIT_HBFS] = "HBFS", 108 [AHCI_PORT_IRQ_BIT_TFES] = "TFES", 109 [AHCI_PORT_IRQ_BIT_CPDS] = "CPDS" 110 }; 111 112 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 113 { 114 uint32_t val; 115 AHCIPortRegs *pr = &s->dev[port].port_regs; 116 enum AHCIPortReg regnum = offset / sizeof(uint32_t); 117 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); 118 119 switch (regnum) { 120 case AHCI_PORT_REG_LST_ADDR: 121 val = pr->lst_addr; 122 break; 123 case AHCI_PORT_REG_LST_ADDR_HI: 124 val = pr->lst_addr_hi; 125 break; 126 case AHCI_PORT_REG_FIS_ADDR: 127 val = pr->fis_addr; 128 break; 129 case AHCI_PORT_REG_FIS_ADDR_HI: 130 val = pr->fis_addr_hi; 131 break; 132 case AHCI_PORT_REG_IRQ_STAT: 133 val = pr->irq_stat; 134 break; 135 case AHCI_PORT_REG_IRQ_MASK: 136 val = pr->irq_mask; 137 break; 138 case AHCI_PORT_REG_CMD: 139 val = pr->cmd; 140 break; 141 case AHCI_PORT_REG_TFDATA: 142 val = pr->tfdata; 143 break; 144 case AHCI_PORT_REG_SIG: 145 val = pr->sig; 146 break; 147 case AHCI_PORT_REG_SCR_STAT: 148 if (s->dev[port].port.ifs[0].blk) { 149 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 150 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 151 } else { 152 val = SATA_SCR_SSTATUS_DET_NODEV; 153 } 154 break; 155 case AHCI_PORT_REG_SCR_CTL: 156 val = pr->scr_ctl; 157 break; 158 case AHCI_PORT_REG_SCR_ERR: 159 val = pr->scr_err; 160 break; 161 case AHCI_PORT_REG_SCR_ACT: 162 val = pr->scr_act; 163 break; 164 case AHCI_PORT_REG_CMD_ISSUE: 165 val = pr->cmd_issue; 166 break; 167 default: 168 trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum], 169 offset); 170 val = 0; 171 } 172 173 trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val); 174 return val; 175 } 176 177 static void ahci_irq_raise(AHCIState *s) 178 { 179 DeviceState *dev_state = s->container; 180 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state), 181 TYPE_PCI_DEVICE); 182 183 trace_ahci_irq_raise(s); 184 185 if (pci_dev && msi_enabled(pci_dev)) { 186 msi_notify(pci_dev, 0); 187 } else { 188 qemu_irq_raise(s->irq); 189 } 190 } 191 192 static void ahci_irq_lower(AHCIState *s) 193 { 194 DeviceState *dev_state = s->container; 195 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state), 196 TYPE_PCI_DEVICE); 197 198 trace_ahci_irq_lower(s); 199 200 if (!pci_dev || !msi_enabled(pci_dev)) { 201 qemu_irq_lower(s->irq); 202 } 203 } 204 205 static void ahci_check_irq(AHCIState *s) 206 { 207 int i; 208 uint32_t old_irq = s->control_regs.irqstatus; 209 210 s->control_regs.irqstatus = 0; 211 for (i = 0; i < s->ports; i++) { 212 AHCIPortRegs *pr = &s->dev[i].port_regs; 213 if (pr->irq_stat & pr->irq_mask) { 214 s->control_regs.irqstatus |= (1 << i); 215 } 216 } 217 trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus); 218 if (s->control_regs.irqstatus && 219 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 220 ahci_irq_raise(s); 221 } else { 222 ahci_irq_lower(s); 223 } 224 } 225 226 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 227 enum AHCIPortIRQ irqbit) 228 { 229 g_assert((unsigned)irqbit < 32); 230 uint32_t irq = 1U << irqbit; 231 uint32_t irqstat = d->port_regs.irq_stat | irq; 232 233 trace_ahci_trigger_irq(s, d->port_no, 234 AHCIPortIRQ_lookup[irqbit], irq, 235 d->port_regs.irq_stat, irqstat, 236 irqstat & d->port_regs.irq_mask); 237 238 d->port_regs.irq_stat = irqstat; 239 ahci_check_irq(s); 240 } 241 242 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr, 243 uint32_t wanted) 244 { 245 hwaddr len = wanted; 246 247 if (*ptr) { 248 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 249 } 250 251 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE); 252 if (len < wanted) { 253 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 254 *ptr = NULL; 255 } 256 } 257 258 /** 259 * Check the cmd register to see if we should start or stop 260 * the DMA or FIS RX engines. 261 * 262 * @ad: Device to dis/engage. 263 * 264 * @return 0 on success, -1 on error. 265 */ 266 static int ahci_cond_start_engines(AHCIDevice *ad) 267 { 268 AHCIPortRegs *pr = &ad->port_regs; 269 bool cmd_start = pr->cmd & PORT_CMD_START; 270 bool cmd_on = pr->cmd & PORT_CMD_LIST_ON; 271 bool fis_start = pr->cmd & PORT_CMD_FIS_RX; 272 bool fis_on = pr->cmd & PORT_CMD_FIS_ON; 273 274 if (cmd_start && !cmd_on) { 275 if (!ahci_map_clb_address(ad)) { 276 pr->cmd &= ~PORT_CMD_START; 277 error_report("AHCI: Failed to start DMA engine: " 278 "bad command list buffer address"); 279 return -1; 280 } 281 } else if (!cmd_start && cmd_on) { 282 ahci_unmap_clb_address(ad); 283 } 284 285 if (fis_start && !fis_on) { 286 if (!ahci_map_fis_address(ad)) { 287 pr->cmd &= ~PORT_CMD_FIS_RX; 288 error_report("AHCI: Failed to start FIS receive engine: " 289 "bad FIS receive buffer address"); 290 return -1; 291 } 292 } else if (!fis_start && fis_on) { 293 ahci_unmap_fis_address(ad); 294 } 295 296 return 0; 297 } 298 299 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 300 { 301 AHCIPortRegs *pr = &s->dev[port].port_regs; 302 enum AHCIPortReg regnum = offset / sizeof(uint32_t); 303 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); 304 trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val); 305 306 switch (regnum) { 307 case AHCI_PORT_REG_LST_ADDR: 308 pr->lst_addr = val; 309 break; 310 case AHCI_PORT_REG_LST_ADDR_HI: 311 pr->lst_addr_hi = val; 312 break; 313 case AHCI_PORT_REG_FIS_ADDR: 314 pr->fis_addr = val; 315 break; 316 case AHCI_PORT_REG_FIS_ADDR_HI: 317 pr->fis_addr_hi = val; 318 break; 319 case AHCI_PORT_REG_IRQ_STAT: 320 pr->irq_stat &= ~val; 321 ahci_check_irq(s); 322 break; 323 case AHCI_PORT_REG_IRQ_MASK: 324 pr->irq_mask = val & 0xfdc000ff; 325 ahci_check_irq(s); 326 break; 327 case AHCI_PORT_REG_CMD: 328 /* Block any Read-only fields from being set; 329 * including LIST_ON and FIS_ON. 330 * The spec requires to set ICC bits to zero after the ICC change 331 * is done. We don't support ICC state changes, therefore always 332 * force the ICC bits to zero. 333 */ 334 pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | 335 (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK)); 336 337 /* Check FIS RX and CLB engines */ 338 ahci_cond_start_engines(&s->dev[port]); 339 340 /* XXX usually the FIS would be pending on the bus here and 341 issuing deferred until the OS enables FIS receival. 342 Instead, we only submit it once - which works in most 343 cases, but is a hack. */ 344 if ((pr->cmd & PORT_CMD_FIS_ON) && 345 !s->dev[port].init_d2h_sent) { 346 ahci_init_d2h(&s->dev[port]); 347 } 348 349 check_cmd(s, port); 350 break; 351 case AHCI_PORT_REG_TFDATA: 352 case AHCI_PORT_REG_SIG: 353 case AHCI_PORT_REG_SCR_STAT: 354 /* Read Only */ 355 break; 356 case AHCI_PORT_REG_SCR_CTL: 357 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 358 ((val & AHCI_SCR_SCTL_DET) == 0)) { 359 ahci_reset_port(s, port); 360 } 361 pr->scr_ctl = val; 362 break; 363 case AHCI_PORT_REG_SCR_ERR: 364 pr->scr_err &= ~val; 365 break; 366 case AHCI_PORT_REG_SCR_ACT: 367 /* RW1 */ 368 pr->scr_act |= val; 369 break; 370 case AHCI_PORT_REG_CMD_ISSUE: 371 pr->cmd_issue |= val; 372 check_cmd(s, port); 373 break; 374 default: 375 trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum], 376 offset, val); 377 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " 378 "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32, 379 port, AHCIPortReg_lookup[regnum], offset, val); 380 break; 381 } 382 } 383 384 static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr) 385 { 386 AHCIState *s = opaque; 387 uint32_t val = 0; 388 389 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 390 enum AHCIHostReg regnum = addr / 4; 391 assert(regnum < AHCI_HOST_REG__COUNT); 392 393 switch (regnum) { 394 case AHCI_HOST_REG_CAP: 395 val = s->control_regs.cap; 396 break; 397 case AHCI_HOST_REG_CTL: 398 val = s->control_regs.ghc; 399 break; 400 case AHCI_HOST_REG_IRQ_STAT: 401 val = s->control_regs.irqstatus; 402 break; 403 case AHCI_HOST_REG_PORTS_IMPL: 404 val = s->control_regs.impl; 405 break; 406 case AHCI_HOST_REG_VERSION: 407 val = s->control_regs.version; 408 break; 409 default: 410 trace_ahci_mem_read_32_host_default(s, AHCIHostReg_lookup[regnum], 411 addr); 412 } 413 trace_ahci_mem_read_32_host(s, AHCIHostReg_lookup[regnum], addr, val); 414 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 415 (addr < (AHCI_PORT_REGS_START_ADDR + 416 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 417 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 418 addr & AHCI_PORT_ADDR_OFFSET_MASK); 419 } else { 420 trace_ahci_mem_read_32_default(s, addr, val); 421 } 422 423 trace_ahci_mem_read_32(s, addr, val); 424 return val; 425 } 426 427 428 /** 429 * AHCI 1.3 section 3 ("HBA Memory Registers") 430 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads. 431 * Caller is responsible for masking unwanted higher order bytes. 432 */ 433 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size) 434 { 435 hwaddr aligned = addr & ~0x3; 436 int ofst = addr - aligned; 437 uint64_t lo = ahci_mem_read_32(opaque, aligned); 438 uint64_t hi; 439 uint64_t val; 440 441 /* if < 8 byte read does not cross 4 byte boundary */ 442 if (ofst + size <= 4) { 443 val = lo >> (ofst * 8); 444 } else { 445 g_assert(size > 1); 446 447 /* If the 64bit read is unaligned, we will produce undefined 448 * results. AHCI does not support unaligned 64bit reads. */ 449 hi = ahci_mem_read_32(opaque, aligned + 4); 450 val = (hi << 32 | lo) >> (ofst * 8); 451 } 452 453 trace_ahci_mem_read(opaque, size, addr, val); 454 return val; 455 } 456 457 458 static void ahci_mem_write(void *opaque, hwaddr addr, 459 uint64_t val, unsigned size) 460 { 461 AHCIState *s = opaque; 462 463 trace_ahci_mem_write(s, size, addr, val); 464 465 /* Only aligned reads are allowed on AHCI */ 466 if (addr & 3) { 467 fprintf(stderr, "ahci: Mis-aligned write to addr 0x" 468 TARGET_FMT_plx "\n", addr); 469 return; 470 } 471 472 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 473 enum AHCIHostReg regnum = addr / 4; 474 assert(regnum < AHCI_HOST_REG__COUNT); 475 476 switch (regnum) { 477 case AHCI_HOST_REG_CAP: /* R/WO, RO */ 478 /* FIXME handle R/WO */ 479 break; 480 case AHCI_HOST_REG_CTL: /* R/W */ 481 if (val & HOST_CTL_RESET) { 482 ahci_reset(s); 483 } else { 484 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 485 ahci_check_irq(s); 486 } 487 break; 488 case AHCI_HOST_REG_IRQ_STAT: /* R/WC, RO */ 489 s->control_regs.irqstatus &= ~val; 490 ahci_check_irq(s); 491 break; 492 case AHCI_HOST_REG_PORTS_IMPL: /* R/WO, RO */ 493 /* FIXME handle R/WO */ 494 break; 495 case AHCI_HOST_REG_VERSION: /* RO */ 496 /* FIXME report write? */ 497 break; 498 default: 499 qemu_log_mask(LOG_UNIMP, 500 "Attempted write to unimplemented register: " 501 "AHCI host register %s, " 502 "offset 0x%"PRIx64": 0x%"PRIx64, 503 AHCIHostReg_lookup[regnum], addr, val); 504 trace_ahci_mem_write_host_unimpl(s, size, 505 AHCIHostReg_lookup[regnum], addr); 506 } 507 trace_ahci_mem_write_host(s, size, AHCIHostReg_lookup[regnum], 508 addr, val); 509 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 510 (addr < (AHCI_PORT_REGS_START_ADDR + 511 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 512 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 513 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 514 } else { 515 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " 516 "AHCI global register at offset 0x%"PRIx64": 0x%"PRIx64, 517 addr, val); 518 trace_ahci_mem_write_unimpl(s, size, addr, val); 519 } 520 } 521 522 static const MemoryRegionOps ahci_mem_ops = { 523 .read = ahci_mem_read, 524 .write = ahci_mem_write, 525 .endianness = DEVICE_LITTLE_ENDIAN, 526 }; 527 528 static uint64_t ahci_idp_read(void *opaque, hwaddr addr, 529 unsigned size) 530 { 531 AHCIState *s = opaque; 532 533 if (addr == s->idp_offset) { 534 /* index register */ 535 return s->idp_index; 536 } else if (addr == s->idp_offset + 4) { 537 /* data register - do memory read at location selected by index */ 538 return ahci_mem_read(opaque, s->idp_index, size); 539 } else { 540 return 0; 541 } 542 } 543 544 static void ahci_idp_write(void *opaque, hwaddr addr, 545 uint64_t val, unsigned size) 546 { 547 AHCIState *s = opaque; 548 549 if (addr == s->idp_offset) { 550 /* index register - mask off reserved bits */ 551 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 552 } else if (addr == s->idp_offset + 4) { 553 /* data register - do memory write at location selected by index */ 554 ahci_mem_write(opaque, s->idp_index, val, size); 555 } 556 } 557 558 static const MemoryRegionOps ahci_idp_ops = { 559 .read = ahci_idp_read, 560 .write = ahci_idp_write, 561 .endianness = DEVICE_LITTLE_ENDIAN, 562 }; 563 564 565 static void ahci_reg_init(AHCIState *s) 566 { 567 int i; 568 569 s->control_regs.cap = (s->ports - 1) | 570 (AHCI_NUM_COMMAND_SLOTS << 8) | 571 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 572 HOST_CAP_NCQ | HOST_CAP_AHCI | HOST_CAP_64; 573 574 s->control_regs.impl = (1 << s->ports) - 1; 575 576 s->control_regs.version = AHCI_VERSION_1_0; 577 578 for (i = 0; i < s->ports; i++) { 579 s->dev[i].port_state = STATE_RUN; 580 } 581 } 582 583 static void check_cmd(AHCIState *s, int port) 584 { 585 AHCIPortRegs *pr = &s->dev[port].port_regs; 586 uint8_t slot; 587 588 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 589 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 590 if ((pr->cmd_issue & (1U << slot)) && 591 !handle_cmd(s, port, slot)) { 592 pr->cmd_issue &= ~(1U << slot); 593 } 594 } 595 } 596 } 597 598 static void ahci_check_cmd_bh(void *opaque) 599 { 600 AHCIDevice *ad = opaque; 601 602 qemu_bh_delete(ad->check_bh); 603 ad->check_bh = NULL; 604 605 check_cmd(ad->hba, ad->port_no); 606 } 607 608 static void ahci_init_d2h(AHCIDevice *ad) 609 { 610 IDEState *ide_state = &ad->port.ifs[0]; 611 AHCIPortRegs *pr = &ad->port_regs; 612 613 if (ad->init_d2h_sent) { 614 return; 615 } 616 617 if (ahci_write_fis_d2h(ad)) { 618 ad->init_d2h_sent = true; 619 /* We're emulating receiving the first Reg H2D Fis from the device; 620 * Update the SIG register, but otherwise proceed as normal. */ 621 pr->sig = ((uint32_t)ide_state->hcyl << 24) | 622 (ide_state->lcyl << 16) | 623 (ide_state->sector << 8) | 624 (ide_state->nsector & 0xFF); 625 } 626 } 627 628 static void ahci_set_signature(AHCIDevice *ad, uint32_t sig) 629 { 630 IDEState *s = &ad->port.ifs[0]; 631 s->hcyl = sig >> 24 & 0xFF; 632 s->lcyl = sig >> 16 & 0xFF; 633 s->sector = sig >> 8 & 0xFF; 634 s->nsector = sig & 0xFF; 635 636 trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector, 637 s->lcyl, s->hcyl, sig); 638 } 639 640 static void ahci_reset_port(AHCIState *s, int port) 641 { 642 AHCIDevice *d = &s->dev[port]; 643 AHCIPortRegs *pr = &d->port_regs; 644 IDEState *ide_state = &d->port.ifs[0]; 645 int i; 646 647 trace_ahci_reset_port(s, port); 648 649 ide_bus_reset(&d->port); 650 ide_state->ncq_queues = AHCI_MAX_CMDS; 651 652 pr->scr_stat = 0; 653 pr->scr_err = 0; 654 pr->scr_act = 0; 655 pr->tfdata = 0x7F; 656 pr->sig = 0xFFFFFFFF; 657 d->busy_slot = -1; 658 d->init_d2h_sent = false; 659 660 ide_state = &s->dev[port].port.ifs[0]; 661 if (!ide_state->blk) { 662 return; 663 } 664 665 /* reset ncq queue */ 666 for (i = 0; i < AHCI_MAX_CMDS; i++) { 667 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 668 ncq_tfs->halt = false; 669 if (!ncq_tfs->used) { 670 continue; 671 } 672 673 if (ncq_tfs->aiocb) { 674 blk_aio_cancel(ncq_tfs->aiocb); 675 ncq_tfs->aiocb = NULL; 676 } 677 678 /* Maybe we just finished the request thanks to blk_aio_cancel() */ 679 if (!ncq_tfs->used) { 680 continue; 681 } 682 683 qemu_sglist_destroy(&ncq_tfs->sglist); 684 ncq_tfs->used = 0; 685 } 686 687 s->dev[port].port_state = STATE_RUN; 688 if (ide_state->drive_kind == IDE_CD) { 689 ahci_set_signature(d, SATA_SIGNATURE_CDROM);\ 690 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 691 } else { 692 ahci_set_signature(d, SATA_SIGNATURE_DISK); 693 ide_state->status = SEEK_STAT | WRERR_STAT; 694 } 695 696 ide_state->error = 1; 697 ahci_init_d2h(d); 698 } 699 700 /* Buffer pretty output based on a raw FIS structure. */ 701 static char *ahci_pretty_buffer_fis(uint8_t *fis, int cmd_len) 702 { 703 int i; 704 GString *s = g_string_new("FIS:"); 705 706 for (i = 0; i < cmd_len; i++) { 707 if ((i & 0xf) == 0) { 708 g_string_append_printf(s, "\n0x%02x: ", i); 709 } 710 g_string_append_printf(s, "%02x ", fis[i]); 711 } 712 g_string_append_c(s, '\n'); 713 714 return g_string_free(s, FALSE); 715 } 716 717 static bool ahci_map_fis_address(AHCIDevice *ad) 718 { 719 AHCIPortRegs *pr = &ad->port_regs; 720 map_page(ad->hba->as, &ad->res_fis, 721 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 722 if (ad->res_fis != NULL) { 723 pr->cmd |= PORT_CMD_FIS_ON; 724 return true; 725 } 726 727 pr->cmd &= ~PORT_CMD_FIS_ON; 728 return false; 729 } 730 731 static void ahci_unmap_fis_address(AHCIDevice *ad) 732 { 733 if (ad->res_fis == NULL) { 734 trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no); 735 return; 736 } 737 ad->port_regs.cmd &= ~PORT_CMD_FIS_ON; 738 dma_memory_unmap(ad->hba->as, ad->res_fis, 256, 739 DMA_DIRECTION_FROM_DEVICE, 256); 740 ad->res_fis = NULL; 741 } 742 743 static bool ahci_map_clb_address(AHCIDevice *ad) 744 { 745 AHCIPortRegs *pr = &ad->port_regs; 746 ad->cur_cmd = NULL; 747 map_page(ad->hba->as, &ad->lst, 748 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 749 if (ad->lst != NULL) { 750 pr->cmd |= PORT_CMD_LIST_ON; 751 return true; 752 } 753 754 pr->cmd &= ~PORT_CMD_LIST_ON; 755 return false; 756 } 757 758 static void ahci_unmap_clb_address(AHCIDevice *ad) 759 { 760 if (ad->lst == NULL) { 761 trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no); 762 return; 763 } 764 ad->port_regs.cmd &= ~PORT_CMD_LIST_ON; 765 dma_memory_unmap(ad->hba->as, ad->lst, 1024, 766 DMA_DIRECTION_FROM_DEVICE, 1024); 767 ad->lst = NULL; 768 } 769 770 static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs) 771 { 772 AHCIDevice *ad = ncq_tfs->drive; 773 AHCIPortRegs *pr = &ad->port_regs; 774 IDEState *ide_state; 775 SDBFIS *sdb_fis; 776 777 if (!ad->res_fis || 778 !(pr->cmd & PORT_CMD_FIS_RX)) { 779 return; 780 } 781 782 sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS]; 783 ide_state = &ad->port.ifs[0]; 784 785 sdb_fis->type = SATA_FIS_TYPE_SDB; 786 /* Interrupt pending & Notification bit */ 787 sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */ 788 sdb_fis->status = ide_state->status & 0x77; 789 sdb_fis->error = ide_state->error; 790 /* update SAct field in SDB_FIS */ 791 sdb_fis->payload = cpu_to_le32(ad->finished); 792 793 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */ 794 pr->tfdata = (ad->port.ifs[0].error << 8) | 795 (ad->port.ifs[0].status & 0x77) | 796 (pr->tfdata & 0x88); 797 pr->scr_act &= ~ad->finished; 798 ad->finished = 0; 799 800 /* Trigger IRQ if interrupt bit is set (which currently, it always is) */ 801 if (sdb_fis->flags & 0x40) { 802 ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS); 803 } 804 } 805 806 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i) 807 { 808 AHCIPortRegs *pr = &ad->port_regs; 809 uint8_t *pio_fis; 810 IDEState *s = &ad->port.ifs[0]; 811 812 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 813 return; 814 } 815 816 pio_fis = &ad->res_fis[RES_FIS_PSFIS]; 817 818 pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP; 819 pio_fis[1] = (pio_fis_i ? (1 << 6) : 0); 820 pio_fis[2] = s->status; 821 pio_fis[3] = s->error; 822 823 pio_fis[4] = s->sector; 824 pio_fis[5] = s->lcyl; 825 pio_fis[6] = s->hcyl; 826 pio_fis[7] = s->select; 827 pio_fis[8] = s->hob_sector; 828 pio_fis[9] = s->hob_lcyl; 829 pio_fis[10] = s->hob_hcyl; 830 pio_fis[11] = 0; 831 pio_fis[12] = s->nsector & 0xFF; 832 pio_fis[13] = (s->nsector >> 8) & 0xFF; 833 pio_fis[14] = 0; 834 pio_fis[15] = s->status; 835 pio_fis[16] = len & 255; 836 pio_fis[17] = len >> 8; 837 pio_fis[18] = 0; 838 pio_fis[19] = 0; 839 840 /* Update shadow registers: */ 841 pr->tfdata = (ad->port.ifs[0].error << 8) | 842 ad->port.ifs[0].status; 843 844 if (pio_fis[2] & ERR_STAT) { 845 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); 846 } 847 } 848 849 static bool ahci_write_fis_d2h(AHCIDevice *ad) 850 { 851 AHCIPortRegs *pr = &ad->port_regs; 852 uint8_t *d2h_fis; 853 int i; 854 IDEState *s = &ad->port.ifs[0]; 855 856 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 857 return false; 858 } 859 860 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 861 862 d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H; 863 d2h_fis[1] = (1 << 6); /* interrupt bit */ 864 d2h_fis[2] = s->status; 865 d2h_fis[3] = s->error; 866 867 d2h_fis[4] = s->sector; 868 d2h_fis[5] = s->lcyl; 869 d2h_fis[6] = s->hcyl; 870 d2h_fis[7] = s->select; 871 d2h_fis[8] = s->hob_sector; 872 d2h_fis[9] = s->hob_lcyl; 873 d2h_fis[10] = s->hob_hcyl; 874 d2h_fis[11] = 0; 875 d2h_fis[12] = s->nsector & 0xFF; 876 d2h_fis[13] = (s->nsector >> 8) & 0xFF; 877 for (i = 14; i < 20; i++) { 878 d2h_fis[i] = 0; 879 } 880 881 /* Update shadow registers: */ 882 pr->tfdata = (ad->port.ifs[0].error << 8) | 883 ad->port.ifs[0].status; 884 885 if (d2h_fis[2] & ERR_STAT) { 886 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); 887 } 888 889 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); 890 return true; 891 } 892 893 static int prdt_tbl_entry_size(const AHCI_SG *tbl) 894 { 895 /* flags_size is zero-based */ 896 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1; 897 } 898 899 /** 900 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist. 901 * @ad: The AHCIDevice for whom we are building the SGList. 902 * @sglist: The SGList target to add PRD entries to. 903 * @cmd: The AHCI Command Header that describes where the PRDT is. 904 * @limit: The remaining size of the S/ATA transaction, in bytes. 905 * @offset: The number of bytes already transferred, in bytes. 906 * 907 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of 908 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop 909 * building the sglist from the PRDT as soon as we hit @limit bytes, 910 * which is <= INT32_MAX/2GiB. 911 */ 912 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, 913 AHCICmdHdr *cmd, int64_t limit, uint64_t offset) 914 { 915 uint16_t opts = le16_to_cpu(cmd->opts); 916 uint16_t prdtl = le16_to_cpu(cmd->prdtl); 917 uint64_t cfis_addr = le64_to_cpu(cmd->tbl_addr); 918 uint64_t prdt_addr = cfis_addr + 0x80; 919 dma_addr_t prdt_len = (prdtl * sizeof(AHCI_SG)); 920 dma_addr_t real_prdt_len = prdt_len; 921 uint8_t *prdt; 922 int i; 923 int r = 0; 924 uint64_t sum = 0; 925 int off_idx = -1; 926 int64_t off_pos = -1; 927 int tbl_entry_size; 928 IDEBus *bus = &ad->port; 929 BusState *qbus = BUS(bus); 930 931 trace_ahci_populate_sglist(ad->hba, ad->port_no); 932 933 if (!prdtl) { 934 trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts); 935 return -1; 936 } 937 938 /* map PRDT */ 939 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, 940 DMA_DIRECTION_TO_DEVICE))){ 941 trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no); 942 return -1; 943 } 944 945 if (prdt_len < real_prdt_len) { 946 trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no); 947 r = -1; 948 goto out; 949 } 950 951 /* Get entries in the PRDT, init a qemu sglist accordingly */ 952 if (prdtl > 0) { 953 AHCI_SG *tbl = (AHCI_SG *)prdt; 954 sum = 0; 955 for (i = 0; i < prdtl; i++) { 956 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]); 957 if (offset < (sum + tbl_entry_size)) { 958 off_idx = i; 959 off_pos = offset - sum; 960 break; 961 } 962 sum += tbl_entry_size; 963 } 964 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { 965 trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no, 966 off_idx, off_pos); 967 r = -1; 968 goto out; 969 } 970 971 qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx), 972 ad->hba->as); 973 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos, 974 MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos, 975 limit)); 976 977 for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) { 978 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 979 MIN(prdt_tbl_entry_size(&tbl[i]), 980 limit - sglist->size)); 981 } 982 } 983 984 out: 985 dma_memory_unmap(ad->hba->as, prdt, prdt_len, 986 DMA_DIRECTION_TO_DEVICE, prdt_len); 987 return r; 988 } 989 990 static void ncq_err(NCQTransferState *ncq_tfs) 991 { 992 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 993 994 ide_state->error = ABRT_ERR; 995 ide_state->status = READY_STAT | ERR_STAT; 996 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); 997 qemu_sglist_destroy(&ncq_tfs->sglist); 998 ncq_tfs->used = 0; 999 } 1000 1001 static void ncq_finish(NCQTransferState *ncq_tfs) 1002 { 1003 /* If we didn't error out, set our finished bit. Errored commands 1004 * do not get a bit set for the SDB FIS ACT register, nor do they 1005 * clear the outstanding bit in scr_act (PxSACT). */ 1006 if (!(ncq_tfs->drive->port_regs.scr_err & (1 << ncq_tfs->tag))) { 1007 ncq_tfs->drive->finished |= (1 << ncq_tfs->tag); 1008 } 1009 1010 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs); 1011 1012 trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, 1013 ncq_tfs->tag); 1014 1015 block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk), 1016 &ncq_tfs->acct); 1017 qemu_sglist_destroy(&ncq_tfs->sglist); 1018 ncq_tfs->used = 0; 1019 } 1020 1021 static void ncq_cb(void *opaque, int ret) 1022 { 1023 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 1024 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 1025 1026 ncq_tfs->aiocb = NULL; 1027 if (ret == -ECANCELED) { 1028 return; 1029 } 1030 1031 if (ret < 0) { 1032 bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED; 1033 BlockErrorAction action = blk_get_error_action(ide_state->blk, 1034 is_read, -ret); 1035 if (action == BLOCK_ERROR_ACTION_STOP) { 1036 ncq_tfs->halt = true; 1037 ide_state->bus->error_status = IDE_RETRY_HBA; 1038 } else if (action == BLOCK_ERROR_ACTION_REPORT) { 1039 ncq_err(ncq_tfs); 1040 } 1041 blk_error_action(ide_state->blk, action, is_read, -ret); 1042 } else { 1043 ide_state->status = READY_STAT | SEEK_STAT; 1044 } 1045 1046 if (!ncq_tfs->halt) { 1047 ncq_finish(ncq_tfs); 1048 } 1049 } 1050 1051 static int is_ncq(uint8_t ata_cmd) 1052 { 1053 /* Based on SATA 3.2 section 13.6.3.2 */ 1054 switch (ata_cmd) { 1055 case READ_FPDMA_QUEUED: 1056 case WRITE_FPDMA_QUEUED: 1057 case NCQ_NON_DATA: 1058 case RECEIVE_FPDMA_QUEUED: 1059 case SEND_FPDMA_QUEUED: 1060 return 1; 1061 default: 1062 return 0; 1063 } 1064 } 1065 1066 static void execute_ncq_command(NCQTransferState *ncq_tfs) 1067 { 1068 AHCIDevice *ad = ncq_tfs->drive; 1069 IDEState *ide_state = &ad->port.ifs[0]; 1070 int port = ad->port_no; 1071 1072 g_assert(is_ncq(ncq_tfs->cmd)); 1073 ncq_tfs->halt = false; 1074 1075 switch (ncq_tfs->cmd) { 1076 case READ_FPDMA_QUEUED: 1077 trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag, 1078 ncq_tfs->sector_count, ncq_tfs->lba); 1079 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 1080 &ncq_tfs->sglist, BLOCK_ACCT_READ); 1081 ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist, 1082 ncq_tfs->lba << BDRV_SECTOR_BITS, 1083 BDRV_SECTOR_SIZE, 1084 ncq_cb, ncq_tfs); 1085 break; 1086 case WRITE_FPDMA_QUEUED: 1087 trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag, 1088 ncq_tfs->sector_count, ncq_tfs->lba); 1089 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 1090 &ncq_tfs->sglist, BLOCK_ACCT_WRITE); 1091 ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist, 1092 ncq_tfs->lba << BDRV_SECTOR_BITS, 1093 BDRV_SECTOR_SIZE, 1094 ncq_cb, ncq_tfs); 1095 break; 1096 default: 1097 trace_execute_ncq_command_unsup(ad->hba, port, 1098 ncq_tfs->tag, ncq_tfs->cmd); 1099 ncq_err(ncq_tfs); 1100 } 1101 } 1102 1103 1104 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis, 1105 uint8_t slot) 1106 { 1107 AHCIDevice *ad = &s->dev[port]; 1108 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis; 1109 uint8_t tag = ncq_fis->tag >> 3; 1110 NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag]; 1111 size_t size; 1112 1113 g_assert(is_ncq(ncq_fis->command)); 1114 if (ncq_tfs->used) { 1115 /* error - already in use */ 1116 fprintf(stderr, "%s: tag %d already used\n", __func__, tag); 1117 return; 1118 } 1119 1120 ncq_tfs->used = 1; 1121 ncq_tfs->drive = ad; 1122 ncq_tfs->slot = slot; 1123 ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot]; 1124 ncq_tfs->cmd = ncq_fis->command; 1125 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 1126 ((uint64_t)ncq_fis->lba4 << 32) | 1127 ((uint64_t)ncq_fis->lba3 << 24) | 1128 ((uint64_t)ncq_fis->lba2 << 16) | 1129 ((uint64_t)ncq_fis->lba1 << 8) | 1130 (uint64_t)ncq_fis->lba0; 1131 ncq_tfs->tag = tag; 1132 1133 /* Sanity-check the NCQ packet */ 1134 if (tag != slot) { 1135 trace_process_ncq_command_mismatch(s, port, tag, slot); 1136 } 1137 1138 if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) { 1139 trace_process_ncq_command_aux(s, port, tag); 1140 } 1141 if (ncq_fis->prio || ncq_fis->icc) { 1142 trace_process_ncq_command_prioicc(s, port, tag); 1143 } 1144 if (ncq_fis->fua & NCQ_FIS_FUA_MASK) { 1145 trace_process_ncq_command_fua(s, port, tag); 1146 } 1147 if (ncq_fis->tag & NCQ_FIS_RARC_MASK) { 1148 trace_process_ncq_command_rarc(s, port, tag); 1149 } 1150 1151 ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) | 1152 ncq_fis->sector_count_low); 1153 if (!ncq_tfs->sector_count) { 1154 ncq_tfs->sector_count = 0x10000; 1155 } 1156 size = ncq_tfs->sector_count * 512; 1157 ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0); 1158 1159 if (ncq_tfs->sglist.size < size) { 1160 error_report("ahci: PRDT length for NCQ command (0x%zx) " 1161 "is smaller than the requested size (0x%zx)", 1162 ncq_tfs->sglist.size, size); 1163 ncq_err(ncq_tfs); 1164 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS); 1165 return; 1166 } else if (ncq_tfs->sglist.size != size) { 1167 trace_process_ncq_command_large(s, port, tag, 1168 ncq_tfs->sglist.size, size); 1169 } 1170 1171 trace_process_ncq_command(s, port, tag, 1172 ncq_fis->command, 1173 ncq_tfs->lba, 1174 ncq_tfs->lba + ncq_tfs->sector_count - 1); 1175 execute_ncq_command(ncq_tfs); 1176 } 1177 1178 static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot) 1179 { 1180 if (port >= s->ports || slot >= AHCI_MAX_CMDS) { 1181 return NULL; 1182 } 1183 1184 return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL; 1185 } 1186 1187 static void handle_reg_h2d_fis(AHCIState *s, int port, 1188 uint8_t slot, uint8_t *cmd_fis) 1189 { 1190 IDEState *ide_state = &s->dev[port].port.ifs[0]; 1191 AHCICmdHdr *cmd = get_cmd_header(s, port, slot); 1192 uint16_t opts = le16_to_cpu(cmd->opts); 1193 1194 if (cmd_fis[1] & 0x0F) { 1195 trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1], 1196 cmd_fis[2], cmd_fis[3]); 1197 return; 1198 } 1199 1200 if (cmd_fis[1] & 0x70) { 1201 trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1], 1202 cmd_fis[2], cmd_fis[3]); 1203 return; 1204 } 1205 1206 if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) { 1207 switch (s->dev[port].port_state) { 1208 case STATE_RUN: 1209 if (cmd_fis[15] & ATA_SRST) { 1210 s->dev[port].port_state = STATE_RESET; 1211 } 1212 break; 1213 case STATE_RESET: 1214 if (!(cmd_fis[15] & ATA_SRST)) { 1215 ahci_reset_port(s, port); 1216 } 1217 break; 1218 } 1219 return; 1220 } 1221 1222 /* Check for NCQ command */ 1223 if (is_ncq(cmd_fis[2])) { 1224 process_ncq_command(s, port, cmd_fis, slot); 1225 return; 1226 } 1227 1228 /* Decompose the FIS: 1229 * AHCI does not interpret FIS packets, it only forwards them. 1230 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets. 1231 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets. 1232 * 1233 * ATA4 describes sector number for LBA28/CHS commands. 1234 * ATA6 describes sector number for LBA48 commands. 1235 * ATA8 deprecates CHS fully, describing only LBA28/48. 1236 * 1237 * We dutifully convert the FIS into IDE registers, and allow the 1238 * core layer to interpret them as needed. */ 1239 ide_state->feature = cmd_fis[3]; 1240 ide_state->sector = cmd_fis[4]; /* LBA 7:0 */ 1241 ide_state->lcyl = cmd_fis[5]; /* LBA 15:8 */ 1242 ide_state->hcyl = cmd_fis[6]; /* LBA 23:16 */ 1243 ide_state->select = cmd_fis[7]; /* LBA 27:24 (LBA28) */ 1244 ide_state->hob_sector = cmd_fis[8]; /* LBA 31:24 */ 1245 ide_state->hob_lcyl = cmd_fis[9]; /* LBA 39:32 */ 1246 ide_state->hob_hcyl = cmd_fis[10]; /* LBA 47:40 */ 1247 ide_state->hob_feature = cmd_fis[11]; 1248 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 1249 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */ 1250 /* 15: Only valid when UPDATE_COMMAND not set. */ 1251 1252 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 1253 * table to ide_state->io_buffer */ 1254 if (opts & AHCI_CMD_ATAPI) { 1255 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 1256 if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP)) { 1257 char *pretty_fis = ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10); 1258 trace_handle_reg_h2d_fis_dump(s, port, pretty_fis); 1259 g_free(pretty_fis); 1260 } 1261 } 1262 1263 ide_state->error = 0; 1264 s->dev[port].done_first_drq = false; 1265 /* Reset transferred byte counter */ 1266 cmd->status = 0; 1267 1268 /* We're ready to process the command in FIS byte 2. */ 1269 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]); 1270 } 1271 1272 static int handle_cmd(AHCIState *s, int port, uint8_t slot) 1273 { 1274 IDEState *ide_state; 1275 uint64_t tbl_addr; 1276 AHCICmdHdr *cmd; 1277 uint8_t *cmd_fis; 1278 dma_addr_t cmd_len; 1279 1280 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 1281 /* Engine currently busy, try again later */ 1282 trace_handle_cmd_busy(s, port); 1283 return -1; 1284 } 1285 1286 if (!s->dev[port].lst) { 1287 trace_handle_cmd_nolist(s, port); 1288 return -1; 1289 } 1290 cmd = get_cmd_header(s, port, slot); 1291 /* remember current slot handle for later */ 1292 s->dev[port].cur_cmd = cmd; 1293 1294 /* The device we are working for */ 1295 ide_state = &s->dev[port].port.ifs[0]; 1296 if (!ide_state->blk) { 1297 trace_handle_cmd_badport(s, port); 1298 return -1; 1299 } 1300 1301 tbl_addr = le64_to_cpu(cmd->tbl_addr); 1302 cmd_len = 0x80; 1303 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, 1304 DMA_DIRECTION_FROM_DEVICE); 1305 if (!cmd_fis) { 1306 trace_handle_cmd_badfis(s, port); 1307 return -1; 1308 } else if (cmd_len != 0x80) { 1309 ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS); 1310 trace_handle_cmd_badmap(s, port, cmd_len); 1311 goto out; 1312 } 1313 if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP)) { 1314 char *pretty_fis = ahci_pretty_buffer_fis(cmd_fis, 0x80); 1315 trace_handle_cmd_fis_dump(s, port, pretty_fis); 1316 g_free(pretty_fis); 1317 } 1318 switch (cmd_fis[0]) { 1319 case SATA_FIS_TYPE_REGISTER_H2D: 1320 handle_reg_h2d_fis(s, port, slot, cmd_fis); 1321 break; 1322 default: 1323 trace_handle_cmd_unhandled_fis(s, port, 1324 cmd_fis[0], cmd_fis[1], cmd_fis[2]); 1325 break; 1326 } 1327 1328 out: 1329 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE, 1330 cmd_len); 1331 1332 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 1333 /* async command, complete later */ 1334 s->dev[port].busy_slot = slot; 1335 return -1; 1336 } 1337 1338 /* done handling the command */ 1339 return 0; 1340 } 1341 1342 /* Transfer PIO data between RAM and device */ 1343 static void ahci_pio_transfer(IDEDMA *dma) 1344 { 1345 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1346 IDEState *s = &ad->port.ifs[0]; 1347 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 1348 /* write == ram -> device */ 1349 uint16_t opts = le16_to_cpu(ad->cur_cmd->opts); 1350 int is_write = opts & AHCI_CMD_WRITE; 1351 int is_atapi = opts & AHCI_CMD_ATAPI; 1352 int has_sglist = 0; 1353 bool pio_fis_i; 1354 1355 /* The PIO Setup FIS is received prior to transfer, but the interrupt 1356 * is only triggered after data is received. 1357 * 1358 * The device only sets the 'I' bit in the PIO Setup FIS for device->host 1359 * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after 1360 * the first (see "DPIOO1"). The latter is consistent with the spec's 1361 * description of the PACKET protocol, where the command part of ATAPI requests 1362 * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests 1363 * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs. 1364 */ 1365 pio_fis_i = ad->done_first_drq || (!is_atapi && !is_write); 1366 ahci_write_fis_pio(ad, size, pio_fis_i); 1367 1368 if (is_atapi && !ad->done_first_drq) { 1369 /* already prepopulated iobuffer */ 1370 goto out; 1371 } 1372 1373 if (ahci_dma_prepare_buf(dma, size)) { 1374 has_sglist = 1; 1375 } 1376 1377 trace_ahci_pio_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read", 1378 size, is_atapi ? "atapi" : "ata", 1379 has_sglist ? "" : "o"); 1380 1381 if (has_sglist && size) { 1382 if (is_write) { 1383 dma_buf_write(s->data_ptr, size, &s->sg); 1384 } else { 1385 dma_buf_read(s->data_ptr, size, &s->sg); 1386 } 1387 } 1388 1389 /* Update number of transferred bytes, destroy sglist */ 1390 dma_buf_commit(s, size); 1391 1392 out: 1393 /* declare that we processed everything */ 1394 s->data_ptr = s->data_end; 1395 1396 ad->done_first_drq = true; 1397 if (pio_fis_i) { 1398 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS); 1399 } 1400 } 1401 1402 static void ahci_start_dma(IDEDMA *dma, IDEState *s, 1403 BlockCompletionFunc *dma_cb) 1404 { 1405 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1406 trace_ahci_start_dma(ad->hba, ad->port_no); 1407 s->io_buffer_offset = 0; 1408 dma_cb(s, 0); 1409 } 1410 1411 static void ahci_restart_dma(IDEDMA *dma) 1412 { 1413 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */ 1414 } 1415 1416 /** 1417 * IDE/PIO restarts are handled by the core layer, but NCQ commands 1418 * need an extra kick from the AHCI HBA. 1419 */ 1420 static void ahci_restart(IDEDMA *dma) 1421 { 1422 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1423 int i; 1424 1425 for (i = 0; i < AHCI_MAX_CMDS; i++) { 1426 NCQTransferState *ncq_tfs = &ad->ncq_tfs[i]; 1427 if (ncq_tfs->halt) { 1428 execute_ncq_command(ncq_tfs); 1429 } 1430 } 1431 } 1432 1433 /** 1434 * Called in DMA and PIO R/W chains to read the PRDT. 1435 * Not shared with NCQ pathways. 1436 */ 1437 static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit) 1438 { 1439 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1440 IDEState *s = &ad->port.ifs[0]; 1441 1442 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, 1443 limit, s->io_buffer_offset) == -1) { 1444 trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no); 1445 return -1; 1446 } 1447 s->io_buffer_size = s->sg.size; 1448 1449 trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size); 1450 return s->io_buffer_size; 1451 } 1452 1453 /** 1454 * Updates the command header with a bytes-read value. 1455 * Called via dma_buf_commit, for both DMA and PIO paths. 1456 * sglist destruction is handled within dma_buf_commit. 1457 */ 1458 static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes) 1459 { 1460 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1461 1462 tx_bytes += le32_to_cpu(ad->cur_cmd->status); 1463 ad->cur_cmd->status = cpu_to_le32(tx_bytes); 1464 } 1465 1466 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) 1467 { 1468 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1469 IDEState *s = &ad->port.ifs[0]; 1470 uint8_t *p = s->io_buffer + s->io_buffer_index; 1471 int l = s->io_buffer_size - s->io_buffer_index; 1472 1473 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) { 1474 return 0; 1475 } 1476 1477 if (is_write) { 1478 dma_buf_read(p, l, &s->sg); 1479 } else { 1480 dma_buf_write(p, l, &s->sg); 1481 } 1482 1483 /* free sglist, update byte count */ 1484 dma_buf_commit(s, l); 1485 s->io_buffer_index += l; 1486 1487 trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l); 1488 return 1; 1489 } 1490 1491 static void ahci_cmd_done(IDEDMA *dma) 1492 { 1493 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1494 1495 trace_ahci_cmd_done(ad->hba, ad->port_no); 1496 1497 /* no longer busy */ 1498 if (ad->busy_slot != -1) { 1499 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot); 1500 ad->busy_slot = -1; 1501 } 1502 1503 /* update d2h status */ 1504 ahci_write_fis_d2h(ad); 1505 1506 if (ad->port_regs.cmd_issue && !ad->check_bh) { 1507 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad); 1508 qemu_bh_schedule(ad->check_bh); 1509 } 1510 } 1511 1512 static void ahci_irq_set(void *opaque, int n, int level) 1513 { 1514 } 1515 1516 static const IDEDMAOps ahci_dma_ops = { 1517 .start_dma = ahci_start_dma, 1518 .restart = ahci_restart, 1519 .restart_dma = ahci_restart_dma, 1520 .pio_transfer = ahci_pio_transfer, 1521 .prepare_buf = ahci_dma_prepare_buf, 1522 .commit_buf = ahci_commit_buf, 1523 .rw_buf = ahci_dma_rw_buf, 1524 .cmd_done = ahci_cmd_done, 1525 }; 1526 1527 void ahci_init(AHCIState *s, DeviceState *qdev) 1528 { 1529 s->container = qdev; 1530 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1531 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, 1532 "ahci", AHCI_MEM_BAR_SIZE); 1533 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, 1534 "ahci-idp", 32); 1535 } 1536 1537 void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) 1538 { 1539 qemu_irq *irqs; 1540 int i; 1541 1542 s->as = as; 1543 s->ports = ports; 1544 s->dev = g_new0(AHCIDevice, ports); 1545 ahci_reg_init(s); 1546 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1547 for (i = 0; i < s->ports; i++) { 1548 AHCIDevice *ad = &s->dev[i]; 1549 1550 ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1); 1551 ide_init2(&ad->port, irqs[i]); 1552 1553 ad->hba = s; 1554 ad->port_no = i; 1555 ad->port.dma = &ad->dma; 1556 ad->port.dma->ops = &ahci_dma_ops; 1557 ide_register_restart_cb(&ad->port); 1558 } 1559 g_free(irqs); 1560 } 1561 1562 void ahci_uninit(AHCIState *s) 1563 { 1564 int i, j; 1565 1566 for (i = 0; i < s->ports; i++) { 1567 AHCIDevice *ad = &s->dev[i]; 1568 1569 for (j = 0; j < 2; j++) { 1570 IDEState *s = &ad->port.ifs[j]; 1571 1572 ide_exit(s); 1573 } 1574 object_unparent(OBJECT(&ad->port)); 1575 } 1576 1577 g_free(s->dev); 1578 } 1579 1580 void ahci_reset(AHCIState *s) 1581 { 1582 AHCIPortRegs *pr; 1583 int i; 1584 1585 trace_ahci_reset(s); 1586 1587 s->control_regs.irqstatus = 0; 1588 /* AHCI Enable (AE) 1589 * The implementation of this bit is dependent upon the value of the 1590 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and 1591 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be 1592 * read-only and shall have a reset value of '1'. 1593 * 1594 * We set HOST_CAP_AHCI so we must enable AHCI at reset. 1595 */ 1596 s->control_regs.ghc = HOST_CTL_AHCI_EN; 1597 1598 for (i = 0; i < s->ports; i++) { 1599 pr = &s->dev[i].port_regs; 1600 pr->irq_stat = 0; 1601 pr->irq_mask = 0; 1602 pr->scr_ctl = 0; 1603 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1604 ahci_reset_port(s, i); 1605 } 1606 } 1607 1608 static const VMStateDescription vmstate_ncq_tfs = { 1609 .name = "ncq state", 1610 .version_id = 1, 1611 .fields = (VMStateField[]) { 1612 VMSTATE_UINT32(sector_count, NCQTransferState), 1613 VMSTATE_UINT64(lba, NCQTransferState), 1614 VMSTATE_UINT8(tag, NCQTransferState), 1615 VMSTATE_UINT8(cmd, NCQTransferState), 1616 VMSTATE_UINT8(slot, NCQTransferState), 1617 VMSTATE_BOOL(used, NCQTransferState), 1618 VMSTATE_BOOL(halt, NCQTransferState), 1619 VMSTATE_END_OF_LIST() 1620 }, 1621 }; 1622 1623 static const VMStateDescription vmstate_ahci_device = { 1624 .name = "ahci port", 1625 .version_id = 1, 1626 .fields = (VMStateField[]) { 1627 VMSTATE_IDE_BUS(port, AHCIDevice), 1628 VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice), 1629 VMSTATE_UINT32(port_state, AHCIDevice), 1630 VMSTATE_UINT32(finished, AHCIDevice), 1631 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), 1632 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), 1633 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), 1634 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), 1635 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), 1636 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), 1637 VMSTATE_UINT32(port_regs.cmd, AHCIDevice), 1638 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), 1639 VMSTATE_UINT32(port_regs.sig, AHCIDevice), 1640 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), 1641 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), 1642 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), 1643 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), 1644 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), 1645 VMSTATE_BOOL(done_first_drq, AHCIDevice), 1646 VMSTATE_INT32(busy_slot, AHCIDevice), 1647 VMSTATE_BOOL(init_d2h_sent, AHCIDevice), 1648 VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS, 1649 1, vmstate_ncq_tfs, NCQTransferState), 1650 VMSTATE_END_OF_LIST() 1651 }, 1652 }; 1653 1654 static int ahci_state_post_load(void *opaque, int version_id) 1655 { 1656 int i, j; 1657 struct AHCIDevice *ad; 1658 NCQTransferState *ncq_tfs; 1659 AHCIPortRegs *pr; 1660 AHCIState *s = opaque; 1661 1662 for (i = 0; i < s->ports; i++) { 1663 ad = &s->dev[i]; 1664 pr = &ad->port_regs; 1665 1666 if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) { 1667 error_report("AHCI: DMA engine should be off, but status bit " 1668 "indicates it is still running."); 1669 return -1; 1670 } 1671 if (!(pr->cmd & PORT_CMD_FIS_RX) && (pr->cmd & PORT_CMD_FIS_ON)) { 1672 error_report("AHCI: FIS RX engine should be off, but status bit " 1673 "indicates it is still running."); 1674 return -1; 1675 } 1676 1677 /* After a migrate, the DMA/FIS engines are "off" and 1678 * need to be conditionally restarted */ 1679 pr->cmd &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); 1680 if (ahci_cond_start_engines(ad) != 0) { 1681 return -1; 1682 } 1683 1684 for (j = 0; j < AHCI_MAX_CMDS; j++) { 1685 ncq_tfs = &ad->ncq_tfs[j]; 1686 ncq_tfs->drive = ad; 1687 1688 if (ncq_tfs->used != ncq_tfs->halt) { 1689 return -1; 1690 } 1691 if (!ncq_tfs->halt) { 1692 continue; 1693 } 1694 if (!is_ncq(ncq_tfs->cmd)) { 1695 return -1; 1696 } 1697 if (ncq_tfs->slot != ncq_tfs->tag) { 1698 return -1; 1699 } 1700 /* If ncq_tfs->halt is justly set, the engine should be engaged, 1701 * and the command list buffer should be mapped. */ 1702 ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot); 1703 if (!ncq_tfs->cmdh) { 1704 return -1; 1705 } 1706 ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist, 1707 ncq_tfs->cmdh, ncq_tfs->sector_count * 512, 1708 0); 1709 if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) { 1710 return -1; 1711 } 1712 } 1713 1714 1715 /* 1716 * If an error is present, ad->busy_slot will be valid and not -1. 1717 * In this case, an operation is waiting to resume and will re-check 1718 * for additional AHCI commands to execute upon completion. 1719 * 1720 * In the case where no error was present, busy_slot will be -1, 1721 * and we should check to see if there are additional commands waiting. 1722 */ 1723 if (ad->busy_slot == -1) { 1724 check_cmd(s, i); 1725 } else { 1726 /* We are in the middle of a command, and may need to access 1727 * the command header in guest memory again. */ 1728 if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) { 1729 return -1; 1730 } 1731 ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot); 1732 } 1733 } 1734 1735 return 0; 1736 } 1737 1738 const VMStateDescription vmstate_ahci = { 1739 .name = "ahci", 1740 .version_id = 1, 1741 .post_load = ahci_state_post_load, 1742 .fields = (VMStateField[]) { 1743 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports, 1744 vmstate_ahci_device, AHCIDevice), 1745 VMSTATE_UINT32(control_regs.cap, AHCIState), 1746 VMSTATE_UINT32(control_regs.ghc, AHCIState), 1747 VMSTATE_UINT32(control_regs.irqstatus, AHCIState), 1748 VMSTATE_UINT32(control_regs.impl, AHCIState), 1749 VMSTATE_UINT32(control_regs.version, AHCIState), 1750 VMSTATE_UINT32(idp_index, AHCIState), 1751 VMSTATE_INT32_EQUAL(ports, AHCIState, NULL), 1752 VMSTATE_END_OF_LIST() 1753 }, 1754 }; 1755 1756 static const VMStateDescription vmstate_sysbus_ahci = { 1757 .name = "sysbus-ahci", 1758 .fields = (VMStateField[]) { 1759 VMSTATE_AHCI(ahci, SysbusAHCIState), 1760 VMSTATE_END_OF_LIST() 1761 }, 1762 }; 1763 1764 static void sysbus_ahci_reset(DeviceState *dev) 1765 { 1766 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1767 1768 ahci_reset(&s->ahci); 1769 } 1770 1771 static void sysbus_ahci_init(Object *obj) 1772 { 1773 SysbusAHCIState *s = SYSBUS_AHCI(obj); 1774 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1775 1776 ahci_init(&s->ahci, DEVICE(obj)); 1777 1778 sysbus_init_mmio(sbd, &s->ahci.mem); 1779 sysbus_init_irq(sbd, &s->ahci.irq); 1780 } 1781 1782 static void sysbus_ahci_realize(DeviceState *dev, Error **errp) 1783 { 1784 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1785 1786 ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports); 1787 } 1788 1789 static Property sysbus_ahci_properties[] = { 1790 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1), 1791 DEFINE_PROP_END_OF_LIST(), 1792 }; 1793 1794 static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 1795 { 1796 DeviceClass *dc = DEVICE_CLASS(klass); 1797 1798 dc->realize = sysbus_ahci_realize; 1799 dc->vmsd = &vmstate_sysbus_ahci; 1800 dc->props = sysbus_ahci_properties; 1801 dc->reset = sysbus_ahci_reset; 1802 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1803 } 1804 1805 static const TypeInfo sysbus_ahci_info = { 1806 .name = TYPE_SYSBUS_AHCI, 1807 .parent = TYPE_SYS_BUS_DEVICE, 1808 .instance_size = sizeof(SysbusAHCIState), 1809 .instance_init = sysbus_ahci_init, 1810 .class_init = sysbus_ahci_class_init, 1811 }; 1812 1813 static void sysbus_ahci_register_types(void) 1814 { 1815 type_register_static(&sysbus_ahci_info); 1816 } 1817 1818 type_init(sysbus_ahci_register_types) 1819 1820 int32_t ahci_get_num_ports(PCIDevice *dev) 1821 { 1822 AHCIPCIState *d = ICH_AHCI(dev); 1823 AHCIState *ahci = &d->ahci; 1824 1825 return ahci->ports; 1826 } 1827 1828 void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd) 1829 { 1830 AHCIPCIState *d = ICH_AHCI(dev); 1831 AHCIState *ahci = &d->ahci; 1832 int i; 1833 1834 for (i = 0; i < ahci->ports; i++) { 1835 if (hd[i] == NULL) { 1836 continue; 1837 } 1838 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 1839 } 1840 1841 } 1842