1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/irq.h" 26 #include "hw/pci/msi.h" 27 #include "hw/pci/pci.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 31 #include "qemu/error-report.h" 32 #include "qemu/log.h" 33 #include "qemu/main-loop.h" 34 #include "qemu/module.h" 35 #include "sysemu/block-backend.h" 36 #include "sysemu/dma.h" 37 #include "hw/ide/internal.h" 38 #include "hw/ide/pci.h" 39 #include "hw/ide/ahci-pci.h" 40 #include "ahci_internal.h" 41 42 #include "trace.h" 43 44 static void check_cmd(AHCIState *s, int port); 45 static void handle_cmd(AHCIState *s, int port, uint8_t slot); 46 static void ahci_reset_port(AHCIState *s, int port); 47 static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i); 48 static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot); 49 static void ahci_init_d2h(AHCIDevice *ad); 50 static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit); 51 static bool ahci_map_clb_address(AHCIDevice *ad); 52 static bool ahci_map_fis_address(AHCIDevice *ad); 53 static void ahci_unmap_clb_address(AHCIDevice *ad); 54 static void ahci_unmap_fis_address(AHCIDevice *ad); 55 56 static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = { 57 [AHCI_HOST_REG_CAP] = "CAP", 58 [AHCI_HOST_REG_CTL] = "GHC", 59 [AHCI_HOST_REG_IRQ_STAT] = "IS", 60 [AHCI_HOST_REG_PORTS_IMPL] = "PI", 61 [AHCI_HOST_REG_VERSION] = "VS", 62 [AHCI_HOST_REG_CCC_CTL] = "CCC_CTL", 63 [AHCI_HOST_REG_CCC_PORTS] = "CCC_PORTS", 64 [AHCI_HOST_REG_EM_LOC] = "EM_LOC", 65 [AHCI_HOST_REG_EM_CTL] = "EM_CTL", 66 [AHCI_HOST_REG_CAP2] = "CAP2", 67 [AHCI_HOST_REG_BOHC] = "BOHC", 68 }; 69 70 static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = { 71 [AHCI_PORT_REG_LST_ADDR] = "PxCLB", 72 [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU", 73 [AHCI_PORT_REG_FIS_ADDR] = "PxFB", 74 [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU", 75 [AHCI_PORT_REG_IRQ_STAT] = "PxIS", 76 [AHCI_PORT_REG_IRQ_MASK] = "PXIE", 77 [AHCI_PORT_REG_CMD] = "PxCMD", 78 [7] = "Reserved", 79 [AHCI_PORT_REG_TFDATA] = "PxTFD", 80 [AHCI_PORT_REG_SIG] = "PxSIG", 81 [AHCI_PORT_REG_SCR_STAT] = "PxSSTS", 82 [AHCI_PORT_REG_SCR_CTL] = "PxSCTL", 83 [AHCI_PORT_REG_SCR_ERR] = "PxSERR", 84 [AHCI_PORT_REG_SCR_ACT] = "PxSACT", 85 [AHCI_PORT_REG_CMD_ISSUE] = "PxCI", 86 [AHCI_PORT_REG_SCR_NOTIF] = "PxSNTF", 87 [AHCI_PORT_REG_FIS_CTL] = "PxFBS", 88 [AHCI_PORT_REG_DEV_SLEEP] = "PxDEVSLP", 89 [18 ... 27] = "Reserved", 90 [AHCI_PORT_REG_VENDOR_1 ... 91 AHCI_PORT_REG_VENDOR_4] = "PxVS", 92 }; 93 94 static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = { 95 [AHCI_PORT_IRQ_BIT_DHRS] = "DHRS", 96 [AHCI_PORT_IRQ_BIT_PSS] = "PSS", 97 [AHCI_PORT_IRQ_BIT_DSS] = "DSS", 98 [AHCI_PORT_IRQ_BIT_SDBS] = "SDBS", 99 [AHCI_PORT_IRQ_BIT_UFS] = "UFS", 100 [AHCI_PORT_IRQ_BIT_DPS] = "DPS", 101 [AHCI_PORT_IRQ_BIT_PCS] = "PCS", 102 [AHCI_PORT_IRQ_BIT_DMPS] = "DMPS", 103 [8 ... 21] = "RESERVED", 104 [AHCI_PORT_IRQ_BIT_PRCS] = "PRCS", 105 [AHCI_PORT_IRQ_BIT_IPMS] = "IPMS", 106 [AHCI_PORT_IRQ_BIT_OFS] = "OFS", 107 [25] = "RESERVED", 108 [AHCI_PORT_IRQ_BIT_INFS] = "INFS", 109 [AHCI_PORT_IRQ_BIT_IFS] = "IFS", 110 [AHCI_PORT_IRQ_BIT_HBDS] = "HBDS", 111 [AHCI_PORT_IRQ_BIT_HBFS] = "HBFS", 112 [AHCI_PORT_IRQ_BIT_TFES] = "TFES", 113 [AHCI_PORT_IRQ_BIT_CPDS] = "CPDS" 114 }; 115 116 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 117 { 118 uint32_t val; 119 AHCIPortRegs *pr = &s->dev[port].port_regs; 120 enum AHCIPortReg regnum = offset / sizeof(uint32_t); 121 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); 122 123 switch (regnum) { 124 case AHCI_PORT_REG_LST_ADDR: 125 val = pr->lst_addr; 126 break; 127 case AHCI_PORT_REG_LST_ADDR_HI: 128 val = pr->lst_addr_hi; 129 break; 130 case AHCI_PORT_REG_FIS_ADDR: 131 val = pr->fis_addr; 132 break; 133 case AHCI_PORT_REG_FIS_ADDR_HI: 134 val = pr->fis_addr_hi; 135 break; 136 case AHCI_PORT_REG_IRQ_STAT: 137 val = pr->irq_stat; 138 break; 139 case AHCI_PORT_REG_IRQ_MASK: 140 val = pr->irq_mask; 141 break; 142 case AHCI_PORT_REG_CMD: 143 val = pr->cmd; 144 break; 145 case AHCI_PORT_REG_TFDATA: 146 val = pr->tfdata; 147 break; 148 case AHCI_PORT_REG_SIG: 149 val = pr->sig; 150 break; 151 case AHCI_PORT_REG_SCR_STAT: 152 if (s->dev[port].port.ifs[0].blk) { 153 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 154 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 155 } else { 156 val = SATA_SCR_SSTATUS_DET_NODEV; 157 } 158 break; 159 case AHCI_PORT_REG_SCR_CTL: 160 val = pr->scr_ctl; 161 break; 162 case AHCI_PORT_REG_SCR_ERR: 163 val = pr->scr_err; 164 break; 165 case AHCI_PORT_REG_SCR_ACT: 166 val = pr->scr_act; 167 break; 168 case AHCI_PORT_REG_CMD_ISSUE: 169 val = pr->cmd_issue; 170 break; 171 default: 172 trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum], 173 offset); 174 val = 0; 175 } 176 177 trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val); 178 return val; 179 } 180 181 static void ahci_irq_raise(AHCIState *s) 182 { 183 DeviceState *dev_state = s->container; 184 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state), 185 TYPE_PCI_DEVICE); 186 187 trace_ahci_irq_raise(s); 188 189 if (pci_dev && msi_enabled(pci_dev)) { 190 msi_notify(pci_dev, 0); 191 } else { 192 qemu_irq_raise(s->irq); 193 } 194 } 195 196 static void ahci_irq_lower(AHCIState *s) 197 { 198 DeviceState *dev_state = s->container; 199 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state), 200 TYPE_PCI_DEVICE); 201 202 trace_ahci_irq_lower(s); 203 204 if (!pci_dev || !msi_enabled(pci_dev)) { 205 qemu_irq_lower(s->irq); 206 } 207 } 208 209 static void ahci_check_irq(AHCIState *s) 210 { 211 int i; 212 uint32_t old_irq = s->control_regs.irqstatus; 213 214 s->control_regs.irqstatus = 0; 215 for (i = 0; i < s->ports; i++) { 216 AHCIPortRegs *pr = &s->dev[i].port_regs; 217 if (pr->irq_stat & pr->irq_mask) { 218 s->control_regs.irqstatus |= (1 << i); 219 } 220 } 221 trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus); 222 if (s->control_regs.irqstatus && 223 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 224 ahci_irq_raise(s); 225 } else { 226 ahci_irq_lower(s); 227 } 228 } 229 230 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 231 enum AHCIPortIRQ irqbit) 232 { 233 g_assert((unsigned)irqbit < 32); 234 uint32_t irq = 1U << irqbit; 235 uint32_t irqstat = d->port_regs.irq_stat | irq; 236 237 trace_ahci_trigger_irq(s, d->port_no, 238 AHCIPortIRQ_lookup[irqbit], irq, 239 d->port_regs.irq_stat, irqstat, 240 irqstat & d->port_regs.irq_mask); 241 242 d->port_regs.irq_stat = irqstat; 243 ahci_check_irq(s); 244 } 245 246 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr, 247 uint32_t wanted) 248 { 249 hwaddr len = wanted; 250 251 if (*ptr) { 252 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 253 } 254 255 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE, 256 MEMTXATTRS_UNSPECIFIED); 257 if (len < wanted && *ptr) { 258 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 259 *ptr = NULL; 260 } 261 } 262 263 /** 264 * Check the cmd register to see if we should start or stop 265 * the DMA or FIS RX engines. 266 * 267 * @ad: Device to dis/engage. 268 * 269 * @return 0 on success, -1 on error. 270 */ 271 static int ahci_cond_start_engines(AHCIDevice *ad) 272 { 273 AHCIPortRegs *pr = &ad->port_regs; 274 bool cmd_start = pr->cmd & PORT_CMD_START; 275 bool cmd_on = pr->cmd & PORT_CMD_LIST_ON; 276 bool fis_start = pr->cmd & PORT_CMD_FIS_RX; 277 bool fis_on = pr->cmd & PORT_CMD_FIS_ON; 278 279 if (cmd_start && !cmd_on) { 280 if (!ahci_map_clb_address(ad)) { 281 pr->cmd &= ~PORT_CMD_START; 282 error_report("AHCI: Failed to start DMA engine: " 283 "bad command list buffer address"); 284 return -1; 285 } 286 } else if (!cmd_start && cmd_on) { 287 ahci_unmap_clb_address(ad); 288 } 289 290 if (fis_start && !fis_on) { 291 if (!ahci_map_fis_address(ad)) { 292 pr->cmd &= ~PORT_CMD_FIS_RX; 293 error_report("AHCI: Failed to start FIS receive engine: " 294 "bad FIS receive buffer address"); 295 return -1; 296 } 297 } else if (!fis_start && fis_on) { 298 ahci_unmap_fis_address(ad); 299 } 300 301 return 0; 302 } 303 304 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 305 { 306 AHCIPortRegs *pr = &s->dev[port].port_regs; 307 enum AHCIPortReg regnum = offset / sizeof(uint32_t); 308 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); 309 trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val); 310 311 switch (regnum) { 312 case AHCI_PORT_REG_LST_ADDR: 313 pr->lst_addr = val; 314 break; 315 case AHCI_PORT_REG_LST_ADDR_HI: 316 pr->lst_addr_hi = val; 317 break; 318 case AHCI_PORT_REG_FIS_ADDR: 319 pr->fis_addr = val; 320 break; 321 case AHCI_PORT_REG_FIS_ADDR_HI: 322 pr->fis_addr_hi = val; 323 break; 324 case AHCI_PORT_REG_IRQ_STAT: 325 pr->irq_stat &= ~val; 326 ahci_check_irq(s); 327 break; 328 case AHCI_PORT_REG_IRQ_MASK: 329 pr->irq_mask = val & 0xfdc000ff; 330 ahci_check_irq(s); 331 break; 332 case AHCI_PORT_REG_CMD: 333 if ((pr->cmd & PORT_CMD_START) && !(val & PORT_CMD_START)) { 334 pr->scr_act = 0; 335 pr->cmd_issue = 0; 336 } 337 338 /* Block any Read-only fields from being set; 339 * including LIST_ON and FIS_ON. 340 * The spec requires to set ICC bits to zero after the ICC change 341 * is done. We don't support ICC state changes, therefore always 342 * force the ICC bits to zero. 343 */ 344 pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | 345 (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK)); 346 347 /* Check FIS RX and CLB engines */ 348 ahci_cond_start_engines(&s->dev[port]); 349 350 /* XXX usually the FIS would be pending on the bus here and 351 issuing deferred until the OS enables FIS receival. 352 Instead, we only submit it once - which works in most 353 cases, but is a hack. */ 354 if ((pr->cmd & PORT_CMD_FIS_ON) && 355 !s->dev[port].init_d2h_sent) { 356 ahci_init_d2h(&s->dev[port]); 357 } 358 359 check_cmd(s, port); 360 break; 361 case AHCI_PORT_REG_TFDATA: 362 case AHCI_PORT_REG_SIG: 363 case AHCI_PORT_REG_SCR_STAT: 364 /* Read Only */ 365 break; 366 case AHCI_PORT_REG_SCR_CTL: 367 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 368 ((val & AHCI_SCR_SCTL_DET) == 0)) { 369 ahci_reset_port(s, port); 370 } 371 pr->scr_ctl = val; 372 break; 373 case AHCI_PORT_REG_SCR_ERR: 374 pr->scr_err &= ~val; 375 break; 376 case AHCI_PORT_REG_SCR_ACT: 377 /* RW1 */ 378 pr->scr_act |= val; 379 break; 380 case AHCI_PORT_REG_CMD_ISSUE: 381 pr->cmd_issue |= val; 382 check_cmd(s, port); 383 break; 384 default: 385 trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum], 386 offset, val); 387 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " 388 "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32, 389 port, AHCIPortReg_lookup[regnum], offset, val); 390 break; 391 } 392 } 393 394 static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr) 395 { 396 AHCIState *s = opaque; 397 uint32_t val = 0; 398 399 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 400 enum AHCIHostReg regnum = addr / 4; 401 assert(regnum < AHCI_HOST_REG__COUNT); 402 403 switch (regnum) { 404 case AHCI_HOST_REG_CAP: 405 val = s->control_regs.cap; 406 break; 407 case AHCI_HOST_REG_CTL: 408 val = s->control_regs.ghc; 409 break; 410 case AHCI_HOST_REG_IRQ_STAT: 411 val = s->control_regs.irqstatus; 412 break; 413 case AHCI_HOST_REG_PORTS_IMPL: 414 val = s->control_regs.impl; 415 break; 416 case AHCI_HOST_REG_VERSION: 417 val = s->control_regs.version; 418 break; 419 default: 420 trace_ahci_mem_read_32_host_default(s, AHCIHostReg_lookup[regnum], 421 addr); 422 } 423 trace_ahci_mem_read_32_host(s, AHCIHostReg_lookup[regnum], addr, val); 424 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 425 (addr < (AHCI_PORT_REGS_START_ADDR + 426 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 427 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 428 addr & AHCI_PORT_ADDR_OFFSET_MASK); 429 } else { 430 trace_ahci_mem_read_32_default(s, addr, val); 431 } 432 433 trace_ahci_mem_read_32(s, addr, val); 434 return val; 435 } 436 437 438 /** 439 * AHCI 1.3 section 3 ("HBA Memory Registers") 440 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads. 441 * Caller is responsible for masking unwanted higher order bytes. 442 */ 443 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size) 444 { 445 hwaddr aligned = addr & ~0x3; 446 int ofst = addr - aligned; 447 uint64_t lo = ahci_mem_read_32(opaque, aligned); 448 uint64_t hi; 449 uint64_t val; 450 451 /* if < 8 byte read does not cross 4 byte boundary */ 452 if (ofst + size <= 4) { 453 val = lo >> (ofst * 8); 454 } else { 455 g_assert(size > 1); 456 457 /* If the 64bit read is unaligned, we will produce undefined 458 * results. AHCI does not support unaligned 64bit reads. */ 459 hi = ahci_mem_read_32(opaque, aligned + 4); 460 val = (hi << 32 | lo) >> (ofst * 8); 461 } 462 463 trace_ahci_mem_read(opaque, size, addr, val); 464 return val; 465 } 466 467 468 static void ahci_mem_write(void *opaque, hwaddr addr, 469 uint64_t val, unsigned size) 470 { 471 AHCIState *s = opaque; 472 473 trace_ahci_mem_write(s, size, addr, val); 474 475 /* Only aligned reads are allowed on AHCI */ 476 if (addr & 3) { 477 qemu_log_mask(LOG_GUEST_ERROR, 478 "ahci: Mis-aligned write to addr 0x%03" HWADDR_PRIX "\n", 479 addr); 480 return; 481 } 482 483 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 484 enum AHCIHostReg regnum = addr / 4; 485 assert(regnum < AHCI_HOST_REG__COUNT); 486 487 switch (regnum) { 488 case AHCI_HOST_REG_CAP: /* R/WO, RO */ 489 /* FIXME handle R/WO */ 490 break; 491 case AHCI_HOST_REG_CTL: /* R/W */ 492 if (val & HOST_CTL_RESET) { 493 ahci_reset(s); 494 } else { 495 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 496 ahci_check_irq(s); 497 } 498 break; 499 case AHCI_HOST_REG_IRQ_STAT: /* R/WC, RO */ 500 s->control_regs.irqstatus &= ~val; 501 ahci_check_irq(s); 502 break; 503 case AHCI_HOST_REG_PORTS_IMPL: /* R/WO, RO */ 504 /* FIXME handle R/WO */ 505 break; 506 case AHCI_HOST_REG_VERSION: /* RO */ 507 /* FIXME report write? */ 508 break; 509 default: 510 qemu_log_mask(LOG_UNIMP, 511 "Attempted write to unimplemented register: " 512 "AHCI host register %s, " 513 "offset 0x%"PRIx64": 0x%"PRIx64, 514 AHCIHostReg_lookup[regnum], addr, val); 515 trace_ahci_mem_write_host_unimpl(s, size, 516 AHCIHostReg_lookup[regnum], addr); 517 } 518 trace_ahci_mem_write_host(s, size, AHCIHostReg_lookup[regnum], 519 addr, val); 520 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 521 (addr < (AHCI_PORT_REGS_START_ADDR + 522 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 523 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 524 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 525 } else { 526 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " 527 "AHCI global register at offset 0x%"PRIx64": 0x%"PRIx64, 528 addr, val); 529 trace_ahci_mem_write_unimpl(s, size, addr, val); 530 } 531 } 532 533 static const MemoryRegionOps ahci_mem_ops = { 534 .read = ahci_mem_read, 535 .write = ahci_mem_write, 536 .endianness = DEVICE_LITTLE_ENDIAN, 537 }; 538 539 static uint64_t ahci_idp_read(void *opaque, hwaddr addr, 540 unsigned size) 541 { 542 AHCIState *s = opaque; 543 544 if (addr == s->idp_offset) { 545 /* index register */ 546 return s->idp_index; 547 } else if (addr == s->idp_offset + 4) { 548 /* data register - do memory read at location selected by index */ 549 return ahci_mem_read(opaque, s->idp_index, size); 550 } else { 551 return 0; 552 } 553 } 554 555 static void ahci_idp_write(void *opaque, hwaddr addr, 556 uint64_t val, unsigned size) 557 { 558 AHCIState *s = opaque; 559 560 if (addr == s->idp_offset) { 561 /* index register - mask off reserved bits */ 562 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 563 } else if (addr == s->idp_offset + 4) { 564 /* data register - do memory write at location selected by index */ 565 ahci_mem_write(opaque, s->idp_index, val, size); 566 } 567 } 568 569 static const MemoryRegionOps ahci_idp_ops = { 570 .read = ahci_idp_read, 571 .write = ahci_idp_write, 572 .endianness = DEVICE_LITTLE_ENDIAN, 573 }; 574 575 576 static void ahci_reg_init(AHCIState *s) 577 { 578 int i; 579 580 s->control_regs.cap = (s->ports - 1) | 581 (AHCI_NUM_COMMAND_SLOTS << 8) | 582 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 583 HOST_CAP_NCQ | HOST_CAP_AHCI | HOST_CAP_64; 584 585 s->control_regs.impl = (1 << s->ports) - 1; 586 587 s->control_regs.version = AHCI_VERSION_1_0; 588 589 for (i = 0; i < s->ports; i++) { 590 s->dev[i].port_state = STATE_RUN; 591 } 592 } 593 594 static void check_cmd(AHCIState *s, int port) 595 { 596 AHCIPortRegs *pr = &s->dev[port].port_regs; 597 uint8_t slot; 598 599 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 600 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 601 if (pr->cmd_issue & (1U << slot)) { 602 handle_cmd(s, port, slot); 603 } 604 } 605 } 606 } 607 608 static void ahci_check_cmd_bh(void *opaque) 609 { 610 AHCIDevice *ad = opaque; 611 612 qemu_bh_delete(ad->check_bh); 613 ad->check_bh = NULL; 614 615 check_cmd(ad->hba, ad->port_no); 616 } 617 618 static void ahci_init_d2h(AHCIDevice *ad) 619 { 620 IDEState *ide_state = &ad->port.ifs[0]; 621 AHCIPortRegs *pr = &ad->port_regs; 622 623 if (ad->init_d2h_sent) { 624 return; 625 } 626 627 /* 628 * For simplicity, do not call ahci_clear_cmd_issue() for this 629 * ahci_write_fis_d2h(). (The reset value for PxCI is 0.) 630 */ 631 if (ahci_write_fis_d2h(ad, true)) { 632 ad->init_d2h_sent = true; 633 /* We're emulating receiving the first Reg D2H FIS from the device; 634 * Update the SIG register, but otherwise proceed as normal. */ 635 pr->sig = ((uint32_t)ide_state->hcyl << 24) | 636 (ide_state->lcyl << 16) | 637 (ide_state->sector << 8) | 638 (ide_state->nsector & 0xFF); 639 } 640 } 641 642 static void ahci_set_signature(AHCIDevice *ad, uint32_t sig) 643 { 644 IDEState *s = &ad->port.ifs[0]; 645 s->hcyl = sig >> 24 & 0xFF; 646 s->lcyl = sig >> 16 & 0xFF; 647 s->sector = sig >> 8 & 0xFF; 648 s->nsector = sig & 0xFF; 649 650 trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector, 651 s->lcyl, s->hcyl, sig); 652 } 653 654 static void ahci_reset_port(AHCIState *s, int port) 655 { 656 AHCIDevice *d = &s->dev[port]; 657 AHCIPortRegs *pr = &d->port_regs; 658 IDEState *ide_state = &d->port.ifs[0]; 659 int i; 660 661 trace_ahci_reset_port(s, port); 662 663 ide_bus_reset(&d->port); 664 ide_state->ncq_queues = AHCI_MAX_CMDS; 665 666 pr->scr_stat = 0; 667 pr->scr_err = 0; 668 pr->scr_act = 0; 669 pr->tfdata = 0x7F; 670 pr->sig = 0xFFFFFFFF; 671 pr->cmd_issue = 0; 672 d->busy_slot = -1; 673 d->init_d2h_sent = false; 674 675 ide_state = &s->dev[port].port.ifs[0]; 676 if (!ide_state->blk) { 677 return; 678 } 679 680 /* reset ncq queue */ 681 for (i = 0; i < AHCI_MAX_CMDS; i++) { 682 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 683 ncq_tfs->halt = false; 684 if (!ncq_tfs->used) { 685 continue; 686 } 687 688 if (ncq_tfs->aiocb) { 689 blk_aio_cancel(ncq_tfs->aiocb); 690 ncq_tfs->aiocb = NULL; 691 } 692 693 /* Maybe we just finished the request thanks to blk_aio_cancel() */ 694 if (!ncq_tfs->used) { 695 continue; 696 } 697 698 qemu_sglist_destroy(&ncq_tfs->sglist); 699 ncq_tfs->used = 0; 700 } 701 702 s->dev[port].port_state = STATE_RUN; 703 if (ide_state->drive_kind == IDE_CD) { 704 ahci_set_signature(d, SATA_SIGNATURE_CDROM); 705 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 706 } else { 707 ahci_set_signature(d, SATA_SIGNATURE_DISK); 708 ide_state->status = SEEK_STAT | WRERR_STAT; 709 } 710 711 ide_state->error = 1; 712 ahci_init_d2h(d); 713 } 714 715 /* Buffer pretty output based on a raw FIS structure. */ 716 static char *ahci_pretty_buffer_fis(const uint8_t *fis, int cmd_len) 717 { 718 int i; 719 GString *s = g_string_new("FIS:"); 720 721 for (i = 0; i < cmd_len; i++) { 722 if ((i & 0xf) == 0) { 723 g_string_append_printf(s, "\n0x%02x: ", i); 724 } 725 g_string_append_printf(s, "%02x ", fis[i]); 726 } 727 g_string_append_c(s, '\n'); 728 729 return g_string_free(s, FALSE); 730 } 731 732 static bool ahci_map_fis_address(AHCIDevice *ad) 733 { 734 AHCIPortRegs *pr = &ad->port_regs; 735 map_page(ad->hba->as, &ad->res_fis, 736 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 737 if (ad->res_fis != NULL) { 738 pr->cmd |= PORT_CMD_FIS_ON; 739 return true; 740 } 741 742 pr->cmd &= ~PORT_CMD_FIS_ON; 743 return false; 744 } 745 746 static void ahci_unmap_fis_address(AHCIDevice *ad) 747 { 748 if (ad->res_fis == NULL) { 749 trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no); 750 return; 751 } 752 ad->port_regs.cmd &= ~PORT_CMD_FIS_ON; 753 dma_memory_unmap(ad->hba->as, ad->res_fis, 256, 754 DMA_DIRECTION_FROM_DEVICE, 256); 755 ad->res_fis = NULL; 756 } 757 758 static bool ahci_map_clb_address(AHCIDevice *ad) 759 { 760 AHCIPortRegs *pr = &ad->port_regs; 761 ad->cur_cmd = NULL; 762 map_page(ad->hba->as, &ad->lst, 763 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 764 if (ad->lst != NULL) { 765 pr->cmd |= PORT_CMD_LIST_ON; 766 return true; 767 } 768 769 pr->cmd &= ~PORT_CMD_LIST_ON; 770 return false; 771 } 772 773 static void ahci_unmap_clb_address(AHCIDevice *ad) 774 { 775 if (ad->lst == NULL) { 776 trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no); 777 return; 778 } 779 ad->port_regs.cmd &= ~PORT_CMD_LIST_ON; 780 dma_memory_unmap(ad->hba->as, ad->lst, 1024, 781 DMA_DIRECTION_FROM_DEVICE, 1024); 782 ad->lst = NULL; 783 } 784 785 static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs) 786 { 787 AHCIDevice *ad = ncq_tfs->drive; 788 AHCIPortRegs *pr = &ad->port_regs; 789 IDEState *ide_state; 790 SDBFIS *sdb_fis; 791 792 if (!ad->res_fis || 793 !(pr->cmd & PORT_CMD_FIS_RX)) { 794 return; 795 } 796 797 sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS]; 798 ide_state = &ad->port.ifs[0]; 799 800 sdb_fis->type = SATA_FIS_TYPE_SDB; 801 /* Interrupt pending & Notification bit */ 802 sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */ 803 sdb_fis->status = ide_state->status & 0x77; 804 sdb_fis->error = ide_state->error; 805 /* update SAct field in SDB_FIS */ 806 sdb_fis->payload = cpu_to_le32(ad->finished); 807 808 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */ 809 pr->tfdata = (ad->port.ifs[0].error << 8) | 810 (ad->port.ifs[0].status & 0x77) | 811 (pr->tfdata & 0x88); 812 pr->scr_act &= ~ad->finished; 813 ad->finished = 0; 814 815 /* 816 * TFES IRQ is always raised if ERR_STAT is set, regardless of I bit. 817 * If ERR_STAT is not set, trigger SDBS IRQ if interrupt bit is set 818 * (which currently, it always is). 819 */ 820 if (sdb_fis->status & ERR_STAT) { 821 ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_TFES); 822 } else if (sdb_fis->flags & 0x40) { 823 ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS); 824 } 825 } 826 827 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i) 828 { 829 AHCIPortRegs *pr = &ad->port_regs; 830 uint8_t *pio_fis; 831 IDEState *s = &ad->port.ifs[0]; 832 833 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 834 return; 835 } 836 837 pio_fis = &ad->res_fis[RES_FIS_PSFIS]; 838 839 pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP; 840 pio_fis[1] = (pio_fis_i ? (1 << 6) : 0); 841 pio_fis[2] = s->status; 842 pio_fis[3] = s->error; 843 844 pio_fis[4] = s->sector; 845 pio_fis[5] = s->lcyl; 846 pio_fis[6] = s->hcyl; 847 pio_fis[7] = s->select; 848 pio_fis[8] = s->hob_sector; 849 pio_fis[9] = s->hob_lcyl; 850 pio_fis[10] = s->hob_hcyl; 851 pio_fis[11] = 0; 852 pio_fis[12] = s->nsector & 0xFF; 853 pio_fis[13] = (s->nsector >> 8) & 0xFF; 854 pio_fis[14] = 0; 855 pio_fis[15] = s->status; 856 pio_fis[16] = len & 255; 857 pio_fis[17] = len >> 8; 858 pio_fis[18] = 0; 859 pio_fis[19] = 0; 860 861 /* Update shadow registers: */ 862 pr->tfdata = (ad->port.ifs[0].error << 8) | 863 ad->port.ifs[0].status; 864 865 if (pio_fis[2] & ERR_STAT) { 866 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); 867 } 868 } 869 870 static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i) 871 { 872 AHCIPortRegs *pr = &ad->port_regs; 873 uint8_t *d2h_fis; 874 int i; 875 IDEState *s = &ad->port.ifs[0]; 876 877 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 878 return false; 879 } 880 881 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 882 883 d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H; 884 d2h_fis[1] = d2h_fis_i ? (1 << 6) : 0; /* interrupt bit */ 885 d2h_fis[2] = s->status; 886 d2h_fis[3] = s->error; 887 888 d2h_fis[4] = s->sector; 889 d2h_fis[5] = s->lcyl; 890 d2h_fis[6] = s->hcyl; 891 d2h_fis[7] = s->select; 892 d2h_fis[8] = s->hob_sector; 893 d2h_fis[9] = s->hob_lcyl; 894 d2h_fis[10] = s->hob_hcyl; 895 d2h_fis[11] = 0; 896 d2h_fis[12] = s->nsector & 0xFF; 897 d2h_fis[13] = (s->nsector >> 8) & 0xFF; 898 for (i = 14; i < 20; i++) { 899 d2h_fis[i] = 0; 900 } 901 902 /* Update shadow registers: */ 903 pr->tfdata = (ad->port.ifs[0].error << 8) | 904 ad->port.ifs[0].status; 905 906 /* TFES IRQ is always raised if ERR_STAT is set, regardless of I bit. */ 907 if (d2h_fis[2] & ERR_STAT) { 908 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); 909 } else if (d2h_fis_i) { 910 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); 911 } 912 913 return true; 914 } 915 916 static int prdt_tbl_entry_size(const AHCI_SG *tbl) 917 { 918 /* flags_size is zero-based */ 919 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1; 920 } 921 922 /** 923 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist. 924 * @ad: The AHCIDevice for whom we are building the SGList. 925 * @sglist: The SGList target to add PRD entries to. 926 * @cmd: The AHCI Command Header that describes where the PRDT is. 927 * @limit: The remaining size of the S/ATA transaction, in bytes. 928 * @offset: The number of bytes already transferred, in bytes. 929 * 930 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of 931 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop 932 * building the sglist from the PRDT as soon as we hit @limit bytes, 933 * which is <= INT32_MAX/2GiB. 934 */ 935 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, 936 AHCICmdHdr *cmd, int64_t limit, uint64_t offset) 937 { 938 uint16_t opts = le16_to_cpu(cmd->opts); 939 uint16_t prdtl = le16_to_cpu(cmd->prdtl); 940 uint64_t cfis_addr = le64_to_cpu(cmd->tbl_addr); 941 uint64_t prdt_addr = cfis_addr + 0x80; 942 dma_addr_t prdt_len = (prdtl * sizeof(AHCI_SG)); 943 dma_addr_t real_prdt_len = prdt_len; 944 uint8_t *prdt; 945 int i; 946 int r = 0; 947 uint64_t sum = 0; 948 int off_idx = -1; 949 int64_t off_pos = -1; 950 int tbl_entry_size; 951 IDEBus *bus = &ad->port; 952 BusState *qbus = BUS(bus); 953 954 trace_ahci_populate_sglist(ad->hba, ad->port_no); 955 956 if (!prdtl) { 957 trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts); 958 return -1; 959 } 960 961 /* map PRDT */ 962 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, 963 DMA_DIRECTION_TO_DEVICE, 964 MEMTXATTRS_UNSPECIFIED))){ 965 trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no); 966 return -1; 967 } 968 969 if (prdt_len < real_prdt_len) { 970 trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no); 971 r = -1; 972 goto out; 973 } 974 975 /* Get entries in the PRDT, init a qemu sglist accordingly */ 976 if (prdtl > 0) { 977 AHCI_SG *tbl = (AHCI_SG *)prdt; 978 sum = 0; 979 for (i = 0; i < prdtl; i++) { 980 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]); 981 if (offset < (sum + tbl_entry_size)) { 982 off_idx = i; 983 off_pos = offset - sum; 984 break; 985 } 986 sum += tbl_entry_size; 987 } 988 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { 989 trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no, 990 off_idx, off_pos); 991 r = -1; 992 goto out; 993 } 994 995 qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx), 996 ad->hba->as); 997 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos, 998 MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos, 999 limit)); 1000 1001 for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) { 1002 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 1003 MIN(prdt_tbl_entry_size(&tbl[i]), 1004 limit - sglist->size)); 1005 } 1006 } 1007 1008 out: 1009 dma_memory_unmap(ad->hba->as, prdt, prdt_len, 1010 DMA_DIRECTION_TO_DEVICE, prdt_len); 1011 return r; 1012 } 1013 1014 static void ncq_err(NCQTransferState *ncq_tfs) 1015 { 1016 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 1017 1018 ide_state->error = ABRT_ERR; 1019 ide_state->status = READY_STAT | ERR_STAT; 1020 qemu_sglist_destroy(&ncq_tfs->sglist); 1021 ncq_tfs->used = 0; 1022 } 1023 1024 static void ncq_finish(NCQTransferState *ncq_tfs) 1025 { 1026 /* If we didn't error out, set our finished bit. Errored commands 1027 * do not get a bit set for the SDB FIS ACT register, nor do they 1028 * clear the outstanding bit in scr_act (PxSACT). */ 1029 if (ncq_tfs->used) { 1030 ncq_tfs->drive->finished |= (1 << ncq_tfs->tag); 1031 } 1032 1033 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs); 1034 1035 trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, 1036 ncq_tfs->tag); 1037 1038 block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk), 1039 &ncq_tfs->acct); 1040 qemu_sglist_destroy(&ncq_tfs->sglist); 1041 ncq_tfs->used = 0; 1042 } 1043 1044 static void ncq_cb(void *opaque, int ret) 1045 { 1046 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 1047 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 1048 1049 ncq_tfs->aiocb = NULL; 1050 1051 if (ret < 0) { 1052 bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED; 1053 BlockErrorAction action = blk_get_error_action(ide_state->blk, 1054 is_read, -ret); 1055 if (action == BLOCK_ERROR_ACTION_STOP) { 1056 ncq_tfs->halt = true; 1057 ide_state->bus->error_status = IDE_RETRY_HBA; 1058 } else if (action == BLOCK_ERROR_ACTION_REPORT) { 1059 ncq_err(ncq_tfs); 1060 } 1061 blk_error_action(ide_state->blk, action, is_read, -ret); 1062 } else { 1063 ide_state->status = READY_STAT | SEEK_STAT; 1064 } 1065 1066 if (!ncq_tfs->halt) { 1067 ncq_finish(ncq_tfs); 1068 } 1069 } 1070 1071 static int is_ncq(uint8_t ata_cmd) 1072 { 1073 /* Based on SATA 3.2 section 13.6.3.2 */ 1074 switch (ata_cmd) { 1075 case READ_FPDMA_QUEUED: 1076 case WRITE_FPDMA_QUEUED: 1077 case NCQ_NON_DATA: 1078 case RECEIVE_FPDMA_QUEUED: 1079 case SEND_FPDMA_QUEUED: 1080 return 1; 1081 default: 1082 return 0; 1083 } 1084 } 1085 1086 static void execute_ncq_command(NCQTransferState *ncq_tfs) 1087 { 1088 AHCIDevice *ad = ncq_tfs->drive; 1089 IDEState *ide_state = &ad->port.ifs[0]; 1090 int port = ad->port_no; 1091 1092 g_assert(is_ncq(ncq_tfs->cmd)); 1093 ncq_tfs->halt = false; 1094 1095 switch (ncq_tfs->cmd) { 1096 case READ_FPDMA_QUEUED: 1097 trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag, 1098 ncq_tfs->sector_count, ncq_tfs->lba); 1099 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 1100 &ncq_tfs->sglist, BLOCK_ACCT_READ); 1101 ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist, 1102 ncq_tfs->lba << BDRV_SECTOR_BITS, 1103 BDRV_SECTOR_SIZE, 1104 ncq_cb, ncq_tfs); 1105 break; 1106 case WRITE_FPDMA_QUEUED: 1107 trace_execute_ncq_command_write(ad->hba, port, ncq_tfs->tag, 1108 ncq_tfs->sector_count, ncq_tfs->lba); 1109 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 1110 &ncq_tfs->sglist, BLOCK_ACCT_WRITE); 1111 ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist, 1112 ncq_tfs->lba << BDRV_SECTOR_BITS, 1113 BDRV_SECTOR_SIZE, 1114 ncq_cb, ncq_tfs); 1115 break; 1116 default: 1117 trace_execute_ncq_command_unsup(ad->hba, port, 1118 ncq_tfs->tag, ncq_tfs->cmd); 1119 ncq_err(ncq_tfs); 1120 } 1121 } 1122 1123 1124 static void process_ncq_command(AHCIState *s, int port, const uint8_t *cmd_fis, 1125 uint8_t slot) 1126 { 1127 AHCIDevice *ad = &s->dev[port]; 1128 const NCQFrame *ncq_fis = (NCQFrame *)cmd_fis; 1129 uint8_t tag = ncq_fis->tag >> 3; 1130 NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag]; 1131 size_t size; 1132 1133 g_assert(is_ncq(ncq_fis->command)); 1134 if (ncq_tfs->used) { 1135 /* error - already in use */ 1136 qemu_log_mask(LOG_GUEST_ERROR, "%s: tag %d already used\n", 1137 __func__, tag); 1138 return; 1139 } 1140 1141 /* 1142 * A NCQ command clears the bit in PxCI after the command has been QUEUED 1143 * successfully (ERROR not set, BUSY and DRQ cleared). 1144 * 1145 * For NCQ commands, PxCI will always be cleared here. 1146 * 1147 * (Once the NCQ command is COMPLETED, the device will send a SDB FIS with 1148 * the interrupt bit set, which will clear PxSACT and raise an interrupt.) 1149 */ 1150 ahci_clear_cmd_issue(ad, slot); 1151 1152 /* 1153 * In reality, for NCQ commands, PxCI is cleared after receiving a D2H FIS 1154 * without the interrupt bit set, but since ahci_write_fis_d2h() can raise 1155 * an IRQ on error, we need to call them in reverse order. 1156 */ 1157 ahci_write_fis_d2h(ad, false); 1158 1159 ncq_tfs->used = 1; 1160 ncq_tfs->drive = ad; 1161 ncq_tfs->slot = slot; 1162 ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot]; 1163 ncq_tfs->cmd = ncq_fis->command; 1164 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 1165 ((uint64_t)ncq_fis->lba4 << 32) | 1166 ((uint64_t)ncq_fis->lba3 << 24) | 1167 ((uint64_t)ncq_fis->lba2 << 16) | 1168 ((uint64_t)ncq_fis->lba1 << 8) | 1169 (uint64_t)ncq_fis->lba0; 1170 ncq_tfs->tag = tag; 1171 1172 /* Sanity-check the NCQ packet */ 1173 if (tag != slot) { 1174 trace_process_ncq_command_mismatch(s, port, tag, slot); 1175 } 1176 1177 if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) { 1178 trace_process_ncq_command_aux(s, port, tag); 1179 } 1180 if (ncq_fis->prio || ncq_fis->icc) { 1181 trace_process_ncq_command_prioicc(s, port, tag); 1182 } 1183 if (ncq_fis->fua & NCQ_FIS_FUA_MASK) { 1184 trace_process_ncq_command_fua(s, port, tag); 1185 } 1186 if (ncq_fis->tag & NCQ_FIS_RARC_MASK) { 1187 trace_process_ncq_command_rarc(s, port, tag); 1188 } 1189 1190 ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) | 1191 ncq_fis->sector_count_low); 1192 if (!ncq_tfs->sector_count) { 1193 ncq_tfs->sector_count = 0x10000; 1194 } 1195 size = ncq_tfs->sector_count * BDRV_SECTOR_SIZE; 1196 ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0); 1197 1198 if (ncq_tfs->sglist.size < size) { 1199 error_report("ahci: PRDT length for NCQ command (0x" DMA_ADDR_FMT ") " 1200 "is smaller than the requested size (0x%zx)", 1201 ncq_tfs->sglist.size, size); 1202 ncq_err(ncq_tfs); 1203 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS); 1204 return; 1205 } else if (ncq_tfs->sglist.size != size) { 1206 trace_process_ncq_command_large(s, port, tag, 1207 ncq_tfs->sglist.size, size); 1208 } 1209 1210 trace_process_ncq_command(s, port, tag, 1211 ncq_fis->command, 1212 ncq_tfs->lba, 1213 ncq_tfs->lba + ncq_tfs->sector_count - 1); 1214 execute_ncq_command(ncq_tfs); 1215 } 1216 1217 static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot) 1218 { 1219 if (port >= s->ports || slot >= AHCI_MAX_CMDS) { 1220 return NULL; 1221 } 1222 1223 return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL; 1224 } 1225 1226 static void handle_reg_h2d_fis(AHCIState *s, int port, 1227 uint8_t slot, const uint8_t *cmd_fis) 1228 { 1229 IDEState *ide_state = &s->dev[port].port.ifs[0]; 1230 AHCICmdHdr *cmd = get_cmd_header(s, port, slot); 1231 AHCIDevice *ad = &s->dev[port]; 1232 uint16_t opts = le16_to_cpu(cmd->opts); 1233 1234 if (cmd_fis[1] & 0x0F) { 1235 trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1], 1236 cmd_fis[2], cmd_fis[3]); 1237 return; 1238 } 1239 1240 if (cmd_fis[1] & 0x70) { 1241 trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1], 1242 cmd_fis[2], cmd_fis[3]); 1243 return; 1244 } 1245 1246 if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) { 1247 switch (s->dev[port].port_state) { 1248 case STATE_RUN: 1249 if (cmd_fis[15] & ATA_SRST) { 1250 s->dev[port].port_state = STATE_RESET; 1251 /* 1252 * When setting SRST in the first H2D FIS in the reset sequence, 1253 * the device does not send a D2H FIS. Host software thus has to 1254 * set the "Clear Busy upon R_OK" bit such that PxCI (and BUSY) 1255 * gets cleared. See AHCI 1.3.1, section 10.4.1 Software Reset. 1256 */ 1257 if (opts & AHCI_CMD_CLR_BUSY) { 1258 ahci_clear_cmd_issue(ad, slot); 1259 } 1260 } 1261 break; 1262 case STATE_RESET: 1263 if (!(cmd_fis[15] & ATA_SRST)) { 1264 /* 1265 * When clearing SRST in the second H2D FIS in the reset 1266 * sequence, the device will execute diagnostics. When this is 1267 * done, the device will send a D2H FIS with the good status. 1268 * See SATA 3.5a Gold, section 11.4 Software reset protocol. 1269 * 1270 * This D2H FIS is the first D2H FIS received from the device, 1271 * and is received regardless if the reset was performed by a 1272 * COMRESET or by setting and clearing the SRST bit. Therefore, 1273 * the logic for this is found in ahci_init_d2h() and not here. 1274 */ 1275 ahci_reset_port(s, port); 1276 } 1277 break; 1278 } 1279 return; 1280 } 1281 1282 /* Check for NCQ command */ 1283 if (is_ncq(cmd_fis[2])) { 1284 process_ncq_command(s, port, cmd_fis, slot); 1285 return; 1286 } 1287 1288 /* Decompose the FIS: 1289 * AHCI does not interpret FIS packets, it only forwards them. 1290 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets. 1291 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets. 1292 * 1293 * ATA4 describes sector number for LBA28/CHS commands. 1294 * ATA6 describes sector number for LBA48 commands. 1295 * ATA8 deprecates CHS fully, describing only LBA28/48. 1296 * 1297 * We dutifully convert the FIS into IDE registers, and allow the 1298 * core layer to interpret them as needed. */ 1299 ide_state->feature = cmd_fis[3]; 1300 ide_state->sector = cmd_fis[4]; /* LBA 7:0 */ 1301 ide_state->lcyl = cmd_fis[5]; /* LBA 15:8 */ 1302 ide_state->hcyl = cmd_fis[6]; /* LBA 23:16 */ 1303 ide_state->select = cmd_fis[7]; /* LBA 27:24 (LBA28) */ 1304 ide_state->hob_sector = cmd_fis[8]; /* LBA 31:24 */ 1305 ide_state->hob_lcyl = cmd_fis[9]; /* LBA 39:32 */ 1306 ide_state->hob_hcyl = cmd_fis[10]; /* LBA 47:40 */ 1307 ide_state->hob_feature = cmd_fis[11]; 1308 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 1309 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */ 1310 /* 15: Only valid when UPDATE_COMMAND not set. */ 1311 1312 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 1313 * table to ide_state->io_buffer */ 1314 if (opts & AHCI_CMD_ATAPI) { 1315 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 1316 if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP)) { 1317 char *pretty_fis = ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10); 1318 trace_handle_reg_h2d_fis_dump(s, port, pretty_fis); 1319 g_free(pretty_fis); 1320 } 1321 } 1322 1323 ide_state->error = 0; 1324 s->dev[port].done_first_drq = false; 1325 /* Reset transferred byte counter */ 1326 cmd->status = 0; 1327 1328 /* 1329 * A non-NCQ command clears the bit in PxCI after the command has COMPLETED 1330 * successfully (ERROR not set, BUSY and DRQ cleared). 1331 * 1332 * For non-NCQ commands, PxCI will always be cleared by ahci_cmd_done(). 1333 */ 1334 ad->busy_slot = slot; 1335 1336 /* We're ready to process the command in FIS byte 2. */ 1337 ide_bus_exec_cmd(&s->dev[port].port, cmd_fis[2]); 1338 } 1339 1340 static void handle_cmd(AHCIState *s, int port, uint8_t slot) 1341 { 1342 IDEState *ide_state; 1343 uint64_t tbl_addr; 1344 AHCICmdHdr *cmd; 1345 uint8_t *cmd_fis; 1346 dma_addr_t cmd_len; 1347 1348 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 1349 /* Engine currently busy, try again later */ 1350 trace_handle_cmd_busy(s, port); 1351 return; 1352 } 1353 1354 if (!s->dev[port].lst) { 1355 trace_handle_cmd_nolist(s, port); 1356 return; 1357 } 1358 cmd = get_cmd_header(s, port, slot); 1359 /* remember current slot handle for later */ 1360 s->dev[port].cur_cmd = cmd; 1361 1362 /* The device we are working for */ 1363 ide_state = &s->dev[port].port.ifs[0]; 1364 if (!ide_state->blk) { 1365 trace_handle_cmd_badport(s, port); 1366 return; 1367 } 1368 1369 tbl_addr = le64_to_cpu(cmd->tbl_addr); 1370 cmd_len = 0x80; 1371 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, 1372 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); 1373 if (!cmd_fis) { 1374 trace_handle_cmd_badfis(s, port); 1375 return; 1376 } else if (cmd_len != 0x80) { 1377 ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS); 1378 trace_handle_cmd_badmap(s, port, cmd_len); 1379 goto out; 1380 } 1381 if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP)) { 1382 char *pretty_fis = ahci_pretty_buffer_fis(cmd_fis, 0x80); 1383 trace_handle_cmd_fis_dump(s, port, pretty_fis); 1384 g_free(pretty_fis); 1385 } 1386 switch (cmd_fis[0]) { 1387 case SATA_FIS_TYPE_REGISTER_H2D: 1388 handle_reg_h2d_fis(s, port, slot, cmd_fis); 1389 break; 1390 default: 1391 trace_handle_cmd_unhandled_fis(s, port, 1392 cmd_fis[0], cmd_fis[1], cmd_fis[2]); 1393 break; 1394 } 1395 1396 out: 1397 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_TO_DEVICE, 1398 cmd_len); 1399 } 1400 1401 /* Transfer PIO data between RAM and device */ 1402 static void ahci_pio_transfer(const IDEDMA *dma) 1403 { 1404 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1405 IDEState *s = &ad->port.ifs[0]; 1406 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 1407 /* write == ram -> device */ 1408 uint16_t opts = le16_to_cpu(ad->cur_cmd->opts); 1409 int is_write = opts & AHCI_CMD_WRITE; 1410 int is_atapi = opts & AHCI_CMD_ATAPI; 1411 int has_sglist = 0; 1412 bool pio_fis_i; 1413 1414 /* The PIO Setup FIS is received prior to transfer, but the interrupt 1415 * is only triggered after data is received. 1416 * 1417 * The device only sets the 'I' bit in the PIO Setup FIS for device->host 1418 * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after 1419 * the first (see "DPIOO1"). The latter is consistent with the spec's 1420 * description of the PACKET protocol, where the command part of ATAPI requests 1421 * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests 1422 * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs. 1423 */ 1424 pio_fis_i = ad->done_first_drq || (!is_atapi && !is_write); 1425 ahci_write_fis_pio(ad, size, pio_fis_i); 1426 1427 if (is_atapi && !ad->done_first_drq) { 1428 /* already prepopulated iobuffer */ 1429 goto out; 1430 } 1431 1432 if (ahci_dma_prepare_buf(dma, size)) { 1433 has_sglist = 1; 1434 } 1435 1436 trace_ahci_pio_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read", 1437 size, is_atapi ? "atapi" : "ata", 1438 has_sglist ? "" : "o"); 1439 1440 if (has_sglist && size) { 1441 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 1442 1443 if (is_write) { 1444 dma_buf_write(s->data_ptr, size, NULL, &s->sg, attrs); 1445 } else { 1446 dma_buf_read(s->data_ptr, size, NULL, &s->sg, attrs); 1447 } 1448 } 1449 1450 /* Update number of transferred bytes, destroy sglist */ 1451 dma_buf_commit(s, size); 1452 1453 out: 1454 /* declare that we processed everything */ 1455 s->data_ptr = s->data_end; 1456 1457 ad->done_first_drq = true; 1458 if (pio_fis_i) { 1459 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS); 1460 } 1461 } 1462 1463 static void ahci_start_dma(const IDEDMA *dma, IDEState *s, 1464 BlockCompletionFunc *dma_cb) 1465 { 1466 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1467 trace_ahci_start_dma(ad->hba, ad->port_no); 1468 s->io_buffer_offset = 0; 1469 dma_cb(s, 0); 1470 } 1471 1472 static void ahci_restart_dma(const IDEDMA *dma) 1473 { 1474 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */ 1475 } 1476 1477 /** 1478 * IDE/PIO restarts are handled by the core layer, but NCQ commands 1479 * need an extra kick from the AHCI HBA. 1480 */ 1481 static void ahci_restart(const IDEDMA *dma) 1482 { 1483 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1484 int i; 1485 1486 for (i = 0; i < AHCI_MAX_CMDS; i++) { 1487 NCQTransferState *ncq_tfs = &ad->ncq_tfs[i]; 1488 if (ncq_tfs->halt) { 1489 execute_ncq_command(ncq_tfs); 1490 } 1491 } 1492 } 1493 1494 /** 1495 * Called in DMA and PIO R/W chains to read the PRDT. 1496 * Not shared with NCQ pathways. 1497 */ 1498 static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit) 1499 { 1500 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1501 IDEState *s = &ad->port.ifs[0]; 1502 1503 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, 1504 limit, s->io_buffer_offset) == -1) { 1505 trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no); 1506 return -1; 1507 } 1508 s->io_buffer_size = s->sg.size; 1509 1510 trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size); 1511 return s->io_buffer_size; 1512 } 1513 1514 /** 1515 * Updates the command header with a bytes-read value. 1516 * Called via dma_buf_commit, for both DMA and PIO paths. 1517 * sglist destruction is handled within dma_buf_commit. 1518 */ 1519 static void ahci_commit_buf(const IDEDMA *dma, uint32_t tx_bytes) 1520 { 1521 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1522 1523 tx_bytes += le32_to_cpu(ad->cur_cmd->status); 1524 ad->cur_cmd->status = cpu_to_le32(tx_bytes); 1525 } 1526 1527 static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write) 1528 { 1529 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1530 IDEState *s = &ad->port.ifs[0]; 1531 uint8_t *p = s->io_buffer + s->io_buffer_index; 1532 int l = s->io_buffer_size - s->io_buffer_index; 1533 1534 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) { 1535 return 0; 1536 } 1537 1538 if (is_write) { 1539 dma_buf_read(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED); 1540 } else { 1541 dma_buf_write(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED); 1542 } 1543 1544 /* free sglist, update byte count */ 1545 dma_buf_commit(s, l); 1546 s->io_buffer_index += l; 1547 1548 trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l); 1549 return 1; 1550 } 1551 1552 static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot) 1553 { 1554 IDEState *ide_state = &ad->port.ifs[0]; 1555 1556 if (!(ide_state->status & ERR_STAT) && 1557 !(ide_state->status & (BUSY_STAT | DRQ_STAT))) { 1558 ad->port_regs.cmd_issue &= ~(1 << slot); 1559 } 1560 } 1561 1562 /* Non-NCQ command is done - This function is never called for NCQ commands. */ 1563 static void ahci_cmd_done(const IDEDMA *dma) 1564 { 1565 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1566 IDEState *ide_state = &ad->port.ifs[0]; 1567 1568 trace_ahci_cmd_done(ad->hba, ad->port_no); 1569 1570 /* no longer busy */ 1571 if (ad->busy_slot != -1) { 1572 ahci_clear_cmd_issue(ad, ad->busy_slot); 1573 ad->busy_slot = -1; 1574 } 1575 1576 /* 1577 * In reality, for non-NCQ commands, PxCI is cleared after receiving a D2H 1578 * FIS with the interrupt bit set, but since ahci_write_fis_d2h() will raise 1579 * an IRQ, we need to call them in reverse order. 1580 */ 1581 ahci_write_fis_d2h(ad, true); 1582 1583 if (!(ide_state->status & ERR_STAT) && 1584 ad->port_regs.cmd_issue && !ad->check_bh) { 1585 ad->check_bh = qemu_bh_new_guarded(ahci_check_cmd_bh, ad, 1586 &ad->mem_reentrancy_guard); 1587 qemu_bh_schedule(ad->check_bh); 1588 } 1589 } 1590 1591 static void ahci_irq_set(void *opaque, int n, int level) 1592 { 1593 qemu_log_mask(LOG_UNIMP, "ahci: IRQ#%d level:%d\n", n, level); 1594 } 1595 1596 static const IDEDMAOps ahci_dma_ops = { 1597 .start_dma = ahci_start_dma, 1598 .restart = ahci_restart, 1599 .restart_dma = ahci_restart_dma, 1600 .pio_transfer = ahci_pio_transfer, 1601 .prepare_buf = ahci_dma_prepare_buf, 1602 .commit_buf = ahci_commit_buf, 1603 .rw_buf = ahci_dma_rw_buf, 1604 .cmd_done = ahci_cmd_done, 1605 }; 1606 1607 void ahci_init(AHCIState *s, DeviceState *qdev) 1608 { 1609 s->container = qdev; 1610 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1611 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, 1612 "ahci", AHCI_MEM_BAR_SIZE); 1613 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, 1614 "ahci-idp", 32); 1615 } 1616 1617 void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as) 1618 { 1619 qemu_irq *irqs; 1620 int i; 1621 1622 s->as = as; 1623 assert(s->ports > 0); 1624 s->dev = g_new0(AHCIDevice, s->ports); 1625 ahci_reg_init(s); 1626 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1627 for (i = 0; i < s->ports; i++) { 1628 AHCIDevice *ad = &s->dev[i]; 1629 1630 ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1); 1631 ide_bus_init_output_irq(&ad->port, irqs[i]); 1632 1633 ad->hba = s; 1634 ad->port_no = i; 1635 ad->port.dma = &ad->dma; 1636 ad->port.dma->ops = &ahci_dma_ops; 1637 ide_bus_register_restart_cb(&ad->port); 1638 } 1639 g_free(irqs); 1640 } 1641 1642 void ahci_uninit(AHCIState *s) 1643 { 1644 int i, j; 1645 1646 for (i = 0; i < s->ports; i++) { 1647 AHCIDevice *ad = &s->dev[i]; 1648 1649 for (j = 0; j < 2; j++) { 1650 ide_exit(&ad->port.ifs[j]); 1651 } 1652 object_unparent(OBJECT(&ad->port)); 1653 } 1654 1655 g_free(s->dev); 1656 } 1657 1658 void ahci_reset(AHCIState *s) 1659 { 1660 AHCIPortRegs *pr; 1661 int i; 1662 1663 trace_ahci_reset(s); 1664 1665 s->control_regs.irqstatus = 0; 1666 /* AHCI Enable (AE) 1667 * The implementation of this bit is dependent upon the value of the 1668 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and 1669 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be 1670 * read-only and shall have a reset value of '1'. 1671 * 1672 * We set HOST_CAP_AHCI so we must enable AHCI at reset. 1673 */ 1674 s->control_regs.ghc = HOST_CTL_AHCI_EN; 1675 1676 for (i = 0; i < s->ports; i++) { 1677 pr = &s->dev[i].port_regs; 1678 pr->irq_stat = 0; 1679 pr->irq_mask = 0; 1680 pr->scr_ctl = 0; 1681 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1682 ahci_reset_port(s, i); 1683 } 1684 } 1685 1686 static const VMStateDescription vmstate_ncq_tfs = { 1687 .name = "ncq state", 1688 .version_id = 1, 1689 .fields = (const VMStateField[]) { 1690 VMSTATE_UINT32(sector_count, NCQTransferState), 1691 VMSTATE_UINT64(lba, NCQTransferState), 1692 VMSTATE_UINT8(tag, NCQTransferState), 1693 VMSTATE_UINT8(cmd, NCQTransferState), 1694 VMSTATE_UINT8(slot, NCQTransferState), 1695 VMSTATE_BOOL(used, NCQTransferState), 1696 VMSTATE_BOOL(halt, NCQTransferState), 1697 VMSTATE_END_OF_LIST() 1698 }, 1699 }; 1700 1701 static const VMStateDescription vmstate_ahci_device = { 1702 .name = "ahci port", 1703 .version_id = 1, 1704 .fields = (const VMStateField[]) { 1705 VMSTATE_IDE_BUS(port, AHCIDevice), 1706 VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice), 1707 VMSTATE_UINT32(port_state, AHCIDevice), 1708 VMSTATE_UINT32(finished, AHCIDevice), 1709 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), 1710 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), 1711 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), 1712 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), 1713 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), 1714 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), 1715 VMSTATE_UINT32(port_regs.cmd, AHCIDevice), 1716 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), 1717 VMSTATE_UINT32(port_regs.sig, AHCIDevice), 1718 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), 1719 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), 1720 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), 1721 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), 1722 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), 1723 VMSTATE_BOOL(done_first_drq, AHCIDevice), 1724 VMSTATE_INT32(busy_slot, AHCIDevice), 1725 VMSTATE_BOOL(init_d2h_sent, AHCIDevice), 1726 VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS, 1727 1, vmstate_ncq_tfs, NCQTransferState), 1728 VMSTATE_END_OF_LIST() 1729 }, 1730 }; 1731 1732 static int ahci_state_post_load(void *opaque, int version_id) 1733 { 1734 int i, j; 1735 struct AHCIDevice *ad; 1736 NCQTransferState *ncq_tfs; 1737 AHCIPortRegs *pr; 1738 AHCIState *s = opaque; 1739 1740 for (i = 0; i < s->ports; i++) { 1741 ad = &s->dev[i]; 1742 pr = &ad->port_regs; 1743 1744 if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) { 1745 error_report("AHCI: DMA engine should be off, but status bit " 1746 "indicates it is still running."); 1747 return -1; 1748 } 1749 if (!(pr->cmd & PORT_CMD_FIS_RX) && (pr->cmd & PORT_CMD_FIS_ON)) { 1750 error_report("AHCI: FIS RX engine should be off, but status bit " 1751 "indicates it is still running."); 1752 return -1; 1753 } 1754 1755 /* After a migrate, the DMA/FIS engines are "off" and 1756 * need to be conditionally restarted */ 1757 pr->cmd &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); 1758 if (ahci_cond_start_engines(ad) != 0) { 1759 return -1; 1760 } 1761 1762 for (j = 0; j < AHCI_MAX_CMDS; j++) { 1763 ncq_tfs = &ad->ncq_tfs[j]; 1764 ncq_tfs->drive = ad; 1765 1766 if (ncq_tfs->used != ncq_tfs->halt) { 1767 return -1; 1768 } 1769 if (!ncq_tfs->halt) { 1770 continue; 1771 } 1772 if (!is_ncq(ncq_tfs->cmd)) { 1773 return -1; 1774 } 1775 if (ncq_tfs->slot != ncq_tfs->tag) { 1776 return -1; 1777 } 1778 /* If ncq_tfs->halt is justly set, the engine should be engaged, 1779 * and the command list buffer should be mapped. */ 1780 ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot); 1781 if (!ncq_tfs->cmdh) { 1782 return -1; 1783 } 1784 ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist, 1785 ncq_tfs->cmdh, 1786 ncq_tfs->sector_count * BDRV_SECTOR_SIZE, 1787 0); 1788 if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) { 1789 return -1; 1790 } 1791 } 1792 1793 1794 /* 1795 * If an error is present, ad->busy_slot will be valid and not -1. 1796 * In this case, an operation is waiting to resume and will re-check 1797 * for additional AHCI commands to execute upon completion. 1798 * 1799 * In the case where no error was present, busy_slot will be -1, 1800 * and we should check to see if there are additional commands waiting. 1801 */ 1802 if (ad->busy_slot == -1) { 1803 check_cmd(s, i); 1804 } else { 1805 /* We are in the middle of a command, and may need to access 1806 * the command header in guest memory again. */ 1807 if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) { 1808 return -1; 1809 } 1810 ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot); 1811 } 1812 } 1813 1814 return 0; 1815 } 1816 1817 const VMStateDescription vmstate_ahci = { 1818 .name = "ahci", 1819 .version_id = 1, 1820 .post_load = ahci_state_post_load, 1821 .fields = (const VMStateField[]) { 1822 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(dev, AHCIState, ports, 1823 vmstate_ahci_device, AHCIDevice), 1824 VMSTATE_UINT32(control_regs.cap, AHCIState), 1825 VMSTATE_UINT32(control_regs.ghc, AHCIState), 1826 VMSTATE_UINT32(control_regs.irqstatus, AHCIState), 1827 VMSTATE_UINT32(control_regs.impl, AHCIState), 1828 VMSTATE_UINT32(control_regs.version, AHCIState), 1829 VMSTATE_UINT32(idp_index, AHCIState), 1830 VMSTATE_UINT32_EQUAL(ports, AHCIState, NULL), 1831 VMSTATE_END_OF_LIST() 1832 }, 1833 }; 1834 1835 static const VMStateDescription vmstate_sysbus_ahci = { 1836 .name = "sysbus-ahci", 1837 .fields = (const VMStateField[]) { 1838 VMSTATE_AHCI(ahci, SysbusAHCIState), 1839 VMSTATE_END_OF_LIST() 1840 }, 1841 }; 1842 1843 static void sysbus_ahci_reset(DeviceState *dev) 1844 { 1845 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1846 1847 ahci_reset(&s->ahci); 1848 } 1849 1850 static void sysbus_ahci_init(Object *obj) 1851 { 1852 SysbusAHCIState *s = SYSBUS_AHCI(obj); 1853 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1854 1855 ahci_init(&s->ahci, DEVICE(obj)); 1856 1857 sysbus_init_mmio(sbd, &s->ahci.mem); 1858 sysbus_init_irq(sbd, &s->ahci.irq); 1859 } 1860 1861 static void sysbus_ahci_realize(DeviceState *dev, Error **errp) 1862 { 1863 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1864 1865 ahci_realize(&s->ahci, dev, &address_space_memory); 1866 } 1867 1868 static Property sysbus_ahci_properties[] = { 1869 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, ahci.ports, 1), 1870 DEFINE_PROP_END_OF_LIST(), 1871 }; 1872 1873 static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 1874 { 1875 DeviceClass *dc = DEVICE_CLASS(klass); 1876 1877 dc->realize = sysbus_ahci_realize; 1878 dc->vmsd = &vmstate_sysbus_ahci; 1879 device_class_set_props(dc, sysbus_ahci_properties); 1880 dc->reset = sysbus_ahci_reset; 1881 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1882 } 1883 1884 static const TypeInfo sysbus_ahci_info = { 1885 .name = TYPE_SYSBUS_AHCI, 1886 .parent = TYPE_SYS_BUS_DEVICE, 1887 .instance_size = sizeof(SysbusAHCIState), 1888 .instance_init = sysbus_ahci_init, 1889 .class_init = sysbus_ahci_class_init, 1890 }; 1891 1892 static void sysbus_ahci_register_types(void) 1893 { 1894 type_register_static(&sysbus_ahci_info); 1895 } 1896 1897 type_init(sysbus_ahci_register_types) 1898 1899 void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd) 1900 { 1901 int i; 1902 1903 for (i = 0; i < ahci->ports; i++) { 1904 if (hd[i] == NULL) { 1905 continue; 1906 } 1907 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 1908 } 1909 } 1910